Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10082068 |
1 |
|
|
T22 |
47 |
|
T23 |
53539 |
|
T24 |
54 |
| auto[1] |
7965307 |
1 |
|
|
T22 |
3 |
|
T23 |
45774 |
|
T24 |
92 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17020405 |
1 |
|
|
T22 |
50 |
|
T23 |
93146 |
|
T24 |
138 |
| auto[1] |
1026970 |
1 |
|
|
T23 |
6167 |
|
T24 |
8 |
|
T26 |
194 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10030498 |
1 |
|
|
T22 |
43 |
|
T23 |
54624 |
|
T24 |
70 |
| auto[1] |
8016877 |
1 |
|
|
T22 |
7 |
|
T23 |
44689 |
|
T24 |
76 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3501760 |
1 |
|
|
T22 |
7 |
|
T23 |
18240 |
|
T24 |
22 |
| auto[1] |
auto[0] |
auto[1] |
514549 |
1 |
|
|
T23 |
2860 |
|
T24 |
1 |
|
T26 |
122 |
| auto[1] |
auto[1] |
auto[0] |
3488147 |
1 |
|
|
T23 |
20282 |
|
T24 |
46 |
|
T26 |
300 |
| auto[1] |
auto[1] |
auto[1] |
512421 |
1 |
|
|
T23 |
3307 |
|
T24 |
7 |
|
T26 |
72 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |