Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10025232 |
1 |
|
|
T22 |
43 |
|
T23 |
56842 |
|
T24 |
119 |
| auto[1] |
8022143 |
1 |
|
|
T22 |
7 |
|
T23 |
42471 |
|
T24 |
27 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17024240 |
1 |
|
|
T22 |
50 |
|
T23 |
93437 |
|
T24 |
144 |
| auto[1] |
1023135 |
1 |
|
|
T23 |
5876 |
|
T24 |
2 |
|
T26 |
145 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10062583 |
1 |
|
|
T22 |
49 |
|
T23 |
55963 |
|
T24 |
60 |
| auto[1] |
7984792 |
1 |
|
|
T22 |
1 |
|
T23 |
43350 |
|
T24 |
86 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3482383 |
1 |
|
|
T22 |
1 |
|
T23 |
20741 |
|
T24 |
70 |
| auto[1] |
auto[0] |
auto[1] |
511461 |
1 |
|
|
T23 |
3305 |
|
T24 |
2 |
|
T26 |
89 |
| auto[1] |
auto[1] |
auto[0] |
3479274 |
1 |
|
|
T23 |
16733 |
|
T24 |
14 |
|
T26 |
272 |
| auto[1] |
auto[1] |
auto[1] |
511674 |
1 |
|
|
T23 |
2571 |
|
T26 |
56 |
|
T30 |
54 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |