Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10021384 |
1 |
|
|
T22 |
23 |
|
T23 |
55276 |
|
T24 |
97 |
| auto[1] |
8025991 |
1 |
|
|
T22 |
27 |
|
T23 |
44037 |
|
T24 |
49 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17012533 |
1 |
|
|
T22 |
50 |
|
T23 |
93114 |
|
T24 |
138 |
| auto[1] |
1034842 |
1 |
|
|
T23 |
6199 |
|
T24 |
8 |
|
T26 |
171 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9982849 |
1 |
|
|
T22 |
50 |
|
T23 |
54551 |
|
T24 |
69 |
| auto[1] |
8064526 |
1 |
|
|
T23 |
44762 |
|
T24 |
77 |
|
T26 |
984 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3486789 |
1 |
|
|
T23 |
19975 |
|
T24 |
49 |
|
T26 |
456 |
| auto[1] |
auto[0] |
auto[1] |
511223 |
1 |
|
|
T23 |
3230 |
|
T24 |
3 |
|
T26 |
91 |
| auto[1] |
auto[1] |
auto[0] |
3542895 |
1 |
|
|
T23 |
18588 |
|
T24 |
20 |
|
T26 |
357 |
| auto[1] |
auto[1] |
auto[1] |
523619 |
1 |
|
|
T23 |
2969 |
|
T24 |
5 |
|
T26 |
80 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |