Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10047220 |
1 |
|
|
T22 |
27 |
|
T23 |
53767 |
|
T24 |
110 |
| auto[1] |
8000155 |
1 |
|
|
T22 |
23 |
|
T23 |
45546 |
|
T24 |
36 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14778830 |
1 |
|
|
T22 |
35 |
|
T23 |
80973 |
|
T24 |
86 |
| auto[1] |
3268545 |
1 |
|
|
T22 |
15 |
|
T23 |
18340 |
|
T24 |
60 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10052281 |
1 |
|
|
T22 |
30 |
|
T23 |
54443 |
|
T24 |
60 |
| auto[1] |
7995094 |
1 |
|
|
T22 |
20 |
|
T23 |
44870 |
|
T24 |
86 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2372809 |
1 |
|
|
T23 |
13070 |
|
T24 |
10 |
|
T26 |
246 |
| auto[1] |
auto[0] |
auto[1] |
1643068 |
1 |
|
|
T22 |
4 |
|
T23 |
8744 |
|
T24 |
55 |
| auto[1] |
auto[1] |
auto[0] |
2353740 |
1 |
|
|
T22 |
5 |
|
T23 |
13460 |
|
T24 |
16 |
| auto[1] |
auto[1] |
auto[1] |
1625477 |
1 |
|
|
T22 |
11 |
|
T23 |
9596 |
|
T24 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |