Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10078977 |
1 |
|
|
T22 |
46 |
|
T23 |
53178 |
|
T24 |
117 |
| auto[1] |
7968398 |
1 |
|
|
T22 |
4 |
|
T23 |
46135 |
|
T24 |
29 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14777986 |
1 |
|
|
T22 |
50 |
|
T23 |
81122 |
|
T24 |
115 |
| auto[1] |
3269389 |
1 |
|
|
T23 |
18191 |
|
T24 |
31 |
|
T26 |
514 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10056744 |
1 |
|
|
T22 |
44 |
|
T23 |
54826 |
|
T24 |
98 |
| auto[1] |
7990631 |
1 |
|
|
T22 |
6 |
|
T23 |
44487 |
|
T24 |
48 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2371899 |
1 |
|
|
T22 |
6 |
|
T23 |
13213 |
|
T24 |
11 |
| auto[1] |
auto[0] |
auto[1] |
1641673 |
1 |
|
|
T23 |
9101 |
|
T24 |
26 |
|
T26 |
317 |
| auto[1] |
auto[1] |
auto[0] |
2349343 |
1 |
|
|
T23 |
13083 |
|
T24 |
6 |
|
T26 |
227 |
| auto[1] |
auto[1] |
auto[1] |
1627716 |
1 |
|
|
T23 |
9090 |
|
T24 |
5 |
|
T26 |
197 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |