Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10033338 |
1 |
|
|
T22 |
30 |
|
T23 |
53892 |
|
T24 |
78 |
| auto[1] |
8014037 |
1 |
|
|
T22 |
20 |
|
T23 |
45421 |
|
T24 |
68 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14785464 |
1 |
|
|
T22 |
40 |
|
T23 |
80865 |
|
T24 |
97 |
| auto[1] |
3261911 |
1 |
|
|
T22 |
10 |
|
T23 |
18448 |
|
T24 |
49 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10063538 |
1 |
|
|
T22 |
36 |
|
T23 |
54489 |
|
T24 |
65 |
| auto[1] |
7983837 |
1 |
|
|
T22 |
14 |
|
T23 |
44824 |
|
T24 |
81 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2340866 |
1 |
|
|
T23 |
13012 |
|
T24 |
14 |
|
T26 |
295 |
| auto[1] |
auto[0] |
auto[1] |
1626090 |
1 |
|
|
T22 |
1 |
|
T23 |
9191 |
|
T24 |
24 |
| auto[1] |
auto[1] |
auto[0] |
2381060 |
1 |
|
|
T22 |
4 |
|
T23 |
13364 |
|
T24 |
18 |
| auto[1] |
auto[1] |
auto[1] |
1635821 |
1 |
|
|
T22 |
9 |
|
T23 |
9257 |
|
T24 |
25 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |