Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10021318 |
1 |
|
|
T22 |
30 |
|
T23 |
55625 |
|
T24 |
78 |
| auto[1] |
8026057 |
1 |
|
|
T22 |
20 |
|
T23 |
43688 |
|
T24 |
68 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14773878 |
1 |
|
|
T22 |
50 |
|
T23 |
81265 |
|
T24 |
118 |
| auto[1] |
3273497 |
1 |
|
|
T23 |
18048 |
|
T24 |
28 |
|
T26 |
314 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10053930 |
1 |
|
|
T22 |
43 |
|
T23 |
55038 |
|
T24 |
88 |
| auto[1] |
7993445 |
1 |
|
|
T22 |
7 |
|
T23 |
44275 |
|
T24 |
58 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2350858 |
1 |
|
|
T22 |
1 |
|
T23 |
13126 |
|
T24 |
17 |
| auto[1] |
auto[0] |
auto[1] |
1633516 |
1 |
|
|
T23 |
8962 |
|
T24 |
10 |
|
T26 |
162 |
| auto[1] |
auto[1] |
auto[0] |
2369090 |
1 |
|
|
T22 |
6 |
|
T23 |
13101 |
|
T24 |
13 |
| auto[1] |
auto[1] |
auto[1] |
1639981 |
1 |
|
|
T23 |
9086 |
|
T24 |
18 |
|
T26 |
152 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |