Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10048944 |
1 |
|
|
T22 |
43 |
|
T23 |
54674 |
|
T24 |
61 |
| auto[1] |
7998431 |
1 |
|
|
T22 |
7 |
|
T23 |
44639 |
|
T24 |
85 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14784354 |
1 |
|
|
T22 |
40 |
|
T23 |
81349 |
|
T24 |
124 |
| auto[1] |
3263021 |
1 |
|
|
T22 |
10 |
|
T23 |
17964 |
|
T24 |
22 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10071262 |
1 |
|
|
T22 |
30 |
|
T23 |
54678 |
|
T24 |
92 |
| auto[1] |
7976113 |
1 |
|
|
T22 |
20 |
|
T23 |
44635 |
|
T24 |
54 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2358147 |
1 |
|
|
T22 |
10 |
|
T23 |
12910 |
|
T24 |
7 |
| auto[1] |
auto[0] |
auto[1] |
1632067 |
1 |
|
|
T22 |
10 |
|
T23 |
8812 |
|
T24 |
15 |
| auto[1] |
auto[1] |
auto[0] |
2354945 |
1 |
|
|
T23 |
13761 |
|
T24 |
25 |
|
T26 |
248 |
| auto[1] |
auto[1] |
auto[1] |
1630954 |
1 |
|
|
T23 |
9152 |
|
T24 |
7 |
|
T26 |
218 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |