Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10037207 |
1 |
|
|
T22 |
50 |
|
T23 |
54643 |
|
T24 |
29 |
| auto[1] |
8010168 |
1 |
|
|
T23 |
44670 |
|
T24 |
117 |
|
T26 |
1307 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14768636 |
1 |
|
|
T22 |
44 |
|
T23 |
80477 |
|
T24 |
122 |
| auto[1] |
3278739 |
1 |
|
|
T22 |
6 |
|
T23 |
18836 |
|
T24 |
24 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10038639 |
1 |
|
|
T22 |
44 |
|
T23 |
53301 |
|
T24 |
93 |
| auto[1] |
8008736 |
1 |
|
|
T22 |
6 |
|
T23 |
46012 |
|
T24 |
53 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2369232 |
1 |
|
|
T23 |
13568 |
|
T24 |
4 |
|
T26 |
196 |
| auto[1] |
auto[0] |
auto[1] |
1638347 |
1 |
|
|
T22 |
6 |
|
T23 |
9272 |
|
T24 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2360765 |
1 |
|
|
T23 |
13608 |
|
T24 |
25 |
|
T26 |
431 |
| auto[1] |
auto[1] |
auto[1] |
1640392 |
1 |
|
|
T23 |
9564 |
|
T24 |
20 |
|
T26 |
454 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |