Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10040766 |
1 |
|
|
T22 |
43 |
|
T23 |
53611 |
|
T24 |
82 |
| auto[1] |
8006609 |
1 |
|
|
T22 |
7 |
|
T23 |
45702 |
|
T24 |
64 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14782599 |
1 |
|
|
T22 |
39 |
|
T23 |
81091 |
|
T24 |
108 |
| auto[1] |
3264776 |
1 |
|
|
T22 |
11 |
|
T23 |
18222 |
|
T24 |
38 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10054178 |
1 |
|
|
T22 |
31 |
|
T23 |
55297 |
|
T24 |
41 |
| auto[1] |
7993197 |
1 |
|
|
T22 |
19 |
|
T23 |
44016 |
|
T24 |
105 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2359423 |
1 |
|
|
T22 |
8 |
|
T23 |
12445 |
|
T24 |
27 |
| auto[1] |
auto[0] |
auto[1] |
1629554 |
1 |
|
|
T22 |
8 |
|
T23 |
8786 |
|
T24 |
27 |
| auto[1] |
auto[1] |
auto[0] |
2368998 |
1 |
|
|
T23 |
13349 |
|
T24 |
40 |
|
T26 |
262 |
| auto[1] |
auto[1] |
auto[1] |
1635222 |
1 |
|
|
T22 |
3 |
|
T23 |
9436 |
|
T24 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |