Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10081704 |
1 |
|
|
T22 |
42 |
|
T23 |
55588 |
|
T24 |
77 |
| auto[1] |
7965671 |
1 |
|
|
T22 |
8 |
|
T23 |
43725 |
|
T24 |
69 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14772726 |
1 |
|
|
T22 |
50 |
|
T23 |
80648 |
|
T24 |
106 |
| auto[1] |
3274649 |
1 |
|
|
T23 |
18665 |
|
T24 |
40 |
|
T26 |
444 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10063869 |
1 |
|
|
T22 |
50 |
|
T23 |
55352 |
|
T24 |
70 |
| auto[1] |
7983506 |
1 |
|
|
T23 |
43961 |
|
T24 |
76 |
|
T26 |
912 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2369173 |
1 |
|
|
T23 |
13262 |
|
T24 |
8 |
|
T26 |
227 |
| auto[1] |
auto[0] |
auto[1] |
1648025 |
1 |
|
|
T23 |
10049 |
|
T24 |
25 |
|
T26 |
216 |
| auto[1] |
auto[1] |
auto[0] |
2339684 |
1 |
|
|
T23 |
12034 |
|
T24 |
28 |
|
T26 |
241 |
| auto[1] |
auto[1] |
auto[1] |
1626624 |
1 |
|
|
T23 |
8616 |
|
T24 |
15 |
|
T26 |
228 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |