Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10046132 |
1 |
|
|
T22 |
39 |
|
T23 |
55106 |
|
T24 |
69 |
| auto[1] |
8001243 |
1 |
|
|
T22 |
11 |
|
T23 |
44207 |
|
T24 |
77 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14775479 |
1 |
|
|
T22 |
50 |
|
T23 |
80667 |
|
T24 |
121 |
| auto[1] |
3271896 |
1 |
|
|
T23 |
18646 |
|
T24 |
25 |
|
T26 |
429 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10050290 |
1 |
|
|
T22 |
44 |
|
T23 |
55149 |
|
T24 |
105 |
| auto[1] |
7997085 |
1 |
|
|
T22 |
6 |
|
T23 |
44164 |
|
T24 |
41 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2366942 |
1 |
|
|
T22 |
3 |
|
T23 |
12583 |
|
T24 |
11 |
| auto[1] |
auto[0] |
auto[1] |
1639020 |
1 |
|
|
T23 |
9224 |
|
T24 |
13 |
|
T26 |
260 |
| auto[1] |
auto[1] |
auto[0] |
2358247 |
1 |
|
|
T22 |
3 |
|
T23 |
12935 |
|
T24 |
5 |
| auto[1] |
auto[1] |
auto[1] |
1632876 |
1 |
|
|
T23 |
9422 |
|
T24 |
12 |
|
T26 |
169 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |