Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10064460 |
1 |
|
|
T22 |
46 |
|
T23 |
55052 |
|
T24 |
39 |
| auto[1] |
7982915 |
1 |
|
|
T22 |
4 |
|
T23 |
44261 |
|
T24 |
107 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14771414 |
1 |
|
|
T22 |
44 |
|
T23 |
80007 |
|
T24 |
108 |
| auto[1] |
3275961 |
1 |
|
|
T22 |
6 |
|
T23 |
19306 |
|
T24 |
38 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10039840 |
1 |
|
|
T22 |
44 |
|
T23 |
51126 |
|
T24 |
88 |
| auto[1] |
8007535 |
1 |
|
|
T22 |
6 |
|
T23 |
48187 |
|
T24 |
58 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2373906 |
1 |
|
|
T23 |
14627 |
|
T24 |
4 |
|
T26 |
253 |
| auto[1] |
auto[0] |
auto[1] |
1641641 |
1 |
|
|
T22 |
6 |
|
T23 |
9985 |
|
T24 |
9 |
| auto[1] |
auto[1] |
auto[0] |
2357668 |
1 |
|
|
T23 |
14254 |
|
T24 |
16 |
|
T26 |
274 |
| auto[1] |
auto[1] |
auto[1] |
1634320 |
1 |
|
|
T23 |
9321 |
|
T24 |
29 |
|
T26 |
278 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |