Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10065599 |
1 |
|
|
T22 |
46 |
|
T23 |
54177 |
|
T24 |
65 |
| auto[1] |
7981776 |
1 |
|
|
T22 |
4 |
|
T23 |
45136 |
|
T24 |
81 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14769978 |
1 |
|
|
T22 |
42 |
|
T23 |
81148 |
|
T24 |
114 |
| auto[1] |
3277397 |
1 |
|
|
T22 |
8 |
|
T23 |
18165 |
|
T24 |
32 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10025516 |
1 |
|
|
T22 |
36 |
|
T23 |
55797 |
|
T24 |
76 |
| auto[1] |
8021859 |
1 |
|
|
T22 |
14 |
|
T23 |
43516 |
|
T24 |
70 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2384924 |
1 |
|
|
T22 |
6 |
|
T23 |
12318 |
|
T24 |
16 |
| auto[1] |
auto[0] |
auto[1] |
1652240 |
1 |
|
|
T22 |
8 |
|
T23 |
8975 |
|
T24 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2359538 |
1 |
|
|
T23 |
13033 |
|
T24 |
22 |
|
T26 |
292 |
| auto[1] |
auto[1] |
auto[1] |
1625157 |
1 |
|
|
T23 |
9190 |
|
T24 |
26 |
|
T26 |
276 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |