Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10041184 |
1 |
|
|
T22 |
50 |
|
T23 |
54691 |
|
T24 |
95 |
| auto[1] |
8006191 |
1 |
|
|
T23 |
44622 |
|
T24 |
51 |
|
T26 |
854 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14776105 |
1 |
|
|
T22 |
42 |
|
T23 |
81200 |
|
T24 |
118 |
| auto[1] |
3271270 |
1 |
|
|
T22 |
8 |
|
T23 |
18113 |
|
T24 |
28 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10049435 |
1 |
|
|
T22 |
30 |
|
T23 |
55896 |
|
T24 |
51 |
| auto[1] |
7997940 |
1 |
|
|
T22 |
20 |
|
T23 |
43417 |
|
T24 |
95 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2357897 |
1 |
|
|
T22 |
12 |
|
T23 |
13072 |
|
T24 |
47 |
| auto[1] |
auto[0] |
auto[1] |
1635273 |
1 |
|
|
T22 |
8 |
|
T23 |
8947 |
|
T24 |
27 |
| auto[1] |
auto[1] |
auto[0] |
2368773 |
1 |
|
|
T23 |
12232 |
|
T24 |
20 |
|
T26 |
219 |
| auto[1] |
auto[1] |
auto[1] |
1635997 |
1 |
|
|
T23 |
9166 |
|
T24 |
1 |
|
T26 |
215 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |