Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10076289 |
1 |
|
|
T22 |
50 |
|
T23 |
56395 |
|
T24 |
76 |
| auto[1] |
7971086 |
1 |
|
|
T23 |
42918 |
|
T24 |
70 |
|
T26 |
929 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14771266 |
1 |
|
|
T22 |
48 |
|
T23 |
80398 |
|
T24 |
124 |
| auto[1] |
3276109 |
1 |
|
|
T22 |
2 |
|
T23 |
18915 |
|
T24 |
22 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10025210 |
1 |
|
|
T22 |
37 |
|
T23 |
52861 |
|
T24 |
109 |
| auto[1] |
8022165 |
1 |
|
|
T22 |
13 |
|
T23 |
46452 |
|
T24 |
37 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2390923 |
1 |
|
|
T22 |
11 |
|
T23 |
14688 |
|
T24 |
11 |
| auto[1] |
auto[0] |
auto[1] |
1648393 |
1 |
|
|
T22 |
2 |
|
T23 |
10201 |
|
T24 |
9 |
| auto[1] |
auto[1] |
auto[0] |
2355133 |
1 |
|
|
T23 |
12849 |
|
T24 |
4 |
|
T26 |
238 |
| auto[1] |
auto[1] |
auto[1] |
1627716 |
1 |
|
|
T23 |
8714 |
|
T24 |
13 |
|
T26 |
266 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |