Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10060461 |
1 |
|
|
T22 |
47 |
|
T23 |
55683 |
|
T24 |
102 |
| auto[1] |
7986914 |
1 |
|
|
T22 |
3 |
|
T23 |
43630 |
|
T24 |
44 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14778172 |
1 |
|
|
T22 |
44 |
|
T23 |
80017 |
|
T24 |
92 |
| auto[1] |
3269203 |
1 |
|
|
T22 |
6 |
|
T23 |
19296 |
|
T24 |
54 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10053299 |
1 |
|
|
T22 |
36 |
|
T23 |
53126 |
|
T24 |
52 |
| auto[1] |
7994076 |
1 |
|
|
T22 |
14 |
|
T23 |
46187 |
|
T24 |
94 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2367326 |
1 |
|
|
T22 |
8 |
|
T23 |
14185 |
|
T24 |
24 |
| auto[1] |
auto[0] |
auto[1] |
1640678 |
1 |
|
|
T22 |
6 |
|
T23 |
10407 |
|
T24 |
34 |
| auto[1] |
auto[1] |
auto[0] |
2357547 |
1 |
|
|
T23 |
12706 |
|
T24 |
16 |
|
T26 |
342 |
| auto[1] |
auto[1] |
auto[1] |
1628525 |
1 |
|
|
T23 |
8889 |
|
T24 |
20 |
|
T26 |
318 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |