Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9989213 |
1 |
|
|
T22 |
30 |
|
T23 |
55435 |
|
T24 |
38 |
| auto[1] |
8058162 |
1 |
|
|
T22 |
20 |
|
T23 |
43878 |
|
T24 |
108 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14768369 |
1 |
|
|
T22 |
45 |
|
T23 |
80227 |
|
T24 |
114 |
| auto[1] |
3279006 |
1 |
|
|
T22 |
5 |
|
T23 |
19086 |
|
T24 |
32 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10032898 |
1 |
|
|
T22 |
30 |
|
T23 |
52869 |
|
T24 |
51 |
| auto[1] |
8014477 |
1 |
|
|
T22 |
20 |
|
T23 |
46444 |
|
T24 |
95 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2356722 |
1 |
|
|
T22 |
3 |
|
T23 |
14329 |
|
T24 |
10 |
| auto[1] |
auto[0] |
auto[1] |
1635237 |
1 |
|
|
T22 |
1 |
|
T23 |
10012 |
|
T24 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2378749 |
1 |
|
|
T22 |
12 |
|
T23 |
13029 |
|
T24 |
53 |
| auto[1] |
auto[1] |
auto[1] |
1643769 |
1 |
|
|
T22 |
4 |
|
T23 |
9074 |
|
T24 |
26 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |