Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10040752 |
1 |
|
|
T22 |
31 |
|
T23 |
55320 |
|
T24 |
62 |
| auto[1] |
8006623 |
1 |
|
|
T22 |
19 |
|
T23 |
43993 |
|
T24 |
84 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17024735 |
1 |
|
|
T22 |
50 |
|
T23 |
93442 |
|
T24 |
142 |
| auto[1] |
1022640 |
1 |
|
|
T23 |
5871 |
|
T24 |
4 |
|
T26 |
192 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10054859 |
1 |
|
|
T22 |
42 |
|
T23 |
56450 |
|
T24 |
91 |
| auto[1] |
7992516 |
1 |
|
|
T22 |
8 |
|
T23 |
42863 |
|
T24 |
55 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3485599 |
1 |
|
|
T22 |
8 |
|
T23 |
19212 |
|
T24 |
20 |
| auto[1] |
auto[0] |
auto[1] |
510746 |
1 |
|
|
T23 |
2993 |
|
T24 |
1 |
|
T26 |
140 |
| auto[1] |
auto[1] |
auto[0] |
3484277 |
1 |
|
|
T23 |
17780 |
|
T24 |
31 |
|
T26 |
222 |
| auto[1] |
auto[1] |
auto[1] |
511894 |
1 |
|
|
T23 |
2878 |
|
T24 |
3 |
|
T26 |
52 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |