Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10085244 |
1 |
|
|
T22 |
50 |
|
T23 |
54385 |
|
T24 |
106 |
| auto[1] |
7962131 |
1 |
|
|
T23 |
44928 |
|
T24 |
40 |
|
T26 |
1203 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14786027 |
1 |
|
|
T22 |
46 |
|
T23 |
80314 |
|
T24 |
134 |
| auto[1] |
3261348 |
1 |
|
|
T22 |
4 |
|
T23 |
18999 |
|
T24 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10070818 |
1 |
|
|
T22 |
31 |
|
T23 |
53991 |
|
T24 |
113 |
| auto[1] |
7976557 |
1 |
|
|
T22 |
19 |
|
T23 |
45322 |
|
T24 |
33 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2371633 |
1 |
|
|
T22 |
15 |
|
T23 |
12777 |
|
T24 |
16 |
| auto[1] |
auto[0] |
auto[1] |
1641221 |
1 |
|
|
T22 |
4 |
|
T23 |
9442 |
|
T24 |
10 |
| auto[1] |
auto[1] |
auto[0] |
2343576 |
1 |
|
|
T23 |
13546 |
|
T24 |
5 |
|
T26 |
194 |
| auto[1] |
auto[1] |
auto[1] |
1620127 |
1 |
|
|
T23 |
9557 |
|
T24 |
2 |
|
T26 |
251 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |