Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10059151 |
1 |
|
|
T22 |
39 |
|
T23 |
54882 |
|
T24 |
73 |
| auto[1] |
7988224 |
1 |
|
|
T22 |
11 |
|
T23 |
44431 |
|
T24 |
73 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14778911 |
1 |
|
|
T22 |
39 |
|
T23 |
81292 |
|
T24 |
103 |
| auto[1] |
3268464 |
1 |
|
|
T22 |
11 |
|
T23 |
18021 |
|
T24 |
43 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10049317 |
1 |
|
|
T22 |
36 |
|
T23 |
55184 |
|
T24 |
50 |
| auto[1] |
7998058 |
1 |
|
|
T22 |
14 |
|
T23 |
44129 |
|
T24 |
96 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2376280 |
1 |
|
|
T22 |
3 |
|
T23 |
12340 |
|
T24 |
23 |
| auto[1] |
auto[0] |
auto[1] |
1642877 |
1 |
|
|
T22 |
11 |
|
T23 |
8603 |
|
T24 |
25 |
| auto[1] |
auto[1] |
auto[0] |
2353314 |
1 |
|
|
T23 |
13768 |
|
T24 |
30 |
|
T26 |
185 |
| auto[1] |
auto[1] |
auto[1] |
1625587 |
1 |
|
|
T23 |
9418 |
|
T24 |
18 |
|
T26 |
143 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |