Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10021495 |
1 |
|
|
T22 |
42 |
|
T23 |
53380 |
|
T24 |
91 |
| auto[1] |
8025880 |
1 |
|
|
T22 |
8 |
|
T23 |
45933 |
|
T24 |
55 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17029872 |
1 |
|
|
T22 |
50 |
|
T23 |
92908 |
|
T24 |
139 |
| auto[1] |
1017503 |
1 |
|
|
T23 |
6405 |
|
T24 |
7 |
|
T26 |
179 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10081655 |
1 |
|
|
T22 |
46 |
|
T23 |
53572 |
|
T24 |
78 |
| auto[1] |
7965720 |
1 |
|
|
T22 |
4 |
|
T23 |
45741 |
|
T24 |
68 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3476570 |
1 |
|
|
T22 |
4 |
|
T23 |
19020 |
|
T24 |
46 |
| auto[1] |
auto[0] |
auto[1] |
509787 |
1 |
|
|
T23 |
3110 |
|
T24 |
6 |
|
T26 |
81 |
| auto[1] |
auto[1] |
auto[0] |
3471647 |
1 |
|
|
T23 |
20316 |
|
T24 |
15 |
|
T26 |
418 |
| auto[1] |
auto[1] |
auto[1] |
507716 |
1 |
|
|
T23 |
3295 |
|
T24 |
1 |
|
T26 |
98 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |