Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10045946 |
1 |
|
|
T22 |
30 |
|
T23 |
52827 |
|
T24 |
88 |
| auto[1] |
8001429 |
1 |
|
|
T22 |
20 |
|
T23 |
46486 |
|
T24 |
58 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17028789 |
1 |
|
|
T22 |
50 |
|
T23 |
93046 |
|
T24 |
144 |
| auto[1] |
1018586 |
1 |
|
|
T23 |
6267 |
|
T24 |
2 |
|
T26 |
184 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10080969 |
1 |
|
|
T22 |
45 |
|
T23 |
54414 |
|
T24 |
99 |
| auto[1] |
7966406 |
1 |
|
|
T22 |
5 |
|
T23 |
44899 |
|
T24 |
47 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3476691 |
1 |
|
|
T22 |
5 |
|
T23 |
18096 |
|
T24 |
28 |
| auto[1] |
auto[0] |
auto[1] |
509803 |
1 |
|
|
T23 |
2885 |
|
T24 |
1 |
|
T26 |
76 |
| auto[1] |
auto[1] |
auto[0] |
3471129 |
1 |
|
|
T23 |
20536 |
|
T24 |
17 |
|
T26 |
430 |
| auto[1] |
auto[1] |
auto[1] |
508783 |
1 |
|
|
T23 |
3382 |
|
T24 |
1 |
|
T26 |
108 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |