Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10069388 |
1 |
|
|
T22 |
27 |
|
T23 |
55610 |
|
T24 |
73 |
| auto[1] |
7977987 |
1 |
|
|
T22 |
23 |
|
T23 |
43703 |
|
T24 |
73 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17023422 |
1 |
|
|
T22 |
50 |
|
T23 |
92917 |
|
T24 |
140 |
| auto[1] |
1023953 |
1 |
|
|
T23 |
6396 |
|
T24 |
6 |
|
T26 |
124 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10043850 |
1 |
|
|
T22 |
49 |
|
T23 |
53272 |
|
T24 |
57 |
| auto[1] |
8003525 |
1 |
|
|
T22 |
1 |
|
T23 |
46041 |
|
T24 |
89 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3519589 |
1 |
|
|
T22 |
1 |
|
T23 |
21019 |
|
T24 |
42 |
| auto[1] |
auto[0] |
auto[1] |
515452 |
1 |
|
|
T23 |
3435 |
|
T24 |
5 |
|
T26 |
59 |
| auto[1] |
auto[1] |
auto[0] |
3459983 |
1 |
|
|
T23 |
18626 |
|
T24 |
41 |
|
T26 |
284 |
| auto[1] |
auto[1] |
auto[1] |
508501 |
1 |
|
|
T23 |
2961 |
|
T24 |
1 |
|
T26 |
65 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |