Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9982551 |
1 |
|
|
T22 |
39 |
|
T23 |
56021 |
|
T24 |
106 |
| auto[1] |
8064824 |
1 |
|
|
T22 |
11 |
|
T23 |
43292 |
|
T24 |
40 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17025213 |
1 |
|
|
T22 |
50 |
|
T23 |
93265 |
|
T24 |
141 |
| auto[1] |
1022162 |
1 |
|
|
T23 |
6048 |
|
T24 |
5 |
|
T26 |
162 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10067176 |
1 |
|
|
T22 |
50 |
|
T23 |
55766 |
|
T24 |
78 |
| auto[1] |
7980199 |
1 |
|
|
T23 |
43547 |
|
T24 |
68 |
|
T26 |
873 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3450335 |
1 |
|
|
T23 |
18910 |
|
T24 |
48 |
|
T26 |
342 |
| auto[1] |
auto[0] |
auto[1] |
506621 |
1 |
|
|
T23 |
3054 |
|
T24 |
3 |
|
T26 |
82 |
| auto[1] |
auto[1] |
auto[0] |
3507702 |
1 |
|
|
T23 |
18589 |
|
T24 |
15 |
|
T26 |
369 |
| auto[1] |
auto[1] |
auto[1] |
515541 |
1 |
|
|
T23 |
2994 |
|
T24 |
2 |
|
T26 |
80 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |