Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10024933 |
1 |
|
|
T22 |
31 |
|
T23 |
53017 |
|
T24 |
73 |
| auto[1] |
8022442 |
1 |
|
|
T22 |
19 |
|
T23 |
46296 |
|
T24 |
73 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17027960 |
1 |
|
|
T22 |
50 |
|
T23 |
93053 |
|
T24 |
141 |
| auto[1] |
1019415 |
1 |
|
|
T23 |
6260 |
|
T24 |
5 |
|
T26 |
200 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10079359 |
1 |
|
|
T22 |
45 |
|
T23 |
53898 |
|
T24 |
61 |
| auto[1] |
7968016 |
1 |
|
|
T22 |
5 |
|
T23 |
45415 |
|
T24 |
85 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3472184 |
1 |
|
|
T22 |
5 |
|
T23 |
18777 |
|
T24 |
51 |
| auto[1] |
auto[0] |
auto[1] |
508370 |
1 |
|
|
T23 |
2839 |
|
T24 |
2 |
|
T26 |
117 |
| auto[1] |
auto[1] |
auto[0] |
3476417 |
1 |
|
|
T23 |
20378 |
|
T24 |
29 |
|
T26 |
321 |
| auto[1] |
auto[1] |
auto[1] |
511045 |
1 |
|
|
T23 |
3421 |
|
T24 |
3 |
|
T26 |
83 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |