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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 947
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T767 /workspace/coverage/cover_reg_top/7.gpio_intr_test.3602694815 Jul 01 04:27:24 PM PDT 24 Jul 01 04:27:36 PM PDT 24 28314967 ps
T768 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.4000154982 Jul 01 04:27:38 PM PDT 24 Jul 01 04:27:49 PM PDT 24 76753105 ps
T769 /workspace/coverage/cover_reg_top/25.gpio_intr_test.392835141 Jul 01 04:27:26 PM PDT 24 Jul 01 04:27:37 PM PDT 24 15921937 ps
T770 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1138079997 Jul 01 04:27:26 PM PDT 24 Jul 01 04:27:38 PM PDT 24 28904027 ps
T771 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2219163427 Jul 01 04:27:23 PM PDT 24 Jul 01 04:27:36 PM PDT 24 25668732 ps
T106 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.900854487 Jul 01 04:27:32 PM PDT 24 Jul 01 04:27:43 PM PDT 24 57938385 ps
T772 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.573982273 Jul 01 04:27:25 PM PDT 24 Jul 01 04:27:36 PM PDT 24 11236787 ps
T773 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3355445909 Jul 01 04:27:32 PM PDT 24 Jul 01 04:27:43 PM PDT 24 13171185 ps
T774 /workspace/coverage/cover_reg_top/41.gpio_intr_test.3912682181 Jul 01 04:27:38 PM PDT 24 Jul 01 04:27:49 PM PDT 24 17373871 ps
T775 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2884246425 Jul 01 04:27:18 PM PDT 24 Jul 01 04:27:31 PM PDT 24 119840543 ps
T776 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2304281385 Jul 01 04:27:53 PM PDT 24 Jul 01 04:28:00 PM PDT 24 35364172 ps
T777 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3882995771 Jul 01 04:27:05 PM PDT 24 Jul 01 04:27:21 PM PDT 24 113814702 ps
T94 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.339467123 Jul 01 04:27:22 PM PDT 24 Jul 01 04:27:35 PM PDT 24 47201612 ps
T113 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.4030238544 Jul 01 04:27:31 PM PDT 24 Jul 01 04:27:42 PM PDT 24 46907123 ps
T107 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2658555778 Jul 01 04:27:27 PM PDT 24 Jul 01 04:27:39 PM PDT 24 59456095 ps
T778 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.779416490 Jul 01 04:27:19 PM PDT 24 Jul 01 04:27:34 PM PDT 24 78141393 ps
T779 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.784162044 Jul 01 04:27:42 PM PDT 24 Jul 01 04:27:52 PM PDT 24 99338791 ps
T780 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.4041204598 Jul 01 04:27:13 PM PDT 24 Jul 01 04:27:29 PM PDT 24 36777590 ps
T781 /workspace/coverage/cover_reg_top/39.gpio_intr_test.2480933221 Jul 01 04:27:28 PM PDT 24 Jul 01 04:27:39 PM PDT 24 133272803 ps
T49 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.40209692 Jul 01 04:27:07 PM PDT 24 Jul 01 04:27:23 PM PDT 24 170796731 ps
T47 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1547512270 Jul 01 04:27:15 PM PDT 24 Jul 01 04:27:30 PM PDT 24 93139996 ps
T45 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.290021507 Jul 01 04:27:34 PM PDT 24 Jul 01 04:27:47 PM PDT 24 301752712 ps
T782 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1145533866 Jul 01 04:27:06 PM PDT 24 Jul 01 04:27:24 PM PDT 24 192942328 ps
T783 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2845551391 Jul 01 04:27:03 PM PDT 24 Jul 01 04:27:18 PM PDT 24 512932927 ps
T108 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3966843129 Jul 01 04:27:27 PM PDT 24 Jul 01 04:27:39 PM PDT 24 82983721 ps
T784 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1953763862 Jul 01 04:27:39 PM PDT 24 Jul 01 04:27:49 PM PDT 24 78593660 ps
T785 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.992731189 Jul 01 04:27:28 PM PDT 24 Jul 01 04:27:39 PM PDT 24 79062650 ps
T786 /workspace/coverage/cover_reg_top/47.gpio_intr_test.3725084919 Jul 01 04:27:32 PM PDT 24 Jul 01 04:27:43 PM PDT 24 14870987 ps
T95 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1359678465 Jul 01 04:27:06 PM PDT 24 Jul 01 04:27:21 PM PDT 24 134678476 ps
T787 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1782816873 Jul 01 04:27:27 PM PDT 24 Jul 01 04:27:40 PM PDT 24 660414341 ps
T788 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1610768503 Jul 01 04:27:37 PM PDT 24 Jul 01 04:27:49 PM PDT 24 54683261 ps
T789 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1721644002 Jul 01 04:27:33 PM PDT 24 Jul 01 04:27:44 PM PDT 24 62514689 ps
T790 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1269315683 Jul 01 04:27:32 PM PDT 24 Jul 01 04:27:43 PM PDT 24 77536782 ps
T791 /workspace/coverage/cover_reg_top/27.gpio_intr_test.742431176 Jul 01 04:27:28 PM PDT 24 Jul 01 04:27:40 PM PDT 24 16655276 ps
T792 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1531245179 Jul 01 04:27:45 PM PDT 24 Jul 01 04:27:55 PM PDT 24 38962519 ps
T793 /workspace/coverage/cover_reg_top/37.gpio_intr_test.1074867729 Jul 01 04:27:33 PM PDT 24 Jul 01 04:27:45 PM PDT 24 45957928 ps
T794 /workspace/coverage/cover_reg_top/9.gpio_intr_test.3297431743 Jul 01 04:27:07 PM PDT 24 Jul 01 04:27:23 PM PDT 24 51736785 ps
T795 /workspace/coverage/cover_reg_top/13.gpio_intr_test.2091424573 Jul 01 04:27:41 PM PDT 24 Jul 01 04:27:51 PM PDT 24 13582932 ps
T796 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1571548831 Jul 01 04:27:17 PM PDT 24 Jul 01 04:27:31 PM PDT 24 13872779 ps
T797 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1457273113 Jul 01 04:27:27 PM PDT 24 Jul 01 04:27:39 PM PDT 24 18749861 ps
T798 /workspace/coverage/cover_reg_top/3.gpio_intr_test.3350326092 Jul 01 04:27:06 PM PDT 24 Jul 01 04:27:21 PM PDT 24 15856698 ps
T799 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.4098564692 Jul 01 04:27:13 PM PDT 24 Jul 01 04:27:28 PM PDT 24 44558310 ps
T800 /workspace/coverage/cover_reg_top/21.gpio_intr_test.527710242 Jul 01 04:27:48 PM PDT 24 Jul 01 04:27:56 PM PDT 24 17824640 ps
T96 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1782021328 Jul 01 04:27:17 PM PDT 24 Jul 01 04:27:31 PM PDT 24 32560642 ps
T801 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.383532302 Jul 01 04:27:27 PM PDT 24 Jul 01 04:27:39 PM PDT 24 51766911 ps
T802 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1234523248 Jul 01 04:27:30 PM PDT 24 Jul 01 04:27:45 PM PDT 24 54648664 ps
T803 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3006102930 Jul 01 04:27:07 PM PDT 24 Jul 01 04:27:22 PM PDT 24 66412223 ps
T804 /workspace/coverage/cover_reg_top/35.gpio_intr_test.3791843200 Jul 01 04:27:34 PM PDT 24 Jul 01 04:27:45 PM PDT 24 43385553 ps
T805 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3144946291 Jul 01 04:27:33 PM PDT 24 Jul 01 04:27:46 PM PDT 24 37933948 ps
T99 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1477375420 Jul 01 04:27:28 PM PDT 24 Jul 01 04:27:40 PM PDT 24 29323265 ps
T806 /workspace/coverage/cover_reg_top/49.gpio_intr_test.2166633334 Jul 01 04:27:29 PM PDT 24 Jul 01 04:27:40 PM PDT 24 14007875 ps
T807 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2700890290 Jul 01 04:27:30 PM PDT 24 Jul 01 04:27:44 PM PDT 24 195009525 ps
T808 /workspace/coverage/cover_reg_top/34.gpio_intr_test.984796892 Jul 01 04:27:33 PM PDT 24 Jul 01 04:27:44 PM PDT 24 48948443 ps
T809 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.253271729 Jul 01 04:27:05 PM PDT 24 Jul 01 04:27:20 PM PDT 24 114615056 ps
T810 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3077603888 Jul 01 04:27:27 PM PDT 24 Jul 01 04:27:41 PM PDT 24 53765265 ps
T811 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2956809678 Jul 01 04:27:04 PM PDT 24 Jul 01 04:27:18 PM PDT 24 51284804 ps
T812 /workspace/coverage/cover_reg_top/8.gpio_intr_test.2022930057 Jul 01 04:27:06 PM PDT 24 Jul 01 04:27:20 PM PDT 24 33366223 ps
T813 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.453547133 Jul 01 04:27:28 PM PDT 24 Jul 01 04:27:40 PM PDT 24 25400559 ps
T814 /workspace/coverage/cover_reg_top/6.gpio_intr_test.365467452 Jul 01 04:27:40 PM PDT 24 Jul 01 04:27:50 PM PDT 24 28508592 ps
T815 /workspace/coverage/cover_reg_top/42.gpio_intr_test.3209333982 Jul 01 04:27:45 PM PDT 24 Jul 01 04:27:54 PM PDT 24 14054892 ps
T816 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1961277526 Jul 01 04:27:30 PM PDT 24 Jul 01 04:27:41 PM PDT 24 80030650 ps
T817 /workspace/coverage/cover_reg_top/15.gpio_intr_test.939930489 Jul 01 04:27:28 PM PDT 24 Jul 01 04:27:40 PM PDT 24 15332894 ps
T818 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3064377688 Jul 01 04:27:23 PM PDT 24 Jul 01 04:27:36 PM PDT 24 55127051 ps
T819 /workspace/coverage/cover_reg_top/45.gpio_intr_test.372908532 Jul 01 04:27:38 PM PDT 24 Jul 01 04:27:49 PM PDT 24 36339806 ps
T820 /workspace/coverage/cover_reg_top/38.gpio_intr_test.1589332313 Jul 01 04:27:29 PM PDT 24 Jul 01 04:27:40 PM PDT 24 32823434 ps
T821 /workspace/coverage/cover_reg_top/44.gpio_intr_test.164475855 Jul 01 04:27:48 PM PDT 24 Jul 01 04:27:56 PM PDT 24 15483276 ps
T822 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1785678778 Jul 01 04:27:05 PM PDT 24 Jul 01 04:27:20 PM PDT 24 38796618 ps
T823 /workspace/coverage/cover_reg_top/24.gpio_intr_test.659449110 Jul 01 04:27:51 PM PDT 24 Jul 01 04:27:58 PM PDT 24 28737005 ps
T824 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3899959944 Jul 01 04:27:05 PM PDT 24 Jul 01 04:27:20 PM PDT 24 38134223 ps
T48 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.4246140884 Jul 01 04:27:22 PM PDT 24 Jul 01 04:27:35 PM PDT 24 76914567 ps
T825 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.48364460 Jul 01 04:27:31 PM PDT 24 Jul 01 04:27:43 PM PDT 24 103065794 ps
T826 /workspace/coverage/cover_reg_top/22.gpio_intr_test.2836519171 Jul 01 04:27:42 PM PDT 24 Jul 01 04:27:53 PM PDT 24 16884702 ps
T827 /workspace/coverage/cover_reg_top/32.gpio_intr_test.4196792431 Jul 01 04:27:35 PM PDT 24 Jul 01 04:27:46 PM PDT 24 15581550 ps
T46 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1210262811 Jul 01 04:27:04 PM PDT 24 Jul 01 04:27:28 PM PDT 24 776294039 ps
T828 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1255603887 Jul 01 04:27:08 PM PDT 24 Jul 01 04:27:24 PM PDT 24 428017968 ps
T97 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3784414953 Jul 01 04:27:11 PM PDT 24 Jul 01 04:27:30 PM PDT 24 44968098 ps
T829 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3135356813 Jul 01 04:27:19 PM PDT 24 Jul 01 04:27:33 PM PDT 24 24819461 ps
T830 /workspace/coverage/cover_reg_top/19.gpio_intr_test.4157447280 Jul 01 04:27:39 PM PDT 24 Jul 01 04:27:50 PM PDT 24 48393916 ps
T831 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.575756801 Jul 01 04:27:27 PM PDT 24 Jul 01 04:27:38 PM PDT 24 153123844 ps
T832 /workspace/coverage/cover_reg_top/30.gpio_intr_test.143071468 Jul 01 04:27:53 PM PDT 24 Jul 01 04:28:00 PM PDT 24 44819540 ps
T833 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2373443189 Jul 01 04:27:31 PM PDT 24 Jul 01 04:27:42 PM PDT 24 81422859 ps
T834 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1584603220 Jul 01 04:27:18 PM PDT 24 Jul 01 04:27:31 PM PDT 24 67004294 ps
T835 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3929799115 Jul 01 04:27:23 PM PDT 24 Jul 01 04:27:36 PM PDT 24 26846700 ps
T100 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.4218288942 Jul 01 04:27:06 PM PDT 24 Jul 01 04:27:22 PM PDT 24 36691480 ps
T836 /workspace/coverage/cover_reg_top/26.gpio_intr_test.2979756160 Jul 01 04:27:38 PM PDT 24 Jul 01 04:27:49 PM PDT 24 13703598 ps
T837 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.156514561 Jul 01 04:27:27 PM PDT 24 Jul 01 04:27:38 PM PDT 24 42673163 ps
T838 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.624564115 Jul 01 04:27:06 PM PDT 24 Jul 01 04:27:27 PM PDT 24 11098736 ps
T839 /workspace/coverage/cover_reg_top/14.gpio_intr_test.3323931410 Jul 01 04:27:32 PM PDT 24 Jul 01 04:27:43 PM PDT 24 14724235 ps
T840 /workspace/coverage/cover_reg_top/16.gpio_intr_test.434595602 Jul 01 04:27:30 PM PDT 24 Jul 01 04:27:42 PM PDT 24 12170165 ps
T841 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2571616393 Jul 01 04:27:25 PM PDT 24 Jul 01 04:27:37 PM PDT 24 49645870 ps
T842 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2647359382 Jul 01 04:27:45 PM PDT 24 Jul 01 04:27:54 PM PDT 24 138871519 ps
T843 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1858859700 Jul 01 04:27:02 PM PDT 24 Jul 01 04:27:17 PM PDT 24 344244779 ps
T844 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1456573640 Jul 01 04:27:13 PM PDT 24 Jul 01 04:27:29 PM PDT 24 217127065 ps
T50 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1158933613 Jul 01 04:27:36 PM PDT 24 Jul 01 04:27:48 PM PDT 24 131176578 ps
T845 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3775890793 Jul 01 04:27:18 PM PDT 24 Jul 01 04:27:33 PM PDT 24 62067569 ps
T846 /workspace/coverage/cover_reg_top/20.gpio_intr_test.2520050243 Jul 01 04:27:14 PM PDT 24 Jul 01 04:27:29 PM PDT 24 27387395 ps
T847 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.555490005 Jul 01 04:27:41 PM PDT 24 Jul 01 04:27:53 PM PDT 24 286486566 ps
T848 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3782312842 Jul 01 04:25:21 PM PDT 24 Jul 01 04:25:33 PM PDT 24 37275693 ps
T849 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1970921791 Jul 01 04:25:42 PM PDT 24 Jul 01 04:25:53 PM PDT 24 238443378 ps
T850 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2498321303 Jul 01 04:25:27 PM PDT 24 Jul 01 04:25:41 PM PDT 24 107156179 ps
T851 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.386604373 Jul 01 04:25:23 PM PDT 24 Jul 01 04:25:35 PM PDT 24 143803952 ps
T852 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4114320665 Jul 01 04:25:39 PM PDT 24 Jul 01 04:25:50 PM PDT 24 155951658 ps
T853 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2876508019 Jul 01 04:25:45 PM PDT 24 Jul 01 04:25:56 PM PDT 24 50014469 ps
T854 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.535071380 Jul 01 04:25:52 PM PDT 24 Jul 01 04:26:04 PM PDT 24 75260734 ps
T855 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2394541449 Jul 01 04:25:32 PM PDT 24 Jul 01 04:25:44 PM PDT 24 124572195 ps
T856 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.4253472021 Jul 01 04:25:19 PM PDT 24 Jul 01 04:25:30 PM PDT 24 95866688 ps
T857 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3189369478 Jul 01 04:25:36 PM PDT 24 Jul 01 04:25:47 PM PDT 24 99164937 ps
T858 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3625543681 Jul 01 04:25:46 PM PDT 24 Jul 01 04:25:58 PM PDT 24 67990656 ps
T859 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2952714018 Jul 01 04:25:52 PM PDT 24 Jul 01 04:26:04 PM PDT 24 68425576 ps
T860 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.4288770761 Jul 01 04:25:31 PM PDT 24 Jul 01 04:25:43 PM PDT 24 28181787 ps
T861 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.814560596 Jul 01 04:25:18 PM PDT 24 Jul 01 04:25:28 PM PDT 24 155054375 ps
T862 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2675621538 Jul 01 04:25:23 PM PDT 24 Jul 01 04:25:36 PM PDT 24 85561322 ps
T863 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.336592240 Jul 01 04:25:37 PM PDT 24 Jul 01 04:25:48 PM PDT 24 82266227 ps
T864 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2978259368 Jul 01 04:25:25 PM PDT 24 Jul 01 04:25:39 PM PDT 24 363723437 ps
T865 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.747513370 Jul 01 04:25:44 PM PDT 24 Jul 01 04:25:55 PM PDT 24 270284501 ps
T866 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1260657353 Jul 01 04:25:22 PM PDT 24 Jul 01 04:25:34 PM PDT 24 47794613 ps
T867 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2217933549 Jul 01 04:25:19 PM PDT 24 Jul 01 04:25:30 PM PDT 24 66500399 ps
T868 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2730725519 Jul 01 04:25:23 PM PDT 24 Jul 01 04:25:37 PM PDT 24 263678587 ps
T869 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2220252600 Jul 01 04:25:33 PM PDT 24 Jul 01 04:25:45 PM PDT 24 141502298 ps
T870 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.496517824 Jul 01 04:25:22 PM PDT 24 Jul 01 04:25:35 PM PDT 24 103566262 ps
T871 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3861014986 Jul 01 04:25:22 PM PDT 24 Jul 01 04:25:34 PM PDT 24 52191616 ps
T872 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.969473755 Jul 01 04:25:18 PM PDT 24 Jul 01 04:25:28 PM PDT 24 686245228 ps
T873 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3850039996 Jul 01 04:25:36 PM PDT 24 Jul 01 04:25:47 PM PDT 24 68321735 ps
T874 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4040450468 Jul 01 04:25:22 PM PDT 24 Jul 01 04:25:34 PM PDT 24 265906650 ps
T875 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.327887845 Jul 01 04:25:24 PM PDT 24 Jul 01 04:25:37 PM PDT 24 311815653 ps
T876 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.309678984 Jul 01 04:25:31 PM PDT 24 Jul 01 04:25:43 PM PDT 24 167895336 ps
T877 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1963152226 Jul 01 04:25:41 PM PDT 24 Jul 01 04:25:52 PM PDT 24 72552800 ps
T878 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1118888453 Jul 01 04:25:45 PM PDT 24 Jul 01 04:25:57 PM PDT 24 325176422 ps
T879 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2675016689 Jul 01 04:25:35 PM PDT 24 Jul 01 04:25:47 PM PDT 24 434031247 ps
T880 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1096027878 Jul 01 04:25:19 PM PDT 24 Jul 01 04:25:30 PM PDT 24 241846834 ps
T881 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.677036851 Jul 01 04:25:23 PM PDT 24 Jul 01 04:25:35 PM PDT 24 416939593 ps
T882 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1258698708 Jul 01 04:25:36 PM PDT 24 Jul 01 04:25:47 PM PDT 24 33713173 ps
T883 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3049831483 Jul 01 04:25:24 PM PDT 24 Jul 01 04:25:36 PM PDT 24 64544321 ps
T884 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3465550851 Jul 01 04:25:28 PM PDT 24 Jul 01 04:25:41 PM PDT 24 212644974 ps
T885 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2705113792 Jul 01 04:25:46 PM PDT 24 Jul 01 04:25:58 PM PDT 24 213638579 ps
T886 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.4148092978 Jul 01 04:25:33 PM PDT 24 Jul 01 04:25:45 PM PDT 24 138235104 ps
T887 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.4185335154 Jul 01 04:25:32 PM PDT 24 Jul 01 04:25:44 PM PDT 24 104829018 ps
T888 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1265585165 Jul 01 04:25:35 PM PDT 24 Jul 01 04:25:47 PM PDT 24 39920715 ps
T889 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2705712816 Jul 01 04:25:29 PM PDT 24 Jul 01 04:25:42 PM PDT 24 51560378 ps
T890 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2481785437 Jul 01 04:25:17 PM PDT 24 Jul 01 04:25:27 PM PDT 24 131569792 ps
T891 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.141887838 Jul 01 04:25:27 PM PDT 24 Jul 01 04:25:41 PM PDT 24 150265838 ps
T892 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.893097158 Jul 01 04:25:36 PM PDT 24 Jul 01 04:25:47 PM PDT 24 36618803 ps
T893 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2254674910 Jul 01 04:25:47 PM PDT 24 Jul 01 04:25:59 PM PDT 24 180479361 ps
T894 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3790429812 Jul 01 04:25:30 PM PDT 24 Jul 01 04:25:42 PM PDT 24 273278834 ps
T895 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.752530693 Jul 01 04:25:27 PM PDT 24 Jul 01 04:25:41 PM PDT 24 182685927 ps
T896 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2186638226 Jul 01 04:25:19 PM PDT 24 Jul 01 04:25:30 PM PDT 24 150810342 ps
T897 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2370880247 Jul 01 04:25:33 PM PDT 24 Jul 01 04:25:45 PM PDT 24 182410182 ps
T898 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3578456945 Jul 01 04:25:31 PM PDT 24 Jul 01 04:25:43 PM PDT 24 196976281 ps
T899 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2988073268 Jul 01 04:25:18 PM PDT 24 Jul 01 04:25:29 PM PDT 24 265175614 ps
T900 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1953504494 Jul 01 04:25:32 PM PDT 24 Jul 01 04:25:44 PM PDT 24 70875652 ps
T901 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.229543764 Jul 01 04:25:16 PM PDT 24 Jul 01 04:25:25 PM PDT 24 217054946 ps
T902 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1256323922 Jul 01 04:25:22 PM PDT 24 Jul 01 04:25:34 PM PDT 24 230387101 ps
T903 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1975383365 Jul 01 04:25:26 PM PDT 24 Jul 01 04:25:40 PM PDT 24 111284765 ps
T904 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1218441100 Jul 01 04:25:17 PM PDT 24 Jul 01 04:25:27 PM PDT 24 202711197 ps
T905 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4065441642 Jul 01 04:25:38 PM PDT 24 Jul 01 04:25:49 PM PDT 24 73025005 ps
T906 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3017432253 Jul 01 04:25:29 PM PDT 24 Jul 01 04:25:42 PM PDT 24 49869738 ps
T907 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.461668107 Jul 01 04:25:42 PM PDT 24 Jul 01 04:25:53 PM PDT 24 302715806 ps
T908 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.113834351 Jul 01 04:25:27 PM PDT 24 Jul 01 04:25:40 PM PDT 24 68351503 ps
T909 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.404716605 Jul 01 04:25:24 PM PDT 24 Jul 01 04:25:38 PM PDT 24 295184259 ps
T910 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.4119098187 Jul 01 04:25:45 PM PDT 24 Jul 01 04:25:57 PM PDT 24 143472111 ps
T911 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1747283529 Jul 01 04:25:36 PM PDT 24 Jul 01 04:25:47 PM PDT 24 35795719 ps
T912 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.451767169 Jul 01 04:25:20 PM PDT 24 Jul 01 04:25:32 PM PDT 24 52291957 ps
T913 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.719315263 Jul 01 04:25:33 PM PDT 24 Jul 01 04:25:45 PM PDT 24 369260035 ps
T914 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1864198480 Jul 01 04:25:30 PM PDT 24 Jul 01 04:25:42 PM PDT 24 209171276 ps
T915 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3631255179 Jul 01 04:25:26 PM PDT 24 Jul 01 04:25:39 PM PDT 24 46688746 ps
T916 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2119518567 Jul 01 04:25:31 PM PDT 24 Jul 01 04:25:43 PM PDT 24 148595722 ps
T917 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.945662628 Jul 01 04:25:24 PM PDT 24 Jul 01 04:25:37 PM PDT 24 36845682 ps
T918 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3327748087 Jul 01 04:25:17 PM PDT 24 Jul 01 04:25:27 PM PDT 24 137268899 ps
T919 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3365335808 Jul 01 04:25:46 PM PDT 24 Jul 01 04:25:58 PM PDT 24 39836027 ps
T920 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2235213760 Jul 01 04:25:24 PM PDT 24 Jul 01 04:25:38 PM PDT 24 103845614 ps
T921 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1609732929 Jul 01 04:25:18 PM PDT 24 Jul 01 04:25:30 PM PDT 24 362933869 ps
T922 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.828316373 Jul 01 04:25:24 PM PDT 24 Jul 01 04:25:38 PM PDT 24 79352214 ps
T923 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3324203928 Jul 01 04:25:36 PM PDT 24 Jul 01 04:25:48 PM PDT 24 84997799 ps
T924 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2459005164 Jul 01 04:25:25 PM PDT 24 Jul 01 04:25:39 PM PDT 24 75348583 ps
T925 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.423835551 Jul 01 04:25:51 PM PDT 24 Jul 01 04:26:03 PM PDT 24 42545296 ps
T926 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2900036649 Jul 01 04:25:47 PM PDT 24 Jul 01 04:25:59 PM PDT 24 54929793 ps
T927 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.4105095968 Jul 01 04:25:28 PM PDT 24 Jul 01 04:25:41 PM PDT 24 445307299 ps
T928 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.620841529 Jul 01 04:25:24 PM PDT 24 Jul 01 04:25:38 PM PDT 24 90725834 ps
T929 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3215743037 Jul 01 04:25:36 PM PDT 24 Jul 01 04:25:47 PM PDT 24 59875644 ps
T930 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1181057447 Jul 01 04:25:23 PM PDT 24 Jul 01 04:25:37 PM PDT 24 994530775 ps
T931 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2094417027 Jul 01 04:25:37 PM PDT 24 Jul 01 04:25:48 PM PDT 24 74220188 ps
T932 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.374048939 Jul 01 04:25:27 PM PDT 24 Jul 01 04:25:41 PM PDT 24 51161342 ps
T933 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3358835062 Jul 01 04:25:39 PM PDT 24 Jul 01 04:25:50 PM PDT 24 143224868 ps
T934 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.191372313 Jul 01 04:25:28 PM PDT 24 Jul 01 04:25:42 PM PDT 24 78398101 ps
T935 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3981412939 Jul 01 04:25:32 PM PDT 24 Jul 01 04:25:44 PM PDT 24 399332075 ps
T936 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2509384932 Jul 01 04:25:41 PM PDT 24 Jul 01 04:25:52 PM PDT 24 187941880 ps
T937 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4082069719 Jul 01 04:25:18 PM PDT 24 Jul 01 04:25:28 PM PDT 24 70663935 ps
T938 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.59131372 Jul 01 04:25:19 PM PDT 24 Jul 01 04:25:30 PM PDT 24 35475788 ps
T939 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1702396333 Jul 01 04:25:38 PM PDT 24 Jul 01 04:25:49 PM PDT 24 79910201 ps
T940 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2623068745 Jul 01 04:25:25 PM PDT 24 Jul 01 04:25:38 PM PDT 24 182246254 ps
T941 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3747939443 Jul 01 04:25:21 PM PDT 24 Jul 01 04:25:33 PM PDT 24 237046876 ps
T942 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2697207659 Jul 01 04:25:19 PM PDT 24 Jul 01 04:25:30 PM PDT 24 130173232 ps
T943 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.594372728 Jul 01 04:25:18 PM PDT 24 Jul 01 04:25:28 PM PDT 24 53112481 ps
T944 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.95122119 Jul 01 04:25:21 PM PDT 24 Jul 01 04:25:32 PM PDT 24 83443879 ps
T945 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3237777604 Jul 01 04:25:20 PM PDT 24 Jul 01 04:25:32 PM PDT 24 69516516 ps
T946 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4191937560 Jul 01 04:25:20 PM PDT 24 Jul 01 04:25:31 PM PDT 24 50293750 ps
T947 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3264461785 Jul 01 04:25:19 PM PDT 24 Jul 01 04:25:30 PM PDT 24 208744550 ps

Test location /workspace/coverage/default/45.gpio_full_random.3393654499
Short name T31
Test name
Test status
Simulation time 91402834 ps
CPU time 1.15 seconds
Started Jul 01 04:50:06 PM PDT 24
Finished Jul 01 04:50:11 PM PDT 24
Peak memory 198408 kb
Host smart-d3cd7bef-af11-4b1c-b903-07c2f9fff79b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393654499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3393654499
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3975726833
Short name T25
Test name
Test status
Simulation time 443533187 ps
CPU time 3.43 seconds
Started Jul 01 04:49:07 PM PDT 24
Finished Jul 01 04:49:16 PM PDT 24
Peak memory 198652 kb
Host smart-b58df94f-988b-4c65-b22e-b6d4615949e8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975726833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3975726833
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.3233566981
Short name T34
Test name
Test status
Simulation time 1445115316460 ps
CPU time 2505.82 seconds
Started Jul 01 04:48:23 PM PDT 24
Finished Jul 01 05:30:11 PM PDT 24
Peak memory 207104 kb
Host smart-4a7ade6d-ca7f-4e04-8c23-e742be8d4038
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3233566981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.3233566981
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.2743727755
Short name T1
Test name
Test status
Simulation time 1561105516 ps
CPU time 4.76 seconds
Started Jul 01 04:49:45 PM PDT 24
Finished Jul 01 04:49:53 PM PDT 24
Peak memory 198604 kb
Host smart-ecf5b156-3334-4afb-9c3a-53af1fbf4243
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743727755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.2743727755
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.1215080235
Short name T40
Test name
Test status
Simulation time 279036788 ps
CPU time 0.91 seconds
Started Jul 01 04:48:19 PM PDT 24
Finished Jul 01 04:48:21 PM PDT 24
Peak memory 215092 kb
Host smart-0ee0396d-341f-4c12-a293-b3ab6f2dc23d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215080235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.1215080235
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.687997685
Short name T85
Test name
Test status
Simulation time 57936017 ps
CPU time 0.61 seconds
Started Jul 01 04:27:42 PM PDT 24
Finished Jul 01 04:27:53 PM PDT 24
Peak memory 195628 kb
Host smart-4dadd88d-05de-4c5f-b8f2-118b33e2917c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687997685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio
_csr_rw.687997685
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.303229701
Short name T44
Test name
Test status
Simulation time 785412915 ps
CPU time 1.41 seconds
Started Jul 01 04:27:31 PM PDT 24
Finished Jul 01 04:27:43 PM PDT 24
Peak memory 198584 kb
Host smart-42725617-c4ea-4a69-83eb-7c188d032e25
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303229701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.gpio_tl_intg_err.303229701
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/10.gpio_alert_test.3952592496
Short name T43
Test name
Test status
Simulation time 25376827 ps
CPU time 0.64 seconds
Started Jul 01 04:48:43 PM PDT 24
Finished Jul 01 04:48:47 PM PDT 24
Peak memory 194836 kb
Host smart-ba5dada0-5953-4bf8-b05a-1bc8edbffdb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952592496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.3952592496
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2658555778
Short name T107
Test name
Test status
Simulation time 59456095 ps
CPU time 0.82 seconds
Started Jul 01 04:27:27 PM PDT 24
Finished Jul 01 04:27:39 PM PDT 24
Peak memory 196580 kb
Host smart-45ecbcc3-4d19-49f1-b8b7-3749efc2150d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658555778 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.2658555778
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.4246140884
Short name T48
Test name
Test status
Simulation time 76914567 ps
CPU time 0.87 seconds
Started Jul 01 04:27:22 PM PDT 24
Finished Jul 01 04:27:35 PM PDT 24
Peak memory 197716 kb
Host smart-c3c5b3c8-5fd1-42e5-b70b-0657db58bbd2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246140884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.4246140884
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/10.gpio_full_random.1114914102
Short name T22
Test name
Test status
Simulation time 681844298 ps
CPU time 0.74 seconds
Started Jul 01 04:48:44 PM PDT 24
Finished Jul 01 04:48:49 PM PDT 24
Peak memory 197072 kb
Host smart-b8f32541-3a2d-4dba-821c-2d34d0a742fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114914102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1114914102
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.4142114730
Short name T37
Test name
Test status
Simulation time 84941469 ps
CPU time 0.88 seconds
Started Jul 01 04:27:22 PM PDT 24
Finished Jul 01 04:27:34 PM PDT 24
Peak memory 197784 kb
Host smart-7627293d-5dea-474d-b123-9297617ddac4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142114730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.4142114730
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1210262811
Short name T46
Test name
Test status
Simulation time 776294039 ps
CPU time 1.22 seconds
Started Jul 01 04:27:04 PM PDT 24
Finished Jul 01 04:27:28 PM PDT 24
Peak memory 198564 kb
Host smart-2de55f0c-e856-4fa4-91e6-65b5577afbd2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210262811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1210262811
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.370827653
Short name T110
Test name
Test status
Simulation time 95270497 ps
CPU time 0.7 seconds
Started Jul 01 04:27:06 PM PDT 24
Finished Jul 01 04:27:22 PM PDT 24
Peak memory 195656 kb
Host smart-37ab7267-4143-4a29-9a4e-20ee0d2c960e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370827653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.gpio_csr_aliasing.370827653
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2845551391
Short name T783
Test name
Test status
Simulation time 512932927 ps
CPU time 2.43 seconds
Started Jul 01 04:27:03 PM PDT 24
Finished Jul 01 04:27:18 PM PDT 24
Peak memory 198492 kb
Host smart-143b06a8-46cd-403f-aef6-9dc686833048
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845551391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2845551391
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3355445909
Short name T773
Test name
Test status
Simulation time 13171185 ps
CPU time 0.62 seconds
Started Jul 01 04:27:32 PM PDT 24
Finished Jul 01 04:27:43 PM PDT 24
Peak memory 195116 kb
Host smart-d51f8ce7-624a-43a9-9630-ef056a243e96
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355445909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.3355445909
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1788988300
Short name T736
Test name
Test status
Simulation time 132184906 ps
CPU time 1 seconds
Started Jul 01 04:27:30 PM PDT 24
Finished Jul 01 04:27:41 PM PDT 24
Peak memory 198428 kb
Host smart-882f6aed-09c7-48e3-b312-d65422acdfcb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788988300 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1788988300
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1571548831
Short name T796
Test name
Test status
Simulation time 13872779 ps
CPU time 0.57 seconds
Started Jul 01 04:27:17 PM PDT 24
Finished Jul 01 04:27:31 PM PDT 24
Peak memory 195188 kb
Host smart-6f50c8ea-5829-4fb5-91da-38fa5f10d573
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571548831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.1571548831
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3098838114
Short name T731
Test name
Test status
Simulation time 52312445 ps
CPU time 0.59 seconds
Started Jul 01 04:27:07 PM PDT 24
Finished Jul 01 04:27:23 PM PDT 24
Peak memory 194956 kb
Host smart-825af0c9-03ad-4f25-a162-16951eacfa01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098838114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3098838114
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.453547133
Short name T813
Test name
Test status
Simulation time 25400559 ps
CPU time 0.75 seconds
Started Jul 01 04:27:28 PM PDT 24
Finished Jul 01 04:27:40 PM PDT 24
Peak memory 195800 kb
Host smart-1f4322e8-ec4c-4897-a878-c6887fc6dbb2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453547133 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.gpio_same_csr_outstanding.453547133
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2262191920
Short name T726
Test name
Test status
Simulation time 388619064 ps
CPU time 2.04 seconds
Started Jul 01 04:27:08 PM PDT 24
Finished Jul 01 04:27:25 PM PDT 24
Peak memory 198756 kb
Host smart-a2486c10-1120-4fbc-bf60-4cd98b171185
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262191920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2262191920
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.4218288942
Short name T100
Test name
Test status
Simulation time 36691480 ps
CPU time 0.83 seconds
Started Jul 01 04:27:06 PM PDT 24
Finished Jul 01 04:27:22 PM PDT 24
Peak memory 196740 kb
Host smart-974602cd-ecfc-4d93-80c8-83171dfba811
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218288942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.4218288942
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1359678465
Short name T95
Test name
Test status
Simulation time 134678476 ps
CPU time 1.56 seconds
Started Jul 01 04:27:06 PM PDT 24
Finished Jul 01 04:27:21 PM PDT 24
Peak memory 197248 kb
Host smart-8230b5e7-7993-49dc-b4b0-3c91451035c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359678465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.1359678465
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1477375420
Short name T99
Test name
Test status
Simulation time 29323265 ps
CPU time 0.61 seconds
Started Jul 01 04:27:28 PM PDT 24
Finished Jul 01 04:27:40 PM PDT 24
Peak memory 195116 kb
Host smart-a6088e7b-9ec9-4d0e-9c3a-1df95f840c72
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477375420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.1477375420
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3300302473
Short name T758
Test name
Test status
Simulation time 45208180 ps
CPU time 0.77 seconds
Started Jul 01 04:27:27 PM PDT 24
Finished Jul 01 04:27:38 PM PDT 24
Peak memory 198516 kb
Host smart-844116bc-f34f-4bc6-810d-a3fa24533b0c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300302473 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3300302473
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.4063351022
Short name T753
Test name
Test status
Simulation time 43785507 ps
CPU time 0.65 seconds
Started Jul 01 04:27:08 PM PDT 24
Finished Jul 01 04:27:23 PM PDT 24
Peak memory 195428 kb
Host smart-39eff530-7673-4e6a-b060-f765b04a6201
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063351022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.4063351022
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.34312205
Short name T751
Test name
Test status
Simulation time 57194293 ps
CPU time 0.63 seconds
Started Jul 01 04:27:29 PM PDT 24
Finished Jul 01 04:27:40 PM PDT 24
Peak memory 195180 kb
Host smart-53e1bd78-2d95-435e-a704-94eca2ec1b71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34312205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.34312205
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1782816873
Short name T787
Test name
Test status
Simulation time 660414341 ps
CPU time 2.18 seconds
Started Jul 01 04:27:27 PM PDT 24
Finished Jul 01 04:27:40 PM PDT 24
Peak memory 198592 kb
Host smart-bd0e126d-5f54-40e5-959c-13324a231994
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782816873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1782816873
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3882995771
Short name T777
Test name
Test status
Simulation time 113814702 ps
CPU time 1.13 seconds
Started Jul 01 04:27:05 PM PDT 24
Finished Jul 01 04:27:21 PM PDT 24
Peak memory 198556 kb
Host smart-d7f2d8f6-8d35-4ad6-a8d3-e3f014331ab1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882995771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3882995771
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.784162044
Short name T779
Test name
Test status
Simulation time 99338791 ps
CPU time 0.86 seconds
Started Jul 01 04:27:42 PM PDT 24
Finished Jul 01 04:27:52 PM PDT 24
Peak memory 193464 kb
Host smart-d9143ac7-f505-4838-a487-1242be8e7ecc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784162044 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.784162044
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1610768503
Short name T788
Test name
Test status
Simulation time 54683261 ps
CPU time 0.64 seconds
Started Jul 01 04:27:37 PM PDT 24
Finished Jul 01 04:27:49 PM PDT 24
Peak memory 196116 kb
Host smart-999e876b-536b-4fb8-8d55-d7895c075eef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610768503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.1610768503
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.991926627
Short name T755
Test name
Test status
Simulation time 30117587 ps
CPU time 0.61 seconds
Started Jul 01 04:27:24 PM PDT 24
Finished Jul 01 04:27:36 PM PDT 24
Peak memory 194564 kb
Host smart-6cd80a15-9d85-4cde-8a42-a7d7b6db68aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991926627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.991926627
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.253271729
Short name T809
Test name
Test status
Simulation time 114615056 ps
CPU time 0.83 seconds
Started Jul 01 04:27:05 PM PDT 24
Finished Jul 01 04:27:20 PM PDT 24
Peak memory 197488 kb
Host smart-73d67025-5a6d-4931-8c5f-9660f6bcf4f3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253271729 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 10.gpio_same_csr_outstanding.253271729
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3077603888
Short name T810
Test name
Test status
Simulation time 53765265 ps
CPU time 2.9 seconds
Started Jul 01 04:27:27 PM PDT 24
Finished Jul 01 04:27:41 PM PDT 24
Peak memory 198752 kb
Host smart-aea27f7b-0fc9-4917-b0b2-6da63ed84a68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077603888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3077603888
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2571616393
Short name T841
Test name
Test status
Simulation time 49645870 ps
CPU time 0.85 seconds
Started Jul 01 04:27:25 PM PDT 24
Finished Jul 01 04:27:37 PM PDT 24
Peak memory 198360 kb
Host smart-4952b98c-7917-4450-8036-a609645f08a4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571616393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.2571616393
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3530994838
Short name T732
Test name
Test status
Simulation time 60490201 ps
CPU time 0.69 seconds
Started Jul 01 04:27:37 PM PDT 24
Finished Jul 01 04:27:48 PM PDT 24
Peak memory 198388 kb
Host smart-8e03a506-6b4a-4a6d-ba10-b8292fb138bf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530994838 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.3530994838
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.575756801
Short name T831
Test name
Test status
Simulation time 153123844 ps
CPU time 0.56 seconds
Started Jul 01 04:27:27 PM PDT 24
Finished Jul 01 04:27:38 PM PDT 24
Peak memory 193880 kb
Host smart-edeaaef6-0ec6-4d12-bcd9-a218da128e8d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575756801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.575756801
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1159481502
Short name T738
Test name
Test status
Simulation time 17388321 ps
CPU time 0.6 seconds
Started Jul 01 04:27:22 PM PDT 24
Finished Jul 01 04:27:35 PM PDT 24
Peak memory 194340 kb
Host smart-89c756a5-c038-4751-97e9-def75b478113
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159481502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1159481502
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1953763862
Short name T784
Test name
Test status
Simulation time 78593660 ps
CPU time 0.62 seconds
Started Jul 01 04:27:39 PM PDT 24
Finished Jul 01 04:27:49 PM PDT 24
Peak memory 196148 kb
Host smart-8ae2ed93-0996-4495-943c-37b993e6bb27
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953763862 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1953763862
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.4041204598
Short name T780
Test name
Test status
Simulation time 36777590 ps
CPU time 1.41 seconds
Started Jul 01 04:27:13 PM PDT 24
Finished Jul 01 04:27:29 PM PDT 24
Peak memory 198812 kb
Host smart-3df3e902-41cf-4391-b096-5b33f8481d3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041204598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.4041204598
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1255603887
Short name T828
Test name
Test status
Simulation time 428017968 ps
CPU time 1.42 seconds
Started Jul 01 04:27:08 PM PDT 24
Finished Jul 01 04:27:24 PM PDT 24
Peak memory 198820 kb
Host smart-2124eed0-4294-4ab5-9283-abd62bb73693
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255603887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.1255603887
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.48364460
Short name T825
Test name
Test status
Simulation time 103065794 ps
CPU time 1.76 seconds
Started Jul 01 04:27:31 PM PDT 24
Finished Jul 01 04:27:43 PM PDT 24
Peak memory 198660 kb
Host smart-73b7e108-96b6-4615-a29c-0f5cc22a3d19
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48364460 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.48364460
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.156514561
Short name T837
Test name
Test status
Simulation time 42673163 ps
CPU time 0.59 seconds
Started Jul 01 04:27:27 PM PDT 24
Finished Jul 01 04:27:38 PM PDT 24
Peak memory 195032 kb
Host smart-c668b912-2b61-4a5d-b4d6-e732ac7056b8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156514561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio
_csr_rw.156514561
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.3352858263
Short name T761
Test name
Test status
Simulation time 12094273 ps
CPU time 0.62 seconds
Started Jul 01 04:27:38 PM PDT 24
Finished Jul 01 04:27:49 PM PDT 24
Peak memory 194324 kb
Host smart-80698ffc-dd4a-41b2-8af0-d3646a4db58d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352858263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.3352858263
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1584603220
Short name T834
Test name
Test status
Simulation time 67004294 ps
CPU time 0.83 seconds
Started Jul 01 04:27:18 PM PDT 24
Finished Jul 01 04:27:31 PM PDT 24
Peak memory 197656 kb
Host smart-18cf03f5-14a6-404e-bfa4-66f298be1c39
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584603220 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.1584603220
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.4098564692
Short name T799
Test name
Test status
Simulation time 44558310 ps
CPU time 1.15 seconds
Started Jul 01 04:27:13 PM PDT 24
Finished Jul 01 04:27:28 PM PDT 24
Peak memory 198560 kb
Host smart-b704ee3a-8518-4502-b16f-c3094af9424f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098564692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.4098564692
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.180881875
Short name T36
Test name
Test status
Simulation time 69271528 ps
CPU time 1.11 seconds
Started Jul 01 04:27:34 PM PDT 24
Finished Jul 01 04:27:47 PM PDT 24
Peak memory 198564 kb
Host smart-c65bbb1e-e50c-459e-8faa-5983c7bb7152
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180881875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.180881875
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1217620687
Short name T729
Test name
Test status
Simulation time 156554006 ps
CPU time 0.93 seconds
Started Jul 01 04:27:57 PM PDT 24
Finished Jul 01 04:28:04 PM PDT 24
Peak memory 198424 kb
Host smart-1815fe38-ec5d-48f8-8625-1cacb474a196
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217620687 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1217620687
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3705701598
Short name T93
Test name
Test status
Simulation time 38033318 ps
CPU time 0.57 seconds
Started Jul 01 04:27:34 PM PDT 24
Finished Jul 01 04:27:45 PM PDT 24
Peak memory 193900 kb
Host smart-c58552fd-d83c-497b-a838-98c1540d0cac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705701598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3705701598
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2091424573
Short name T795
Test name
Test status
Simulation time 13582932 ps
CPU time 0.59 seconds
Started Jul 01 04:27:41 PM PDT 24
Finished Jul 01 04:27:51 PM PDT 24
Peak memory 194608 kb
Host smart-b39830c2-b700-407b-b8aa-6ea57347d2ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091424573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2091424573
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1269315683
Short name T790
Test name
Test status
Simulation time 77536782 ps
CPU time 0.8 seconds
Started Jul 01 04:27:32 PM PDT 24
Finished Jul 01 04:27:43 PM PDT 24
Peak memory 196788 kb
Host smart-32918ce9-ff24-42b3-8666-7b7849a97e44
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269315683 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1269315683
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2878800228
Short name T765
Test name
Test status
Simulation time 940640362 ps
CPU time 1.37 seconds
Started Jul 01 04:27:30 PM PDT 24
Finished Jul 01 04:27:42 PM PDT 24
Peak memory 198564 kb
Host smart-8093db6b-cb90-4f73-a73e-7b92101e29e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878800228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.2878800228
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1158933613
Short name T50
Test name
Test status
Simulation time 131176578 ps
CPU time 1.45 seconds
Started Jul 01 04:27:36 PM PDT 24
Finished Jul 01 04:27:48 PM PDT 24
Peak memory 198708 kb
Host smart-69fb118a-68ba-46ca-9467-31ca59420267
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158933613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.1158933613
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1721644002
Short name T789
Test name
Test status
Simulation time 62514689 ps
CPU time 0.91 seconds
Started Jul 01 04:27:33 PM PDT 24
Finished Jul 01 04:27:44 PM PDT 24
Peak memory 198480 kb
Host smart-0ba17d53-1b5f-47d3-a3b7-9055b0d96297
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721644002 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1721644002
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.3323931410
Short name T839
Test name
Test status
Simulation time 14724235 ps
CPU time 0.57 seconds
Started Jul 01 04:27:32 PM PDT 24
Finished Jul 01 04:27:43 PM PDT 24
Peak memory 194280 kb
Host smart-e8940279-ce83-49ae-932e-ce8a47aea1df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323931410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.3323931410
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1531245179
Short name T792
Test name
Test status
Simulation time 38962519 ps
CPU time 0.8 seconds
Started Jul 01 04:27:45 PM PDT 24
Finished Jul 01 04:27:55 PM PDT 24
Peak memory 197072 kb
Host smart-be4f415a-9148-40e0-b05d-dead02c4058e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531245179 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.1531245179
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1234523248
Short name T802
Test name
Test status
Simulation time 54648664 ps
CPU time 2.93 seconds
Started Jul 01 04:27:30 PM PDT 24
Finished Jul 01 04:27:45 PM PDT 24
Peak memory 198760 kb
Host smart-65f93702-3f0c-457a-87a3-2ee7ecd9babf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234523248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.1234523248
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.290021507
Short name T45
Test name
Test status
Simulation time 301752712 ps
CPU time 0.98 seconds
Started Jul 01 04:27:34 PM PDT 24
Finished Jul 01 04:27:47 PM PDT 24
Peak memory 198596 kb
Host smart-8d70116c-6628-4f51-86db-6adb599f8894
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290021507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.gpio_tl_intg_err.290021507
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.992731189
Short name T785
Test name
Test status
Simulation time 79062650 ps
CPU time 0.78 seconds
Started Jul 01 04:27:28 PM PDT 24
Finished Jul 01 04:27:39 PM PDT 24
Peak memory 198496 kb
Host smart-f56e7792-5203-4bea-a0cf-9cc3ddb0d44e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992731189 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.992731189
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2077809255
Short name T111
Test name
Test status
Simulation time 60468718 ps
CPU time 0.6 seconds
Started Jul 01 04:27:23 PM PDT 24
Finished Jul 01 04:27:35 PM PDT 24
Peak memory 196028 kb
Host smart-e8aafff5-4dc7-4cbd-b901-5fe16ad0369d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077809255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2077809255
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.939930489
Short name T817
Test name
Test status
Simulation time 15332894 ps
CPU time 0.63 seconds
Started Jul 01 04:27:28 PM PDT 24
Finished Jul 01 04:27:40 PM PDT 24
Peak memory 194364 kb
Host smart-8b874b79-0393-4ef5-9a53-44acfdcdbf49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939930489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.939930489
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3966843129
Short name T108
Test name
Test status
Simulation time 82983721 ps
CPU time 0.83 seconds
Started Jul 01 04:27:27 PM PDT 24
Finished Jul 01 04:27:39 PM PDT 24
Peak memory 197424 kb
Host smart-167f02b5-2d2f-4d34-880d-6dc75bfb2203
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966843129 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.3966843129
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1703222909
Short name T725
Test name
Test status
Simulation time 177271860 ps
CPU time 1.41 seconds
Started Jul 01 04:27:26 PM PDT 24
Finished Jul 01 04:27:39 PM PDT 24
Peak memory 198624 kb
Host smart-c12459c7-5ec1-4268-b149-d0ab4fccff9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703222909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.1703222909
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2203336097
Short name T739
Test name
Test status
Simulation time 242199971 ps
CPU time 1.1 seconds
Started Jul 01 04:27:49 PM PDT 24
Finished Jul 01 04:27:57 PM PDT 24
Peak memory 198684 kb
Host smart-5824dc68-21e7-4981-a1c2-d9cb07077cfe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203336097 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2203336097
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2304281385
Short name T776
Test name
Test status
Simulation time 35364172 ps
CPU time 0.57 seconds
Started Jul 01 04:27:53 PM PDT 24
Finished Jul 01 04:28:00 PM PDT 24
Peak memory 193856 kb
Host smart-436d5681-b967-4e0f-81c4-4040fee8388b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304281385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.2304281385
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.434595602
Short name T840
Test name
Test status
Simulation time 12170165 ps
CPU time 0.65 seconds
Started Jul 01 04:27:30 PM PDT 24
Finished Jul 01 04:27:42 PM PDT 24
Peak memory 194520 kb
Host smart-6bc2ad22-70d5-4a0a-9c1d-76ff3514f390
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434595602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.434595602
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.541996401
Short name T91
Test name
Test status
Simulation time 493232720 ps
CPU time 0.83 seconds
Started Jul 01 04:27:33 PM PDT 24
Finished Jul 01 04:27:44 PM PDT 24
Peak memory 196844 kb
Host smart-1d729ba9-7b78-4f40-b622-4d2d06306e3e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541996401 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 16.gpio_same_csr_outstanding.541996401
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.555490005
Short name T847
Test name
Test status
Simulation time 286486566 ps
CPU time 3.09 seconds
Started Jul 01 04:27:41 PM PDT 24
Finished Jul 01 04:27:53 PM PDT 24
Peak memory 198952 kb
Host smart-4ffb8816-b784-4e1f-abec-3fefe76132e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555490005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.555490005
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.383532302
Short name T801
Test name
Test status
Simulation time 51766911 ps
CPU time 0.87 seconds
Started Jul 01 04:27:27 PM PDT 24
Finished Jul 01 04:27:39 PM PDT 24
Peak memory 198040 kb
Host smart-2f206316-2930-45df-b4c4-3f22bffc33da
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383532302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.383532302
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3146325318
Short name T724
Test name
Test status
Simulation time 30370077 ps
CPU time 1.3 seconds
Started Jul 01 04:27:33 PM PDT 24
Finished Jul 01 04:27:44 PM PDT 24
Peak memory 198656 kb
Host smart-6588da37-463e-44ca-9c99-e3ade142fc09
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146325318 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3146325318
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.570566122
Short name T87
Test name
Test status
Simulation time 37843660 ps
CPU time 0.62 seconds
Started Jul 01 04:27:40 PM PDT 24
Finished Jul 01 04:27:50 PM PDT 24
Peak memory 193864 kb
Host smart-a616aa3a-824d-41a1-b81b-4fad015b5e0a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570566122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.570566122
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.884454019
Short name T746
Test name
Test status
Simulation time 13553496 ps
CPU time 0.6 seconds
Started Jul 01 04:27:24 PM PDT 24
Finished Jul 01 04:27:35 PM PDT 24
Peak memory 194944 kb
Host smart-c9006e1c-585e-4a81-af1e-7b3d047791c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884454019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.884454019
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1457273113
Short name T797
Test name
Test status
Simulation time 18749861 ps
CPU time 0.8 seconds
Started Jul 01 04:27:27 PM PDT 24
Finished Jul 01 04:27:39 PM PDT 24
Peak memory 196860 kb
Host smart-974c28c5-58d9-42f2-a06b-34fefdc54f2c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457273113 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.1457273113
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1637252463
Short name T728
Test name
Test status
Simulation time 637347605 ps
CPU time 1.49 seconds
Started Jul 01 04:27:24 PM PDT 24
Finished Jul 01 04:27:36 PM PDT 24
Peak memory 198816 kb
Host smart-334ed6f4-05e8-4516-a54e-e9f4391bda66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637252463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1637252463
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1335569836
Short name T39
Test name
Test status
Simulation time 50362834 ps
CPU time 0.89 seconds
Started Jul 01 04:27:26 PM PDT 24
Finished Jul 01 04:27:38 PM PDT 24
Peak memory 198336 kb
Host smart-b1807f51-3462-4272-af3c-e6127274f4ca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335569836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1335569836
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.510759766
Short name T750
Test name
Test status
Simulation time 79189083 ps
CPU time 0.71 seconds
Started Jul 01 04:27:29 PM PDT 24
Finished Jul 01 04:27:41 PM PDT 24
Peak memory 198472 kb
Host smart-7a8801d8-3728-44dd-a443-d9fdad8cd537
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510759766 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.510759766
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.4000154982
Short name T768
Test name
Test status
Simulation time 76753105 ps
CPU time 0.61 seconds
Started Jul 01 04:27:38 PM PDT 24
Finished Jul 01 04:27:49 PM PDT 24
Peak memory 195636 kb
Host smart-6a21a200-96e4-457d-8279-e00c54371ab2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000154982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.4000154982
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.3076402773
Short name T744
Test name
Test status
Simulation time 45542179 ps
CPU time 0.59 seconds
Started Jul 01 04:27:39 PM PDT 24
Finished Jul 01 04:27:50 PM PDT 24
Peak memory 194960 kb
Host smart-d451c6e6-4ba2-4e67-b4f4-ffcb725d09f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076402773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.3076402773
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2647359382
Short name T842
Test name
Test status
Simulation time 138871519 ps
CPU time 0.84 seconds
Started Jul 01 04:27:45 PM PDT 24
Finished Jul 01 04:27:54 PM PDT 24
Peak memory 197480 kb
Host smart-264251f5-04ec-44e0-a991-2fe452f4b6c5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647359382 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2647359382
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3144946291
Short name T805
Test name
Test status
Simulation time 37933948 ps
CPU time 1.93 seconds
Started Jul 01 04:27:33 PM PDT 24
Finished Jul 01 04:27:46 PM PDT 24
Peak memory 198572 kb
Host smart-010a830e-0a76-46aa-a504-32e971149b9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144946291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3144946291
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.650782474
Short name T763
Test name
Test status
Simulation time 69748630 ps
CPU time 0.82 seconds
Started Jul 01 04:27:23 PM PDT 24
Finished Jul 01 04:27:35 PM PDT 24
Peak memory 197796 kb
Host smart-feb467a1-3a78-4dca-b346-4b0077954b08
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650782474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.650782474
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1138079997
Short name T770
Test name
Test status
Simulation time 28904027 ps
CPU time 1.25 seconds
Started Jul 01 04:27:26 PM PDT 24
Finished Jul 01 04:27:38 PM PDT 24
Peak memory 195556 kb
Host smart-51f48dde-7b83-4e2a-95cb-4a4d76d9f84f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138079997 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.1138079997
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3385510532
Short name T90
Test name
Test status
Simulation time 35866090 ps
CPU time 0.57 seconds
Started Jul 01 04:27:28 PM PDT 24
Finished Jul 01 04:27:39 PM PDT 24
Peak memory 193812 kb
Host smart-71723b68-6db1-4ccc-8a0f-4180c17379ae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385510532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.3385510532
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.4157447280
Short name T830
Test name
Test status
Simulation time 48393916 ps
CPU time 0.6 seconds
Started Jul 01 04:27:39 PM PDT 24
Finished Jul 01 04:27:50 PM PDT 24
Peak memory 194904 kb
Host smart-ce519981-bf15-4ef6-914b-de80c2216bbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157447280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.4157447280
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.900854487
Short name T106
Test name
Test status
Simulation time 57938385 ps
CPU time 0.64 seconds
Started Jul 01 04:27:32 PM PDT 24
Finished Jul 01 04:27:43 PM PDT 24
Peak memory 195268 kb
Host smart-48f09709-99a8-4cfd-bed6-264f1644ff28
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900854487 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.900854487
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1456573640
Short name T844
Test name
Test status
Simulation time 217127065 ps
CPU time 1.27 seconds
Started Jul 01 04:27:13 PM PDT 24
Finished Jul 01 04:27:29 PM PDT 24
Peak memory 198592 kb
Host smart-22ba2343-1415-4d6d-973d-b14f9e064cb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456573640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1456573640
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.4030238544
Short name T113
Test name
Test status
Simulation time 46907123 ps
CPU time 0.84 seconds
Started Jul 01 04:27:31 PM PDT 24
Finished Jul 01 04:27:42 PM PDT 24
Peak memory 197448 kb
Host smart-ac9dac66-c45e-41cb-8549-feb744d7f6a1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030238544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.4030238544
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.339467123
Short name T94
Test name
Test status
Simulation time 47201612 ps
CPU time 0.78 seconds
Started Jul 01 04:27:22 PM PDT 24
Finished Jul 01 04:27:35 PM PDT 24
Peak memory 197204 kb
Host smart-956c6ad9-1eb3-46c0-b086-ced78a237a0e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339467123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.339467123
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.498940743
Short name T112
Test name
Test status
Simulation time 325388521 ps
CPU time 2.88 seconds
Started Jul 01 04:27:15 PM PDT 24
Finished Jul 01 04:27:35 PM PDT 24
Peak memory 197492 kb
Host smart-b0cccc0f-93b6-4302-8f08-52db3cbb547f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498940743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.498940743
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1837195358
Short name T760
Test name
Test status
Simulation time 18494139 ps
CPU time 0.69 seconds
Started Jul 01 04:27:06 PM PDT 24
Finished Jul 01 04:27:20 PM PDT 24
Peak memory 195684 kb
Host smart-2f21f932-a438-4782-846b-0e0d3c54aa3b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837195358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1837195358
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.336800856
Short name T759
Test name
Test status
Simulation time 21046226 ps
CPU time 0.79 seconds
Started Jul 01 04:27:06 PM PDT 24
Finished Jul 01 04:27:21 PM PDT 24
Peak memory 198432 kb
Host smart-3b9eb701-8201-45a0-83b1-21e98a5ffd25
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336800856 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.336800856
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.573982273
Short name T772
Test name
Test status
Simulation time 11236787 ps
CPU time 0.61 seconds
Started Jul 01 04:27:25 PM PDT 24
Finished Jul 01 04:27:36 PM PDT 24
Peak memory 195176 kb
Host smart-2c953710-7feb-40f9-8c3a-c45144ec18bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573982273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_
csr_rw.573982273
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1847017528
Short name T741
Test name
Test status
Simulation time 47111049 ps
CPU time 0.62 seconds
Started Jul 01 04:27:18 PM PDT 24
Finished Jul 01 04:27:31 PM PDT 24
Peak memory 194412 kb
Host smart-6bfe123f-96f6-4f68-8ab1-85051d60ca04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847017528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1847017528
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2720770568
Short name T101
Test name
Test status
Simulation time 46987699 ps
CPU time 0.86 seconds
Started Jul 01 04:27:13 PM PDT 24
Finished Jul 01 04:27:28 PM PDT 24
Peak memory 196648 kb
Host smart-845fe1cd-24c7-48e0-b501-a439aeb85ab6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720770568 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2720770568
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1145533866
Short name T782
Test name
Test status
Simulation time 192942328 ps
CPU time 2.93 seconds
Started Jul 01 04:27:06 PM PDT 24
Finished Jul 01 04:27:24 PM PDT 24
Peak memory 198552 kb
Host smart-cccc60f8-8672-49c1-84bc-61d4e4852117
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145533866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1145533866
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3775355334
Short name T757
Test name
Test status
Simulation time 45451806 ps
CPU time 0.86 seconds
Started Jul 01 04:27:23 PM PDT 24
Finished Jul 01 04:27:36 PM PDT 24
Peak memory 197692 kb
Host smart-3869a9b2-ccb2-4f4c-b4c2-6f7c246caae5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775355334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3775355334
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2520050243
Short name T846
Test name
Test status
Simulation time 27387395 ps
CPU time 0.59 seconds
Started Jul 01 04:27:14 PM PDT 24
Finished Jul 01 04:27:29 PM PDT 24
Peak memory 194312 kb
Host smart-6ce2723d-6b91-4bb9-b954-fa6c967c54a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520050243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2520050243
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.527710242
Short name T800
Test name
Test status
Simulation time 17824640 ps
CPU time 0.61 seconds
Started Jul 01 04:27:48 PM PDT 24
Finished Jul 01 04:27:56 PM PDT 24
Peak memory 194596 kb
Host smart-342ad8be-e9a2-4839-a4b9-cc69a74e46d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527710242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.527710242
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.2836519171
Short name T826
Test name
Test status
Simulation time 16884702 ps
CPU time 0.63 seconds
Started Jul 01 04:27:42 PM PDT 24
Finished Jul 01 04:27:53 PM PDT 24
Peak memory 194932 kb
Host smart-5cb0ed68-661a-41a4-8e06-715a44353357
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836519171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.2836519171
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.2528290930
Short name T737
Test name
Test status
Simulation time 15091408 ps
CPU time 0.59 seconds
Started Jul 01 04:27:29 PM PDT 24
Finished Jul 01 04:27:40 PM PDT 24
Peak memory 194204 kb
Host smart-447d83ec-0c09-4337-aa76-c29641f1f3c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528290930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.2528290930
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.659449110
Short name T823
Test name
Test status
Simulation time 28737005 ps
CPU time 0.58 seconds
Started Jul 01 04:27:51 PM PDT 24
Finished Jul 01 04:27:58 PM PDT 24
Peak memory 194240 kb
Host smart-2312f2ab-9595-4b92-bff0-b9f784cee006
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659449110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.659449110
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.392835141
Short name T769
Test name
Test status
Simulation time 15921937 ps
CPU time 0.59 seconds
Started Jul 01 04:27:26 PM PDT 24
Finished Jul 01 04:27:37 PM PDT 24
Peak memory 194424 kb
Host smart-1e31b5cc-cb61-433e-936b-666e4801c176
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392835141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.392835141
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2979756160
Short name T836
Test name
Test status
Simulation time 13703598 ps
CPU time 0.58 seconds
Started Jul 01 04:27:38 PM PDT 24
Finished Jul 01 04:27:49 PM PDT 24
Peak memory 194292 kb
Host smart-d10e12b8-be7a-4837-b0c2-20f4fc2af4ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979756160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2979756160
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.742431176
Short name T791
Test name
Test status
Simulation time 16655276 ps
CPU time 0.59 seconds
Started Jul 01 04:27:28 PM PDT 24
Finished Jul 01 04:27:40 PM PDT 24
Peak memory 195068 kb
Host smart-6885e7ff-6a7e-46df-afd3-f744cdae7d8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742431176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.742431176
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1276816201
Short name T754
Test name
Test status
Simulation time 76159402 ps
CPU time 0.56 seconds
Started Jul 01 04:27:32 PM PDT 24
Finished Jul 01 04:27:43 PM PDT 24
Peak memory 194280 kb
Host smart-053067a9-e672-4d17-b24f-faa078c23a96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276816201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1276816201
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.777492636
Short name T766
Test name
Test status
Simulation time 14343166 ps
CPU time 0.6 seconds
Started Jul 01 04:27:49 PM PDT 24
Finished Jul 01 04:27:56 PM PDT 24
Peak memory 194392 kb
Host smart-d4e49c22-ab73-4f73-a93f-30ad1345d7d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777492636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.777492636
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3656157049
Short name T86
Test name
Test status
Simulation time 119551582 ps
CPU time 0.65 seconds
Started Jul 01 04:27:15 PM PDT 24
Finished Jul 01 04:27:29 PM PDT 24
Peak memory 195716 kb
Host smart-5053508c-1544-45e8-8aaf-4f34498d88ae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656157049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.3656157049
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3775890793
Short name T845
Test name
Test status
Simulation time 62067569 ps
CPU time 2.14 seconds
Started Jul 01 04:27:18 PM PDT 24
Finished Jul 01 04:27:33 PM PDT 24
Peak memory 197224 kb
Host smart-05d606a8-5453-42f0-8722-21fef31fcd19
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775890793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.3775890793
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.629251144
Short name T92
Test name
Test status
Simulation time 36292151 ps
CPU time 0.66 seconds
Started Jul 01 04:27:04 PM PDT 24
Finished Jul 01 04:27:18 PM PDT 24
Peak memory 195548 kb
Host smart-496fbcad-070d-46ed-85c2-7b5898e865aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629251144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.629251144
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3929799115
Short name T835
Test name
Test status
Simulation time 26846700 ps
CPU time 1.18 seconds
Started Jul 01 04:27:23 PM PDT 24
Finished Jul 01 04:27:36 PM PDT 24
Peak memory 198592 kb
Host smart-b3cfc1ad-b35e-4db6-a3d0-0dfc85bb3fc9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929799115 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3929799115
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3899959944
Short name T824
Test name
Test status
Simulation time 38134223 ps
CPU time 0.61 seconds
Started Jul 01 04:27:05 PM PDT 24
Finished Jul 01 04:27:20 PM PDT 24
Peak memory 195836 kb
Host smart-cfdc5b85-fa40-4e89-b185-0d58cd90951a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899959944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.3899959944
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3350326092
Short name T798
Test name
Test status
Simulation time 15856698 ps
CPU time 0.6 seconds
Started Jul 01 04:27:06 PM PDT 24
Finished Jul 01 04:27:21 PM PDT 24
Peak memory 194244 kb
Host smart-aa5ed304-1bc2-40b9-bb80-02f12b08a680
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350326092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3350326092
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2911691048
Short name T105
Test name
Test status
Simulation time 66160385 ps
CPU time 0.68 seconds
Started Jul 01 04:27:07 PM PDT 24
Finished Jul 01 04:27:22 PM PDT 24
Peak memory 195096 kb
Host smart-a5dd7dbe-e353-4956-bdac-52e504ef5db6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911691048 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.2911691048
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3064377688
Short name T818
Test name
Test status
Simulation time 55127051 ps
CPU time 1.29 seconds
Started Jul 01 04:27:23 PM PDT 24
Finished Jul 01 04:27:36 PM PDT 24
Peak memory 198592 kb
Host smart-93735c3f-4450-40f8-a125-1c385868d34b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064377688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3064377688
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.40209692
Short name T49
Test name
Test status
Simulation time 170796731 ps
CPU time 0.89 seconds
Started Jul 01 04:27:07 PM PDT 24
Finished Jul 01 04:27:23 PM PDT 24
Peak memory 198420 kb
Host smart-8b5cbd72-58ce-4453-85c0-8e2d76f3e63d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40209692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_tl_intg_err.40209692
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.143071468
Short name T832
Test name
Test status
Simulation time 44819540 ps
CPU time 0.61 seconds
Started Jul 01 04:27:53 PM PDT 24
Finished Jul 01 04:28:00 PM PDT 24
Peak memory 194468 kb
Host smart-0d10b306-17cf-45c2-812f-7441cde05850
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143071468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.143071468
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.1084378098
Short name T748
Test name
Test status
Simulation time 125671976 ps
CPU time 0.68 seconds
Started Jul 01 04:27:33 PM PDT 24
Finished Jul 01 04:27:44 PM PDT 24
Peak memory 194520 kb
Host smart-8694a8ab-50ba-4269-80c4-f6c40f7a5641
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084378098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1084378098
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.4196792431
Short name T827
Test name
Test status
Simulation time 15581550 ps
CPU time 0.65 seconds
Started Jul 01 04:27:35 PM PDT 24
Finished Jul 01 04:27:46 PM PDT 24
Peak memory 194312 kb
Host smart-a9b63e78-29f6-494d-8b84-16f2f4e2e7f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196792431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.4196792431
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.2039983337
Short name T730
Test name
Test status
Simulation time 16322218 ps
CPU time 0.63 seconds
Started Jul 01 04:27:31 PM PDT 24
Finished Jul 01 04:27:43 PM PDT 24
Peak memory 194312 kb
Host smart-fb1af26f-ee77-42b0-8721-bb0d871e2eb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039983337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.2039983337
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.984796892
Short name T808
Test name
Test status
Simulation time 48948443 ps
CPU time 0.64 seconds
Started Jul 01 04:27:33 PM PDT 24
Finished Jul 01 04:27:44 PM PDT 24
Peak memory 194600 kb
Host smart-7133dd74-f81e-49fe-9eaf-366c4e5429ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984796892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.984796892
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3791843200
Short name T804
Test name
Test status
Simulation time 43385553 ps
CPU time 0.57 seconds
Started Jul 01 04:27:34 PM PDT 24
Finished Jul 01 04:27:45 PM PDT 24
Peak memory 194900 kb
Host smart-8a10fb66-0d1a-4e6b-aaac-54bbd0ee87b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791843200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3791843200
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2135238111
Short name T742
Test name
Test status
Simulation time 12502592 ps
CPU time 0.56 seconds
Started Jul 01 04:27:35 PM PDT 24
Finished Jul 01 04:27:47 PM PDT 24
Peak memory 194256 kb
Host smart-9294cf5e-d6b6-4f7b-9665-d59a19199953
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135238111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2135238111
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1074867729
Short name T793
Test name
Test status
Simulation time 45957928 ps
CPU time 0.61 seconds
Started Jul 01 04:27:33 PM PDT 24
Finished Jul 01 04:27:45 PM PDT 24
Peak memory 194252 kb
Host smart-d39cb42d-5e16-4bce-abb1-ceb07499aebc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074867729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1074867729
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1589332313
Short name T820
Test name
Test status
Simulation time 32823434 ps
CPU time 0.57 seconds
Started Jul 01 04:27:29 PM PDT 24
Finished Jul 01 04:27:40 PM PDT 24
Peak memory 194300 kb
Host smart-cf6b5800-b4cf-469f-88a7-c4c645786f33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589332313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1589332313
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.2480933221
Short name T781
Test name
Test status
Simulation time 133272803 ps
CPU time 0.6 seconds
Started Jul 01 04:27:28 PM PDT 24
Finished Jul 01 04:27:39 PM PDT 24
Peak memory 194380 kb
Host smart-a437163a-cbfd-402a-932b-f72f2b38eaee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480933221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.2480933221
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3006102930
Short name T803
Test name
Test status
Simulation time 66412223 ps
CPU time 0.83 seconds
Started Jul 01 04:27:07 PM PDT 24
Finished Jul 01 04:27:22 PM PDT 24
Peak memory 197052 kb
Host smart-2a194ff4-0721-4236-b8d7-3f4290adbf10
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006102930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3006102930
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1914861655
Short name T98
Test name
Test status
Simulation time 120363416 ps
CPU time 2.24 seconds
Started Jul 01 04:27:26 PM PDT 24
Finished Jul 01 04:27:40 PM PDT 24
Peak memory 198576 kb
Host smart-7ed9ef4c-55d6-4f21-9833-0977bf0ced08
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914861655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1914861655
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1782021328
Short name T96
Test name
Test status
Simulation time 32560642 ps
CPU time 0.6 seconds
Started Jul 01 04:27:17 PM PDT 24
Finished Jul 01 04:27:31 PM PDT 24
Peak memory 195384 kb
Host smart-15aa1aad-6955-408a-bde8-72e6e6904a06
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782021328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1782021328
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2956809678
Short name T811
Test name
Test status
Simulation time 51284804 ps
CPU time 0.66 seconds
Started Jul 01 04:27:04 PM PDT 24
Finished Jul 01 04:27:18 PM PDT 24
Peak memory 197840 kb
Host smart-2163bb43-18cf-4947-861d-1564b47ea4f3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956809678 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2956809678
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.704288861
Short name T88
Test name
Test status
Simulation time 40791986 ps
CPU time 0.57 seconds
Started Jul 01 04:27:06 PM PDT 24
Finished Jul 01 04:27:20 PM PDT 24
Peak memory 194532 kb
Host smart-ce5f8ffa-1ae7-40d2-8fab-c935f994c6d3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704288861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_
csr_rw.704288861
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.1686596744
Short name T743
Test name
Test status
Simulation time 14812311 ps
CPU time 0.6 seconds
Started Jul 01 04:27:26 PM PDT 24
Finished Jul 01 04:27:38 PM PDT 24
Peak memory 194324 kb
Host smart-a1d5e939-49fb-4646-8178-5ec33247534f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686596744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.1686596744
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1785678778
Short name T822
Test name
Test status
Simulation time 38796618 ps
CPU time 0.7 seconds
Started Jul 01 04:27:05 PM PDT 24
Finished Jul 01 04:27:20 PM PDT 24
Peak memory 196104 kb
Host smart-a61d2411-d5fc-4744-8249-659a6d5986e6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785678778 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.1785678778
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2700890290
Short name T807
Test name
Test status
Simulation time 195009525 ps
CPU time 2.31 seconds
Started Jul 01 04:27:30 PM PDT 24
Finished Jul 01 04:27:44 PM PDT 24
Peak memory 198644 kb
Host smart-39ff3241-4ebb-4cb8-b977-6dc01b063725
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700890290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2700890290
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1858859700
Short name T843
Test name
Test status
Simulation time 344244779 ps
CPU time 1.09 seconds
Started Jul 01 04:27:02 PM PDT 24
Finished Jul 01 04:27:17 PM PDT 24
Peak memory 198568 kb
Host smart-c3d0a5f4-cf00-41e1-9e8a-a1959a3b2031
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858859700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.1858859700
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.3928866882
Short name T756
Test name
Test status
Simulation time 18311524 ps
CPU time 0.59 seconds
Started Jul 01 04:27:39 PM PDT 24
Finished Jul 01 04:27:49 PM PDT 24
Peak memory 195188 kb
Host smart-a5ce9ed0-d6d6-463a-9ca9-f83098e0bd55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928866882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.3928866882
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.3912682181
Short name T774
Test name
Test status
Simulation time 17373871 ps
CPU time 0.62 seconds
Started Jul 01 04:27:38 PM PDT 24
Finished Jul 01 04:27:49 PM PDT 24
Peak memory 194328 kb
Host smart-6eb621f1-b450-4b3e-8150-71750e9919e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912682181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.3912682181
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.3209333982
Short name T815
Test name
Test status
Simulation time 14054892 ps
CPU time 0.59 seconds
Started Jul 01 04:27:45 PM PDT 24
Finished Jul 01 04:27:54 PM PDT 24
Peak memory 194244 kb
Host smart-80243c3f-ab1e-4ee8-addd-17da765eab02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209333982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3209333982
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1202795452
Short name T727
Test name
Test status
Simulation time 17299141 ps
CPU time 0.62 seconds
Started Jul 01 04:27:28 PM PDT 24
Finished Jul 01 04:27:40 PM PDT 24
Peak memory 194252 kb
Host smart-24e6a6b4-194a-423c-a477-c9d258e55e92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202795452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1202795452
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.164475855
Short name T821
Test name
Test status
Simulation time 15483276 ps
CPU time 0.56 seconds
Started Jul 01 04:27:48 PM PDT 24
Finished Jul 01 04:27:56 PM PDT 24
Peak memory 194956 kb
Host smart-3dd3d814-2728-4a13-862f-8114a4da3b59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164475855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.164475855
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.372908532
Short name T819
Test name
Test status
Simulation time 36339806 ps
CPU time 0.6 seconds
Started Jul 01 04:27:38 PM PDT 24
Finished Jul 01 04:27:49 PM PDT 24
Peak memory 194904 kb
Host smart-d8743d89-cb97-4b00-8f59-f7f56202efe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372908532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.372908532
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2347301056
Short name T734
Test name
Test status
Simulation time 39076015 ps
CPU time 0.59 seconds
Started Jul 01 04:27:34 PM PDT 24
Finished Jul 01 04:27:45 PM PDT 24
Peak memory 194308 kb
Host smart-014a2ca1-1b18-4527-9b20-86c35756cbce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347301056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2347301056
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.3725084919
Short name T786
Test name
Test status
Simulation time 14870987 ps
CPU time 0.62 seconds
Started Jul 01 04:27:32 PM PDT 24
Finished Jul 01 04:27:43 PM PDT 24
Peak memory 194276 kb
Host smart-c07813ea-670b-485e-abab-db57658b361b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725084919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.3725084919
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.930216111
Short name T733
Test name
Test status
Simulation time 14132392 ps
CPU time 0.56 seconds
Started Jul 01 04:27:36 PM PDT 24
Finished Jul 01 04:27:51 PM PDT 24
Peak memory 194216 kb
Host smart-3e0b4960-124a-4fb7-b630-7dfb072f6a3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930216111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.930216111
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2166633334
Short name T806
Test name
Test status
Simulation time 14007875 ps
CPU time 0.61 seconds
Started Jul 01 04:27:29 PM PDT 24
Finished Jul 01 04:27:40 PM PDT 24
Peak memory 194260 kb
Host smart-1579edb7-51be-4583-a677-22ea18c979f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166633334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2166633334
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2884246425
Short name T775
Test name
Test status
Simulation time 119840543 ps
CPU time 0.86 seconds
Started Jul 01 04:27:18 PM PDT 24
Finished Jul 01 04:27:31 PM PDT 24
Peak memory 198500 kb
Host smart-7d7af236-3662-42e1-8a36-a52a862df889
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884246425 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2884246425
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.118703150
Short name T109
Test name
Test status
Simulation time 13604557 ps
CPU time 0.61 seconds
Started Jul 01 04:27:18 PM PDT 24
Finished Jul 01 04:27:32 PM PDT 24
Peak memory 196024 kb
Host smart-e813fa1b-bb6c-417d-bdb7-6d053eeea0df
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118703150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.118703150
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3665880921
Short name T735
Test name
Test status
Simulation time 30281348 ps
CPU time 0.56 seconds
Started Jul 01 04:27:07 PM PDT 24
Finished Jul 01 04:27:22 PM PDT 24
Peak memory 194296 kb
Host smart-7ba4baff-2d2f-4760-bf00-dfcb93f45776
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665880921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3665880921
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3135356813
Short name T829
Test name
Test status
Simulation time 24819461 ps
CPU time 0.74 seconds
Started Jul 01 04:27:19 PM PDT 24
Finished Jul 01 04:27:33 PM PDT 24
Peak memory 196680 kb
Host smart-cb74f3f0-14f6-4053-bf5b-a95e33b07ac4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135356813 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3135356813
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3747071135
Short name T740
Test name
Test status
Simulation time 197406234 ps
CPU time 3.34 seconds
Started Jul 01 04:27:30 PM PDT 24
Finished Jul 01 04:27:45 PM PDT 24
Peak memory 198592 kb
Host smart-7e8cbd61-792e-4f78-9f0c-cbdcda5fa9f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747071135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3747071135
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1547512270
Short name T47
Test name
Test status
Simulation time 93139996 ps
CPU time 1.09 seconds
Started Jul 01 04:27:15 PM PDT 24
Finished Jul 01 04:27:30 PM PDT 24
Peak memory 198576 kb
Host smart-f899c539-8e45-459e-af67-056c62a018e1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547512270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.1547512270
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2219163427
Short name T771
Test name
Test status
Simulation time 25668732 ps
CPU time 1.15 seconds
Started Jul 01 04:27:23 PM PDT 24
Finished Jul 01 04:27:36 PM PDT 24
Peak memory 198756 kb
Host smart-b1c29891-7a88-4144-9b08-1624b75d8073
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219163427 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2219163427
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.624564115
Short name T838
Test name
Test status
Simulation time 11098736 ps
CPU time 0.58 seconds
Started Jul 01 04:27:06 PM PDT 24
Finished Jul 01 04:27:27 PM PDT 24
Peak memory 195000 kb
Host smart-711b8478-8c24-4536-9c1e-8d05afec96e8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624564115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_
csr_rw.624564115
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.365467452
Short name T814
Test name
Test status
Simulation time 28508592 ps
CPU time 0.6 seconds
Started Jul 01 04:27:40 PM PDT 24
Finished Jul 01 04:27:50 PM PDT 24
Peak memory 194272 kb
Host smart-6bf1189c-06c4-4ebc-b438-ecd048be53fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365467452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.365467452
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2942247887
Short name T102
Test name
Test status
Simulation time 41515812 ps
CPU time 0.65 seconds
Started Jul 01 04:27:24 PM PDT 24
Finished Jul 01 04:27:35 PM PDT 24
Peak memory 195320 kb
Host smart-a0d0bbd8-d133-4b90-aba4-ff76f6099431
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942247887 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.2942247887
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.779416490
Short name T778
Test name
Test status
Simulation time 78141393 ps
CPU time 1.18 seconds
Started Jul 01 04:27:19 PM PDT 24
Finished Jul 01 04:27:34 PM PDT 24
Peak memory 198556 kb
Host smart-0dbe6850-dfe4-4892-8ead-cb483d522462
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779416490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.779416490
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2373443189
Short name T833
Test name
Test status
Simulation time 81422859 ps
CPU time 1.12 seconds
Started Jul 01 04:27:31 PM PDT 24
Finished Jul 01 04:27:42 PM PDT 24
Peak memory 198688 kb
Host smart-ab029698-3772-429f-b9be-8cb76e903d2f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373443189 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.2373443189
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3784414953
Short name T97
Test name
Test status
Simulation time 44968098 ps
CPU time 0.62 seconds
Started Jul 01 04:27:11 PM PDT 24
Finished Jul 01 04:27:30 PM PDT 24
Peak memory 196156 kb
Host smart-5eff3d16-2374-40b2-a1c7-7a6ef0d5a01f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784414953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3784414953
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3602694815
Short name T767
Test name
Test status
Simulation time 28314967 ps
CPU time 0.67 seconds
Started Jul 01 04:27:24 PM PDT 24
Finished Jul 01 04:27:36 PM PDT 24
Peak memory 194948 kb
Host smart-abc346c9-5025-40f5-aa35-4faa6768002d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602694815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3602694815
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.796147074
Short name T103
Test name
Test status
Simulation time 84524038 ps
CPU time 0.88 seconds
Started Jul 01 04:27:18 PM PDT 24
Finished Jul 01 04:27:32 PM PDT 24
Peak memory 197008 kb
Host smart-dcfbccd6-4114-492e-90d2-f7a452e8ad53
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796147074 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.796147074
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2199280103
Short name T747
Test name
Test status
Simulation time 827214972 ps
CPU time 1.23 seconds
Started Jul 01 04:27:23 PM PDT 24
Finished Jul 01 04:27:35 PM PDT 24
Peak memory 198628 kb
Host smart-e4324c12-abf9-4774-bcfc-76bfb2bd8c50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199280103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2199280103
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1364031953
Short name T38
Test name
Test status
Simulation time 75106803 ps
CPU time 0.91 seconds
Started Jul 01 04:27:17 PM PDT 24
Finished Jul 01 04:27:31 PM PDT 24
Peak memory 197760 kb
Host smart-c67a1cd0-2fa5-43ff-a844-a9eaab4d932f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364031953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1364031953
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1961277526
Short name T816
Test name
Test status
Simulation time 80030650 ps
CPU time 0.96 seconds
Started Jul 01 04:27:30 PM PDT 24
Finished Jul 01 04:27:41 PM PDT 24
Peak memory 198496 kb
Host smart-8b646c51-7998-4a02-bf33-3eb4af879b29
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961277526 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.1961277526
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2138806975
Short name T745
Test name
Test status
Simulation time 32103363 ps
CPU time 0.57 seconds
Started Jul 01 04:27:07 PM PDT 24
Finished Jul 01 04:27:23 PM PDT 24
Peak memory 194476 kb
Host smart-8fba25a0-137b-4813-9228-9733a2c461bb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138806975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2138806975
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.2022930057
Short name T812
Test name
Test status
Simulation time 33366223 ps
CPU time 0.59 seconds
Started Jul 01 04:27:06 PM PDT 24
Finished Jul 01 04:27:20 PM PDT 24
Peak memory 194376 kb
Host smart-75048139-be88-4d15-b7a2-d4faa6e006bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022930057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.2022930057
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.956626926
Short name T89
Test name
Test status
Simulation time 30186127 ps
CPU time 0.82 seconds
Started Jul 01 04:27:12 PM PDT 24
Finished Jul 01 04:27:27 PM PDT 24
Peak memory 197112 kb
Host smart-ecefb19d-e722-46a8-ac27-57b8c081fc08
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956626926 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 8.gpio_same_csr_outstanding.956626926
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2833598915
Short name T762
Test name
Test status
Simulation time 45532381 ps
CPU time 2.19 seconds
Started Jul 01 04:27:26 PM PDT 24
Finished Jul 01 04:27:39 PM PDT 24
Peak memory 198556 kb
Host smart-51c9c327-f6af-4efe-8cc6-41594af80f84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833598915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2833598915
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3600827673
Short name T114
Test name
Test status
Simulation time 184017896 ps
CPU time 1.44 seconds
Started Jul 01 04:27:22 PM PDT 24
Finished Jul 01 04:27:35 PM PDT 24
Peak memory 198568 kb
Host smart-881ad22a-aa62-4c0f-9df4-608ea22b0484
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600827673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.3600827673
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1470376355
Short name T749
Test name
Test status
Simulation time 28831342 ps
CPU time 1.28 seconds
Started Jul 01 04:27:24 PM PDT 24
Finished Jul 01 04:27:37 PM PDT 24
Peak memory 198660 kb
Host smart-8107347b-2d01-418f-8bf4-d17c1e91b4f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470376355 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1470376355
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1198146347
Short name T764
Test name
Test status
Simulation time 17226850 ps
CPU time 0.62 seconds
Started Jul 01 04:27:20 PM PDT 24
Finished Jul 01 04:27:33 PM PDT 24
Peak memory 195312 kb
Host smart-46531c95-e64f-4f36-9d98-b5aa3da4bc20
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198146347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1198146347
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.3297431743
Short name T794
Test name
Test status
Simulation time 51736785 ps
CPU time 0.58 seconds
Started Jul 01 04:27:07 PM PDT 24
Finished Jul 01 04:27:23 PM PDT 24
Peak memory 194904 kb
Host smart-3927662c-9526-4b5f-ab69-7ad0c70f3ac7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297431743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3297431743
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.1034199307
Short name T104
Test name
Test status
Simulation time 158051603 ps
CPU time 0.73 seconds
Started Jul 01 04:27:21 PM PDT 24
Finished Jul 01 04:27:34 PM PDT 24
Peak memory 196904 kb
Host smart-0606aa62-1bf5-4be5-8807-af984486762f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034199307 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.1034199307
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.600225173
Short name T752
Test name
Test status
Simulation time 95903298 ps
CPU time 2.98 seconds
Started Jul 01 04:27:08 PM PDT 24
Finished Jul 01 04:27:26 PM PDT 24
Peak memory 198804 kb
Host smart-8f20e48d-0435-4b30-8ccc-5fc0f002efe5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600225173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.600225173
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/default/0.gpio_alert_test.4263890710
Short name T360
Test name
Test status
Simulation time 19438787 ps
CPU time 0.56 seconds
Started Jul 01 04:48:20 PM PDT 24
Finished Jul 01 04:48:22 PM PDT 24
Peak memory 194656 kb
Host smart-4c8753c5-df71-4f42-9742-06b0a0135e2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263890710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.4263890710
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.450650666
Short name T176
Test name
Test status
Simulation time 127951376 ps
CPU time 0.82 seconds
Started Jul 01 04:48:22 PM PDT 24
Finished Jul 01 04:48:26 PM PDT 24
Peak memory 195784 kb
Host smart-c575f67c-5c45-4ca0-918f-15837936258e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450650666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.450650666
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.555548482
Short name T529
Test name
Test status
Simulation time 1376969409 ps
CPU time 19.44 seconds
Started Jul 01 04:48:24 PM PDT 24
Finished Jul 01 04:48:46 PM PDT 24
Peak memory 197560 kb
Host smart-b8c5ee14-ead5-4129-bae6-3272abddf348
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555548482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress
.555548482
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1633354678
Short name T636
Test name
Test status
Simulation time 466468785 ps
CPU time 0.89 seconds
Started Jul 01 04:48:20 PM PDT 24
Finished Jul 01 04:48:23 PM PDT 24
Peak memory 197536 kb
Host smart-033d4309-8837-4c02-8c26-5e774deb8d31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633354678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1633354678
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.4012781098
Short name T646
Test name
Test status
Simulation time 816833131 ps
CPU time 1.38 seconds
Started Jul 01 04:48:17 PM PDT 24
Finished Jul 01 04:48:19 PM PDT 24
Peak memory 197504 kb
Host smart-c7de0cc2-9fd3-4b3f-b537-78f8d14b7ce0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012781098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.4012781098
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.321944627
Short name T505
Test name
Test status
Simulation time 90891988 ps
CPU time 3.53 seconds
Started Jul 01 04:48:16 PM PDT 24
Finished Jul 01 04:48:21 PM PDT 24
Peak memory 198644 kb
Host smart-585fc25f-849b-4830-a86c-e089d59c259c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321944627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.321944627
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.2379673963
Short name T666
Test name
Test status
Simulation time 60636745 ps
CPU time 1.87 seconds
Started Jul 01 04:48:17 PM PDT 24
Finished Jul 01 04:48:19 PM PDT 24
Peak memory 196720 kb
Host smart-bf2fa959-97a1-4a3c-87a1-a4b69b80dd51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379673963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
2379673963
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.1357169611
Short name T446
Test name
Test status
Simulation time 140323773 ps
CPU time 0.95 seconds
Started Jul 01 04:48:16 PM PDT 24
Finished Jul 01 04:48:18 PM PDT 24
Peak memory 197304 kb
Host smart-2c85ea8a-e7c7-4232-9479-1708611333c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357169611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.1357169611
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.894596471
Short name T588
Test name
Test status
Simulation time 124621929 ps
CPU time 1.26 seconds
Started Jul 01 04:48:16 PM PDT 24
Finished Jul 01 04:48:18 PM PDT 24
Peak memory 196536 kb
Host smart-46121937-5020-49b9-a388-b96bc95bfc92
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894596471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.894596471
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2666729620
Short name T688
Test name
Test status
Simulation time 1029963964 ps
CPU time 4.26 seconds
Started Jul 01 04:48:22 PM PDT 24
Finished Jul 01 04:48:28 PM PDT 24
Peak memory 198708 kb
Host smart-951bf366-3023-4d9b-b15e-e384bdef6347
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666729620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2666729620
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.1235814445
Short name T271
Test name
Test status
Simulation time 83082930 ps
CPU time 1.21 seconds
Started Jul 01 04:48:22 PM PDT 24
Finished Jul 01 04:48:26 PM PDT 24
Peak memory 196988 kb
Host smart-0f645492-bf67-459f-b510-39a23d5596ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235814445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1235814445
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.1844380517
Short name T53
Test name
Test status
Simulation time 189228575 ps
CPU time 1.26 seconds
Started Jul 01 04:48:22 PM PDT 24
Finished Jul 01 04:48:25 PM PDT 24
Peak memory 197380 kb
Host smart-d57a4d08-dc15-4ea0-8734-cbfb9b43a346
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844380517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.1844380517
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1332130020
Short name T168
Test name
Test status
Simulation time 20023157095 ps
CPU time 136.33 seconds
Started Jul 01 04:48:19 PM PDT 24
Finished Jul 01 04:50:37 PM PDT 24
Peak memory 198788 kb
Host smart-a7234f6f-dda1-4c3c-b9ca-ea3607add130
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332130020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1332130020
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.4017838302
Short name T62
Test name
Test status
Simulation time 112676171436 ps
CPU time 2263.03 seconds
Started Jul 01 04:48:21 PM PDT 24
Finished Jul 01 05:26:06 PM PDT 24
Peak memory 207184 kb
Host smart-81237273-bae1-4fc3-99f2-1d31c5acf13a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4017838302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.4017838302
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.1132168564
Short name T347
Test name
Test status
Simulation time 12765873 ps
CPU time 0.59 seconds
Started Jul 01 04:48:23 PM PDT 24
Finished Jul 01 04:48:26 PM PDT 24
Peak memory 194732 kb
Host smart-da549062-be80-4462-bd64-95e00c5380d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132168564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.1132168564
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1728573766
Short name T282
Test name
Test status
Simulation time 85427235 ps
CPU time 0.72 seconds
Started Jul 01 04:48:20 PM PDT 24
Finished Jul 01 04:48:23 PM PDT 24
Peak memory 195596 kb
Host smart-226a860d-8e7d-453d-add9-1e7352980a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728573766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1728573766
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.2257072842
Short name T241
Test name
Test status
Simulation time 2858644196 ps
CPU time 29.89 seconds
Started Jul 01 04:48:22 PM PDT 24
Finished Jul 01 04:48:55 PM PDT 24
Peak memory 198248 kb
Host smart-100b2f53-48a5-44b5-9911-8dca4f6aa167
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257072842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.2257072842
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1776753438
Short name T520
Test name
Test status
Simulation time 1347989325 ps
CPU time 0.93 seconds
Started Jul 01 04:48:22 PM PDT 24
Finished Jul 01 04:48:25 PM PDT 24
Peak memory 197904 kb
Host smart-53924dcb-592a-4df4-933d-772826295190
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776753438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1776753438
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.3102543956
Short name T165
Test name
Test status
Simulation time 35074234 ps
CPU time 1.21 seconds
Started Jul 01 04:48:20 PM PDT 24
Finished Jul 01 04:48:23 PM PDT 24
Peak memory 197572 kb
Host smart-ce75bf6b-5fb0-4c47-a9e0-39b2ba882d2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102543956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.3102543956
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2231074622
Short name T286
Test name
Test status
Simulation time 147412435 ps
CPU time 1.6 seconds
Started Jul 01 04:48:19 PM PDT 24
Finished Jul 01 04:48:22 PM PDT 24
Peak memory 197392 kb
Host smart-5142850f-98ec-462f-9f10-a57220d45464
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231074622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2231074622
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.2936416465
Short name T398
Test name
Test status
Simulation time 84765513 ps
CPU time 1.9 seconds
Started Jul 01 04:48:21 PM PDT 24
Finished Jul 01 04:48:24 PM PDT 24
Peak memory 196952 kb
Host smart-c61e738f-f58f-42e2-89d8-4f47d67dc2fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936416465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
2936416465
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.701207090
Short name T222
Test name
Test status
Simulation time 26096601 ps
CPU time 0.94 seconds
Started Jul 01 04:48:19 PM PDT 24
Finished Jul 01 04:48:21 PM PDT 24
Peak memory 196624 kb
Host smart-cff49be1-c095-4fb8-b468-e6178ed7296b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701207090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.701207090
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2262460157
Short name T227
Test name
Test status
Simulation time 82939755 ps
CPU time 0.85 seconds
Started Jul 01 04:48:19 PM PDT 24
Finished Jul 01 04:48:21 PM PDT 24
Peak memory 197816 kb
Host smart-48e5e648-b9ff-41cd-90ea-da647bdd0f2d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262460157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2262460157
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2517258487
Short name T613
Test name
Test status
Simulation time 88972228 ps
CPU time 1.08 seconds
Started Jul 01 04:48:18 PM PDT 24
Finished Jul 01 04:48:20 PM PDT 24
Peak memory 198644 kb
Host smart-f8f4d351-806a-4697-b988-a4e0a28317b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517258487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2517258487
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.2628968737
Short name T52
Test name
Test status
Simulation time 119065999 ps
CPU time 0.82 seconds
Started Jul 01 04:48:23 PM PDT 24
Finished Jul 01 04:48:27 PM PDT 24
Peak memory 214276 kb
Host smart-d50a31b7-6045-446b-b3ab-762d9182a493
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628968737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2628968737
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.1256550227
Short name T596
Test name
Test status
Simulation time 47280313 ps
CPU time 0.99 seconds
Started Jul 01 04:48:20 PM PDT 24
Finished Jul 01 04:48:23 PM PDT 24
Peak memory 196272 kb
Host smart-b49ca290-a138-4c65-b814-5e133d47752c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256550227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.1256550227
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.3857492889
Short name T182
Test name
Test status
Simulation time 468901174 ps
CPU time 1.36 seconds
Started Jul 01 04:48:22 PM PDT 24
Finished Jul 01 04:48:25 PM PDT 24
Peak memory 196556 kb
Host smart-e2ee6f2b-08a4-4f5a-a228-74737c197d9e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857492889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.3857492889
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.1208182013
Short name T462
Test name
Test status
Simulation time 11845729412 ps
CPU time 210.9 seconds
Started Jul 01 04:48:20 PM PDT 24
Finished Jul 01 04:51:52 PM PDT 24
Peak memory 198756 kb
Host smart-7f18dfa2-3be7-42a5-b9bb-0f9df3d88599
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208182013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.1208182013
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1073583641
Short name T345
Test name
Test status
Simulation time 90695740 ps
CPU time 0.96 seconds
Started Jul 01 04:48:42 PM PDT 24
Finished Jul 01 04:48:46 PM PDT 24
Peak memory 196592 kb
Host smart-d695ecd3-2141-4cb6-bb3e-d93cf3a6ba75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073583641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1073583641
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.186559869
Short name T678
Test name
Test status
Simulation time 689263212 ps
CPU time 17.71 seconds
Started Jul 01 04:48:47 PM PDT 24
Finished Jul 01 04:49:08 PM PDT 24
Peak memory 197544 kb
Host smart-6b992d2f-d48d-43c0-9e38-1d772abbf879
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186559869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stres
s.186559869
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.1761858478
Short name T24
Test name
Test status
Simulation time 42107974 ps
CPU time 0.94 seconds
Started Jul 01 04:48:41 PM PDT 24
Finished Jul 01 04:48:46 PM PDT 24
Peak memory 197912 kb
Host smart-5f835725-167f-4cdf-a708-1db430cbfa30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761858478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.1761858478
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.4181962876
Short name T352
Test name
Test status
Simulation time 47331505 ps
CPU time 1.93 seconds
Started Jul 01 04:48:44 PM PDT 24
Finished Jul 01 04:48:50 PM PDT 24
Peak memory 198768 kb
Host smart-6eb57ff2-ed17-45cd-ae89-a72cca4de2e6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181962876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.4181962876
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3990411664
Short name T298
Test name
Test status
Simulation time 1020243266 ps
CPU time 3.4 seconds
Started Jul 01 04:48:44 PM PDT 24
Finished Jul 01 04:48:51 PM PDT 24
Peak memory 197928 kb
Host smart-db178539-e0c7-42e6-a9cb-38142805bb2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990411664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.3990411664
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3317132248
Short name T518
Test name
Test status
Simulation time 119318705 ps
CPU time 1.22 seconds
Started Jul 01 04:48:44 PM PDT 24
Finished Jul 01 04:48:49 PM PDT 24
Peak memory 196596 kb
Host smart-217e3e8f-559d-481c-aed7-900b2e016576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317132248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3317132248
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.927681781
Short name T503
Test name
Test status
Simulation time 161192053 ps
CPU time 1.12 seconds
Started Jul 01 04:48:45 PM PDT 24
Finished Jul 01 04:48:50 PM PDT 24
Peak memory 197200 kb
Host smart-b1c55b62-f421-41be-a11b-215a13bfffbb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927681781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup
_pulldown.927681781
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1360808660
Short name T408
Test name
Test status
Simulation time 295032964 ps
CPU time 1.17 seconds
Started Jul 01 04:48:43 PM PDT 24
Finished Jul 01 04:48:48 PM PDT 24
Peak memory 198488 kb
Host smart-def88382-1916-4791-883c-7fe749514a21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360808660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1360808660
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1152489415
Short name T406
Test name
Test status
Simulation time 68442691 ps
CPU time 1.19 seconds
Started Jul 01 04:48:41 PM PDT 24
Finished Jul 01 04:48:46 PM PDT 24
Peak memory 196260 kb
Host smart-f4846e21-b14a-451b-b75f-d1bd45090dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152489415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1152489415
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.2480583596
Short name T375
Test name
Test status
Simulation time 100879058 ps
CPU time 0.89 seconds
Started Jul 01 04:48:43 PM PDT 24
Finished Jul 01 04:48:48 PM PDT 24
Peak memory 196880 kb
Host smart-5ab43741-4fd5-42e0-bb3b-8346b23c27d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480583596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.2480583596
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.756548921
Short name T457
Test name
Test status
Simulation time 52559123665 ps
CPU time 157.09 seconds
Started Jul 01 04:48:41 PM PDT 24
Finished Jul 01 04:51:22 PM PDT 24
Peak memory 198776 kb
Host smart-0b5c63e6-e1db-45ea-80ea-9bbbb54a751d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756548921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.756548921
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.3020452680
Short name T35
Test name
Test status
Simulation time 69998337902 ps
CPU time 316.66 seconds
Started Jul 01 04:48:42 PM PDT 24
Finished Jul 01 04:54:03 PM PDT 24
Peak memory 198884 kb
Host smart-c15086ff-990d-4f92-9869-a7cf8db0cfe2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3020452680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.3020452680
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.15097702
Short name T151
Test name
Test status
Simulation time 19900086 ps
CPU time 0.59 seconds
Started Jul 01 04:48:45 PM PDT 24
Finished Jul 01 04:48:49 PM PDT 24
Peak memory 193456 kb
Host smart-912e3072-d263-4085-ad3d-9b86b3729eba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15097702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.15097702
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.1928057863
Short name T663
Test name
Test status
Simulation time 32252610 ps
CPU time 0.84 seconds
Started Jul 01 04:48:45 PM PDT 24
Finished Jul 01 04:48:50 PM PDT 24
Peak memory 195920 kb
Host smart-ff781e34-32d7-43e1-b6e7-5ad6d684198a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928057863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.1928057863
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.3634333624
Short name T259
Test name
Test status
Simulation time 789020510 ps
CPU time 20.34 seconds
Started Jul 01 04:48:44 PM PDT 24
Finished Jul 01 04:49:08 PM PDT 24
Peak memory 196168 kb
Host smart-aee0e13a-86ae-4504-a8a6-55c243c4acef
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634333624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.3634333624
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.3278452881
Short name T434
Test name
Test status
Simulation time 77195464 ps
CPU time 0.98 seconds
Started Jul 01 04:48:47 PM PDT 24
Finished Jul 01 04:48:52 PM PDT 24
Peak memory 197612 kb
Host smart-71dd2203-418b-4259-b1fc-ecb8b0476cc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278452881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3278452881
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.426336926
Short name T481
Test name
Test status
Simulation time 54063576 ps
CPU time 0.68 seconds
Started Jul 01 04:48:42 PM PDT 24
Finished Jul 01 04:48:46 PM PDT 24
Peak memory 195708 kb
Host smart-94439596-df3d-4c1c-90de-4029e7b4b69b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426336926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.426336926
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3425727804
Short name T295
Test name
Test status
Simulation time 810543327 ps
CPU time 2.81 seconds
Started Jul 01 04:48:40 PM PDT 24
Finished Jul 01 04:48:46 PM PDT 24
Peak memory 197920 kb
Host smart-2a56922b-cb89-48eb-99dd-02836c428d8e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425727804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3425727804
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.2124326234
Short name T629
Test name
Test status
Simulation time 97283006 ps
CPU time 2.91 seconds
Started Jul 01 04:48:44 PM PDT 24
Finished Jul 01 04:48:51 PM PDT 24
Peak memory 197544 kb
Host smart-1a53964d-4065-4a3b-95cc-f3975001bd76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124326234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.2124326234
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2852488462
Short name T523
Test name
Test status
Simulation time 198451578 ps
CPU time 1.14 seconds
Started Jul 01 04:48:43 PM PDT 24
Finished Jul 01 04:48:48 PM PDT 24
Peak memory 196708 kb
Host smart-63202737-b0ee-4be5-8712-8a2355176822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852488462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2852488462
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2315200940
Short name T390
Test name
Test status
Simulation time 47882609 ps
CPU time 0.95 seconds
Started Jul 01 04:48:43 PM PDT 24
Finished Jul 01 04:48:48 PM PDT 24
Peak memory 196500 kb
Host smart-48d43501-250e-402a-844e-97e9df0c52e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315200940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2315200940
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.530093692
Short name T8
Test name
Test status
Simulation time 809663858 ps
CPU time 2.99 seconds
Started Jul 01 04:48:41 PM PDT 24
Finished Jul 01 04:48:48 PM PDT 24
Peak memory 198828 kb
Host smart-1ea317ab-2a3a-49f0-af90-e895fa76f92b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530093692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.530093692
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.2742559837
Short name T641
Test name
Test status
Simulation time 107270940 ps
CPU time 0.98 seconds
Started Jul 01 04:48:43 PM PDT 24
Finished Jul 01 04:48:48 PM PDT 24
Peak memory 196612 kb
Host smart-16e3a4f3-7b51-4993-b221-b222f1d842fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742559837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.2742559837
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3585609596
Short name T571
Test name
Test status
Simulation time 69583721 ps
CPU time 1.31 seconds
Started Jul 01 04:48:43 PM PDT 24
Finished Jul 01 04:48:49 PM PDT 24
Peak memory 196444 kb
Host smart-ff123f4f-35ca-4204-95e4-2106670d4c2b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585609596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3585609596
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.3435845869
Short name T704
Test name
Test status
Simulation time 43964643831 ps
CPU time 147.04 seconds
Started Jul 01 04:48:41 PM PDT 24
Finished Jul 01 04:51:12 PM PDT 24
Peak memory 198832 kb
Host smart-f2aeab3d-0eb1-4766-89fe-9a8dc0a4bff4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435845869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.3435845869
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.3686001331
Short name T440
Test name
Test status
Simulation time 99488053988 ps
CPU time 2456.9 seconds
Started Jul 01 04:48:43 PM PDT 24
Finished Jul 01 05:29:44 PM PDT 24
Peak memory 198960 kb
Host smart-9af7058d-7db9-4c9e-b129-badbd4b038e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3686001331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.3686001331
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3672758240
Short name T19
Test name
Test status
Simulation time 61055455 ps
CPU time 0.61 seconds
Started Jul 01 04:48:48 PM PDT 24
Finished Jul 01 04:48:53 PM PDT 24
Peak memory 194716 kb
Host smart-52a3520a-e90f-4311-a71d-87461b50a4a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672758240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3672758240
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2616993531
Short name T698
Test name
Test status
Simulation time 62425655 ps
CPU time 0.63 seconds
Started Jul 01 04:48:47 PM PDT 24
Finished Jul 01 04:48:51 PM PDT 24
Peak memory 194520 kb
Host smart-c62af0ef-5747-4e15-8c62-d15752be8487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616993531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2616993531
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.3134072581
Short name T612
Test name
Test status
Simulation time 421713472 ps
CPU time 10.53 seconds
Started Jul 01 04:48:53 PM PDT 24
Finished Jul 01 04:49:08 PM PDT 24
Peak memory 197028 kb
Host smart-a2b84c21-7d2e-415e-b101-76593101ff46
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134072581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.3134072581
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.3024186368
Short name T174
Test name
Test status
Simulation time 75666994 ps
CPU time 1.02 seconds
Started Jul 01 04:48:51 PM PDT 24
Finished Jul 01 04:48:56 PM PDT 24
Peak memory 198360 kb
Host smart-7dba0a34-9f03-482a-9340-cc55d0c9475f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024186368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.3024186368
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.1766786280
Short name T147
Test name
Test status
Simulation time 83042328 ps
CPU time 1.4 seconds
Started Jul 01 04:48:50 PM PDT 24
Finished Jul 01 04:48:56 PM PDT 24
Peak memory 197888 kb
Host smart-d6b935c5-30e8-4e31-87c9-ad1d51ac4ccf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766786280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.1766786280
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.355533218
Short name T534
Test name
Test status
Simulation time 330237422 ps
CPU time 3.05 seconds
Started Jul 01 04:48:56 PM PDT 24
Finished Jul 01 04:49:03 PM PDT 24
Peak memory 198800 kb
Host smart-b3962b61-4f24-4c3a-9964-405b8cd4ecb9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355533218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.355533218
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2706028476
Short name T569
Test name
Test status
Simulation time 293985912 ps
CPU time 2.67 seconds
Started Jul 01 04:48:51 PM PDT 24
Finished Jul 01 04:48:58 PM PDT 24
Peak memory 198820 kb
Host smart-78c0d37c-e624-4f62-a95f-563a73af208e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706028476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2706028476
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.739989629
Short name T431
Test name
Test status
Simulation time 247146108 ps
CPU time 1.19 seconds
Started Jul 01 04:48:45 PM PDT 24
Finished Jul 01 04:48:50 PM PDT 24
Peak memory 196700 kb
Host smart-5c10e05d-8b43-4558-ad87-1544d94b1c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739989629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.739989629
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.2109170567
Short name T299
Test name
Test status
Simulation time 38200134 ps
CPU time 0.9 seconds
Started Jul 01 04:48:43 PM PDT 24
Finished Jul 01 04:48:48 PM PDT 24
Peak memory 197344 kb
Host smart-cd964480-4dfe-44cc-91ac-14ec2a60860a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109170567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.2109170567
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.825401462
Short name T284
Test name
Test status
Simulation time 42617659 ps
CPU time 2.03 seconds
Started Jul 01 04:48:51 PM PDT 24
Finished Jul 01 04:48:57 PM PDT 24
Peak memory 198588 kb
Host smart-4f3fb6a2-15ad-45bb-ab75-969f246363ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825401462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ran
dom_long_reg_writes_reg_reads.825401462
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1108862627
Short name T55
Test name
Test status
Simulation time 340032167 ps
CPU time 1.35 seconds
Started Jul 01 04:48:41 PM PDT 24
Finished Jul 01 04:48:46 PM PDT 24
Peak memory 196248 kb
Host smart-aac8556d-64a7-48e7-b09c-82a4bd4e632f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108862627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1108862627
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2809349085
Short name T331
Test name
Test status
Simulation time 50860898 ps
CPU time 1.41 seconds
Started Jul 01 04:48:42 PM PDT 24
Finished Jul 01 04:48:48 PM PDT 24
Peak memory 197548 kb
Host smart-0d00404b-0320-4e08-9fc6-f36bc8544148
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809349085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2809349085
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.750634151
Short name T221
Test name
Test status
Simulation time 23100655646 ps
CPU time 79.5 seconds
Started Jul 01 04:48:50 PM PDT 24
Finished Jul 01 04:50:14 PM PDT 24
Peak memory 198772 kb
Host smart-1390753a-1446-4ac6-b8d4-2d7408afcee4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750634151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.g
pio_stress_all.750634151
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.2524499674
Short name T391
Test name
Test status
Simulation time 151932583584 ps
CPU time 2155.36 seconds
Started Jul 01 04:48:53 PM PDT 24
Finished Jul 01 05:24:52 PM PDT 24
Peak memory 198388 kb
Host smart-20c85685-f8a2-47b3-a59b-aa21bcf0a3fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2524499674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.2524499674
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.442441863
Short name T264
Test name
Test status
Simulation time 15176889 ps
CPU time 0.62 seconds
Started Jul 01 04:48:50 PM PDT 24
Finished Jul 01 04:48:54 PM PDT 24
Peak memory 194648 kb
Host smart-16ab33ea-bcc2-47af-8a5b-9b27f9b7cfed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442441863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.442441863
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3837164017
Short name T71
Test name
Test status
Simulation time 21693253 ps
CPU time 0.74 seconds
Started Jul 01 04:48:52 PM PDT 24
Finished Jul 01 04:48:57 PM PDT 24
Peak memory 195816 kb
Host smart-1657a998-edcb-479f-ad63-6ffde6b4fd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837164017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3837164017
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3911045740
Short name T517
Test name
Test status
Simulation time 133433972 ps
CPU time 7.18 seconds
Started Jul 01 04:48:49 PM PDT 24
Finished Jul 01 04:49:00 PM PDT 24
Peak memory 198656 kb
Host smart-47fc2ee6-47fb-4415-9dd2-a12e11d9e1d7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911045740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3911045740
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.223621572
Short name T10
Test name
Test status
Simulation time 593198689 ps
CPU time 1.03 seconds
Started Jul 01 04:48:51 PM PDT 24
Finished Jul 01 04:48:56 PM PDT 24
Peak memory 197048 kb
Host smart-43285222-a4d9-45a9-9d39-6d968f7d733f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223621572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.223621572
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3918312663
Short name T522
Test name
Test status
Simulation time 421161692 ps
CPU time 1.22 seconds
Started Jul 01 04:48:49 PM PDT 24
Finished Jul 01 04:48:55 PM PDT 24
Peak memory 197512 kb
Host smart-ed7c6144-abe6-4684-8f5a-9fbd7af35d78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918312663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3918312663
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1237530086
Short name T438
Test name
Test status
Simulation time 42167430 ps
CPU time 1.72 seconds
Started Jul 01 04:48:49 PM PDT 24
Finished Jul 01 04:48:55 PM PDT 24
Peak memory 197368 kb
Host smart-b1eb2cda-703f-44ef-b054-0051c1b3a55c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237530086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1237530086
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.1512785011
Short name T690
Test name
Test status
Simulation time 76984876 ps
CPU time 2.43 seconds
Started Jul 01 04:48:50 PM PDT 24
Finished Jul 01 04:48:57 PM PDT 24
Peak memory 197168 kb
Host smart-3ac94c87-ce24-4295-a5fa-466d3f7e33df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512785011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.1512785011
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2221944456
Short name T662
Test name
Test status
Simulation time 20421384 ps
CPU time 0.78 seconds
Started Jul 01 04:48:51 PM PDT 24
Finished Jul 01 04:48:56 PM PDT 24
Peak memory 196732 kb
Host smart-758b43e2-c15e-41fe-a126-6aabb46a752a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221944456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2221944456
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.930944049
Short name T502
Test name
Test status
Simulation time 116249923 ps
CPU time 1.21 seconds
Started Jul 01 04:48:50 PM PDT 24
Finished Jul 01 04:48:56 PM PDT 24
Peak memory 197644 kb
Host smart-1a49a82f-d455-43f4-bc00-3b3d97809c6d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930944049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullup
_pulldown.930944049
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.3513177171
Short name T403
Test name
Test status
Simulation time 1572397989 ps
CPU time 5.21 seconds
Started Jul 01 04:48:53 PM PDT 24
Finished Jul 01 04:49:02 PM PDT 24
Peak memory 198048 kb
Host smart-96c8f74a-4d89-448f-a2f4-e9f5c6e150f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513177171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.3513177171
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.221762848
Short name T17
Test name
Test status
Simulation time 51626238 ps
CPU time 1.2 seconds
Started Jul 01 04:48:50 PM PDT 24
Finished Jul 01 04:48:56 PM PDT 24
Peak memory 198660 kb
Host smart-f1c0155f-84ab-4d73-ae30-436482919260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221762848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.221762848
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.709291209
Short name T573
Test name
Test status
Simulation time 179366815 ps
CPU time 0.94 seconds
Started Jul 01 04:48:51 PM PDT 24
Finished Jul 01 04:48:56 PM PDT 24
Peak memory 197220 kb
Host smart-27473838-d8e5-40be-ac75-8067938da434
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709291209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.709291209
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.797736993
Short name T665
Test name
Test status
Simulation time 7996373221 ps
CPU time 54.13 seconds
Started Jul 01 04:48:51 PM PDT 24
Finished Jul 01 04:49:49 PM PDT 24
Peak memory 198860 kb
Host smart-dba87afd-8d4d-4ff7-9c31-506c89740e0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797736993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.g
pio_stress_all.797736993
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.198984484
Short name T130
Test name
Test status
Simulation time 28236531 ps
CPU time 0.6 seconds
Started Jul 01 04:48:50 PM PDT 24
Finished Jul 01 04:48:55 PM PDT 24
Peak memory 194660 kb
Host smart-15ede363-40d1-4bc9-9db8-c7655bb5c455
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198984484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.198984484
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.941391648
Short name T131
Test name
Test status
Simulation time 36044085 ps
CPU time 0.76 seconds
Started Jul 01 04:48:50 PM PDT 24
Finished Jul 01 04:48:55 PM PDT 24
Peak memory 195952 kb
Host smart-e148d4e5-ebdb-40c0-b930-7a709ec3e4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941391648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.941391648
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.3166686405
Short name T496
Test name
Test status
Simulation time 182910427 ps
CPU time 9.28 seconds
Started Jul 01 04:48:51 PM PDT 24
Finished Jul 01 04:49:04 PM PDT 24
Peak memory 197516 kb
Host smart-f383cd76-05b4-450c-9303-717d4a6c4acd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166686405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.3166686405
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.2278384287
Short name T5
Test name
Test status
Simulation time 333168267 ps
CPU time 0.97 seconds
Started Jul 01 04:48:51 PM PDT 24
Finished Jul 01 04:48:57 PM PDT 24
Peak memory 197640 kb
Host smart-208a4f1b-f6a2-41c5-947f-61901e37ede7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278384287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.2278384287
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.287459455
Short name T684
Test name
Test status
Simulation time 372129924 ps
CPU time 1.48 seconds
Started Jul 01 04:48:51 PM PDT 24
Finished Jul 01 04:48:57 PM PDT 24
Peak memory 197424 kb
Host smart-ab1d30d9-8bd3-47fe-9cd6-b3b0d6620eb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287459455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.287459455
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.2727853339
Short name T593
Test name
Test status
Simulation time 237857936 ps
CPU time 2.52 seconds
Started Jul 01 04:48:50 PM PDT 24
Finished Jul 01 04:48:57 PM PDT 24
Peak memory 198656 kb
Host smart-64b4b10d-9847-45aa-a005-dec1e4ef9481
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727853339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.2727853339
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.3691329308
Short name T154
Test name
Test status
Simulation time 120416714 ps
CPU time 1.16 seconds
Started Jul 01 04:48:47 PM PDT 24
Finished Jul 01 04:48:51 PM PDT 24
Peak memory 197484 kb
Host smart-8c8fec8f-0c2f-4858-91e6-6fe80769ce95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691329308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.3691329308
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3399305897
Short name T717
Test name
Test status
Simulation time 450162336 ps
CPU time 1.33 seconds
Started Jul 01 04:48:48 PM PDT 24
Finished Jul 01 04:48:53 PM PDT 24
Peak memory 198952 kb
Host smart-729f31ff-9c60-4226-9a38-9f630adfb17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399305897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3399305897
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1360772943
Short name T669
Test name
Test status
Simulation time 58260373 ps
CPU time 0.79 seconds
Started Jul 01 04:48:49 PM PDT 24
Finished Jul 01 04:48:55 PM PDT 24
Peak memory 196136 kb
Host smart-e65e459a-05db-45f2-ac2b-e5a06e7be923
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360772943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.1360772943
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2201883395
Short name T329
Test name
Test status
Simulation time 1623344504 ps
CPU time 5.62 seconds
Started Jul 01 04:48:53 PM PDT 24
Finished Jul 01 04:49:03 PM PDT 24
Peak memory 198676 kb
Host smart-ef7ae340-8082-4d0e-8f6c-e674e6175bbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201883395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2201883395
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1269469424
Short name T327
Test name
Test status
Simulation time 40828660 ps
CPU time 0.95 seconds
Started Jul 01 04:48:48 PM PDT 24
Finished Jul 01 04:48:53 PM PDT 24
Peak memory 196816 kb
Host smart-9e7d5a52-3f1d-4747-b0cb-1a7de4256f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269469424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1269469424
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.2908386643
Short name T546
Test name
Test status
Simulation time 24538785 ps
CPU time 0.83 seconds
Started Jul 01 04:48:50 PM PDT 24
Finished Jul 01 04:48:55 PM PDT 24
Peak memory 197052 kb
Host smart-832338e9-93c4-4261-88d1-cb4777c16123
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908386643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.2908386643
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2572663843
Short name T167
Test name
Test status
Simulation time 7485387535 ps
CPU time 117.16 seconds
Started Jul 01 04:48:51 PM PDT 24
Finished Jul 01 04:50:53 PM PDT 24
Peak memory 198768 kb
Host smart-afd1770a-876c-4e30-bf6e-27ff38df7824
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572663843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2572663843
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.2300101099
Short name T84
Test name
Test status
Simulation time 487667736184 ps
CPU time 1908.33 seconds
Started Jul 01 04:48:50 PM PDT 24
Finished Jul 01 05:20:42 PM PDT 24
Peak memory 198928 kb
Host smart-d5afdf1c-58b5-4759-b932-33a9505ba9e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2300101099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.2300101099
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2783222884
Short name T266
Test name
Test status
Simulation time 17238778 ps
CPU time 0.57 seconds
Started Jul 01 04:48:57 PM PDT 24
Finished Jul 01 04:49:01 PM PDT 24
Peak memory 194152 kb
Host smart-c5937d63-bc94-4447-8fd5-3faaa08f1b6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783222884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2783222884
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2845458787
Short name T605
Test name
Test status
Simulation time 24833797 ps
CPU time 0.77 seconds
Started Jul 01 04:48:58 PM PDT 24
Finished Jul 01 04:49:04 PM PDT 24
Peak memory 194852 kb
Host smart-0fda8a13-29fd-42e9-b716-b8d2379cf088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845458787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2845458787
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.1874592977
Short name T145
Test name
Test status
Simulation time 400903312 ps
CPU time 19.64 seconds
Started Jul 01 04:48:56 PM PDT 24
Finished Jul 01 04:49:20 PM PDT 24
Peak memory 196212 kb
Host smart-c06746fd-e9fb-4930-879c-5549345f4065
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874592977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.1874592977
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.521320370
Short name T187
Test name
Test status
Simulation time 423339936 ps
CPU time 0.77 seconds
Started Jul 01 04:48:58 PM PDT 24
Finished Jul 01 04:49:03 PM PDT 24
Peak memory 197248 kb
Host smart-daa86e44-9e55-4638-928f-16d721b20ae9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521320370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.521320370
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.4104201664
Short name T135
Test name
Test status
Simulation time 80981151 ps
CPU time 1.28 seconds
Started Jul 01 04:48:57 PM PDT 24
Finished Jul 01 04:49:03 PM PDT 24
Peak memory 198728 kb
Host smart-07c83dae-091b-4d67-bda7-c07b22d8e296
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104201664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.4104201664
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2987570144
Short name T318
Test name
Test status
Simulation time 208021439 ps
CPU time 2.45 seconds
Started Jul 01 04:48:57 PM PDT 24
Finished Jul 01 04:49:03 PM PDT 24
Peak memory 198496 kb
Host smart-aab07872-b8d5-4c81-86d9-23967304545c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987570144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2987570144
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1171795939
Short name T483
Test name
Test status
Simulation time 112859397 ps
CPU time 2.66 seconds
Started Jul 01 04:48:55 PM PDT 24
Finished Jul 01 04:49:02 PM PDT 24
Peak memory 197868 kb
Host smart-6ed6777e-395e-4902-9efe-3d7a337855e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171795939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1171795939
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.197323337
Short name T719
Test name
Test status
Simulation time 18510135 ps
CPU time 0.76 seconds
Started Jul 01 04:48:57 PM PDT 24
Finished Jul 01 04:49:02 PM PDT 24
Peak memory 196108 kb
Host smart-23654b67-8d92-47a1-bb55-3ceb7e2de855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197323337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.197323337
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.283173648
Short name T377
Test name
Test status
Simulation time 476889693 ps
CPU time 1.13 seconds
Started Jul 01 04:49:05 PM PDT 24
Finished Jul 01 04:49:12 PM PDT 24
Peak memory 196788 kb
Host smart-12161db9-9747-46f5-af86-86e9b042ec10
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283173648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullup
_pulldown.283173648
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3453293205
Short name T548
Test name
Test status
Simulation time 774062707 ps
CPU time 6.08 seconds
Started Jul 01 04:48:58 PM PDT 24
Finished Jul 01 04:49:09 PM PDT 24
Peak memory 198648 kb
Host smart-e7495be7-3a6d-49a6-be9d-5ea500580e96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453293205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3453293205
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.2904423073
Short name T136
Test name
Test status
Simulation time 400394542 ps
CPU time 1.27 seconds
Started Jul 01 04:48:55 PM PDT 24
Finished Jul 01 04:49:00 PM PDT 24
Peak memory 197536 kb
Host smart-86af1386-dcbc-42fc-9c81-668bcb350f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904423073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.2904423073
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.149659996
Short name T117
Test name
Test status
Simulation time 37897499 ps
CPU time 0.96 seconds
Started Jul 01 04:48:57 PM PDT 24
Finished Jul 01 04:49:03 PM PDT 24
Peak memory 197780 kb
Host smart-34c4ee10-8d38-4eae-8e4e-e8802c23ffab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149659996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.149659996
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1706804761
Short name T367
Test name
Test status
Simulation time 45676831743 ps
CPU time 61.08 seconds
Started Jul 01 04:48:58 PM PDT 24
Finished Jul 01 04:50:04 PM PDT 24
Peak memory 198764 kb
Host smart-c0860775-482d-495b-85b5-b3adaa023077
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706804761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1706804761
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1239353966
Short name T702
Test name
Test status
Simulation time 12931765 ps
CPU time 0.58 seconds
Started Jul 01 04:49:03 PM PDT 24
Finished Jul 01 04:49:07 PM PDT 24
Peak memory 195304 kb
Host smart-106fae50-f8fb-42bd-8cdd-55220180408c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239353966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1239353966
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.4166746885
Short name T158
Test name
Test status
Simulation time 69730322 ps
CPU time 0.73 seconds
Started Jul 01 04:48:56 PM PDT 24
Finished Jul 01 04:49:01 PM PDT 24
Peak memory 195616 kb
Host smart-477b814c-4d0e-4c1b-affa-1722ffbe9ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166746885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.4166746885
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.4099379269
Short name T599
Test name
Test status
Simulation time 3119207316 ps
CPU time 25.33 seconds
Started Jul 01 04:48:57 PM PDT 24
Finished Jul 01 04:49:27 PM PDT 24
Peak memory 197848 kb
Host smart-c6fcf663-ca6c-41fd-89f5-dc417aa0a137
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099379269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.4099379269
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.980461805
Short name T348
Test name
Test status
Simulation time 118281008 ps
CPU time 0.86 seconds
Started Jul 01 04:48:58 PM PDT 24
Finished Jul 01 04:49:03 PM PDT 24
Peak memory 196820 kb
Host smart-2c5bc18c-6281-42c6-87c1-2f55a4c4faf2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980461805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.980461805
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.2641933271
Short name T714
Test name
Test status
Simulation time 760891559 ps
CPU time 0.91 seconds
Started Jul 01 04:48:57 PM PDT 24
Finished Jul 01 04:49:02 PM PDT 24
Peak memory 196176 kb
Host smart-5a5205c0-9899-49a2-b713-cd907bdaf9be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641933271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.2641933271
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2871065646
Short name T686
Test name
Test status
Simulation time 64772925 ps
CPU time 3.26 seconds
Started Jul 01 04:48:57 PM PDT 24
Finished Jul 01 04:49:05 PM PDT 24
Peak memory 198752 kb
Host smart-a738b650-9cde-4d3f-ab06-b229ac5f14f6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871065646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2871065646
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2695585499
Short name T169
Test name
Test status
Simulation time 63062794 ps
CPU time 1.97 seconds
Started Jul 01 04:48:57 PM PDT 24
Finished Jul 01 04:49:04 PM PDT 24
Peak memory 197432 kb
Host smart-7097bc77-d939-459f-827e-61c6da7dab53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695585499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2695585499
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.486209132
Short name T228
Test name
Test status
Simulation time 59272850 ps
CPU time 0.8 seconds
Started Jul 01 04:48:57 PM PDT 24
Finished Jul 01 04:49:02 PM PDT 24
Peak memory 196032 kb
Host smart-7be0f322-95af-470a-b5f4-d7dfca97057b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486209132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.486209132
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.4236288338
Short name T371
Test name
Test status
Simulation time 18104833 ps
CPU time 0.84 seconds
Started Jul 01 04:48:57 PM PDT 24
Finished Jul 01 04:49:02 PM PDT 24
Peak memory 196116 kb
Host smart-1d13245a-f83f-4180-a60b-553655b4c54d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236288338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.4236288338
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.638425518
Short name T361
Test name
Test status
Simulation time 270512106 ps
CPU time 3.78 seconds
Started Jul 01 04:48:57 PM PDT 24
Finished Jul 01 04:49:06 PM PDT 24
Peak memory 198580 kb
Host smart-e5be5467-361a-4d98-9982-c80e26022c9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638425518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ran
dom_long_reg_writes_reg_reads.638425518
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2368897529
Short name T550
Test name
Test status
Simulation time 61195608 ps
CPU time 1.33 seconds
Started Jul 01 04:48:57 PM PDT 24
Finished Jul 01 04:49:03 PM PDT 24
Peak memory 196448 kb
Host smart-ad056ae5-cbb2-45f1-8861-a3a6b3d1ec49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368897529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2368897529
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.2258563422
Short name T491
Test name
Test status
Simulation time 197744998 ps
CPU time 1.56 seconds
Started Jul 01 04:48:55 PM PDT 24
Finished Jul 01 04:49:00 PM PDT 24
Peak memory 197568 kb
Host smart-779ab565-3bcd-49f2-a7e8-a9510e858c01
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258563422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.2258563422
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.4158548896
Short name T23
Test name
Test status
Simulation time 5971455225 ps
CPU time 146.34 seconds
Started Jul 01 04:48:57 PM PDT 24
Finished Jul 01 04:51:28 PM PDT 24
Peak memory 198764 kb
Host smart-9a0b09e2-acca-411d-9baa-98a226835117
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158548896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.4158548896
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.2269999108
Short name T606
Test name
Test status
Simulation time 16043574 ps
CPU time 0.58 seconds
Started Jul 01 04:49:04 PM PDT 24
Finished Jul 01 04:49:08 PM PDT 24
Peak memory 194664 kb
Host smart-cf0a02c5-9f00-4925-b4f0-155d0e7aea72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269999108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.2269999108
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1553403132
Short name T336
Test name
Test status
Simulation time 22788078 ps
CPU time 0.66 seconds
Started Jul 01 04:48:58 PM PDT 24
Finished Jul 01 04:49:04 PM PDT 24
Peak memory 195292 kb
Host smart-37fec4c8-8cb6-4b34-8ba6-71f27993f3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553403132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1553403132
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2831263418
Short name T317
Test name
Test status
Simulation time 529624140 ps
CPU time 8.33 seconds
Started Jul 01 04:48:58 PM PDT 24
Finished Jul 01 04:49:11 PM PDT 24
Peak memory 198620 kb
Host smart-f6f9f1b1-066a-4cf5-a9c3-1b230775a5ec
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831263418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2831263418
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.350222894
Short name T260
Test name
Test status
Simulation time 874487217 ps
CPU time 0.97 seconds
Started Jul 01 04:48:58 PM PDT 24
Finished Jul 01 04:49:03 PM PDT 24
Peak memory 197408 kb
Host smart-f099a624-0bf0-4a66-b157-6c85bb5ffba0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350222894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.350222894
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3026394658
Short name T680
Test name
Test status
Simulation time 388163157 ps
CPU time 0.92 seconds
Started Jul 01 04:49:00 PM PDT 24
Finished Jul 01 04:49:05 PM PDT 24
Peak memory 196724 kb
Host smart-18d7fc7d-bf38-46da-8ca6-c5365ab84662
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026394658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3026394658
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.768238852
Short name T81
Test name
Test status
Simulation time 621867501 ps
CPU time 3.35 seconds
Started Jul 01 04:48:58 PM PDT 24
Finished Jul 01 04:49:06 PM PDT 24
Peak memory 198744 kb
Host smart-55a305a0-6635-4c6a-855f-c8205b0ae56f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768238852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.gpio_intr_with_filter_rand_intr_event.768238852
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.1957036514
Short name T696
Test name
Test status
Simulation time 73046530 ps
CPU time 1.53 seconds
Started Jul 01 04:48:59 PM PDT 24
Finished Jul 01 04:49:05 PM PDT 24
Peak memory 196480 kb
Host smart-6ab4370d-00ce-44ed-84b9-5c7483ba68fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957036514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.1957036514
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.1531538385
Short name T393
Test name
Test status
Simulation time 39155528 ps
CPU time 0.72 seconds
Started Jul 01 04:48:59 PM PDT 24
Finished Jul 01 04:49:05 PM PDT 24
Peak memory 196744 kb
Host smart-3807e33e-98b3-4619-a0c3-e6cc06329f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531538385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.1531538385
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3500866462
Short name T485
Test name
Test status
Simulation time 116457808 ps
CPU time 1.17 seconds
Started Jul 01 04:48:58 PM PDT 24
Finished Jul 01 04:49:04 PM PDT 24
Peak memory 197664 kb
Host smart-db55c803-0013-41a4-b7f7-9ae1e4ddc9e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500866462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3500866462
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3827086368
Short name T21
Test name
Test status
Simulation time 1026530245 ps
CPU time 5.6 seconds
Started Jul 01 04:48:59 PM PDT 24
Finished Jul 01 04:49:09 PM PDT 24
Peak memory 198632 kb
Host smart-9d5f1cd8-42b0-48bc-9a1d-daac5ac9461e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827086368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3827086368
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3020390673
Short name T206
Test name
Test status
Simulation time 240798672 ps
CPU time 1.47 seconds
Started Jul 01 04:48:57 PM PDT 24
Finished Jul 01 04:49:03 PM PDT 24
Peak memory 198844 kb
Host smart-58983eea-854e-44dc-85d4-c39e1fabdaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020390673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3020390673
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2023815041
Short name T162
Test name
Test status
Simulation time 83780802 ps
CPU time 0.87 seconds
Started Jul 01 04:48:57 PM PDT 24
Finished Jul 01 04:49:02 PM PDT 24
Peak memory 195976 kb
Host smart-78ca6c1d-17be-46e8-9853-7e12e2e6f483
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023815041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2023815041
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1405258871
Short name T7
Test name
Test status
Simulation time 8537712876 ps
CPU time 52.19 seconds
Started Jul 01 04:48:57 PM PDT 24
Finished Jul 01 04:49:53 PM PDT 24
Peak memory 198828 kb
Host smart-fdb084a8-2ff5-4b10-add0-68b311772cf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405258871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1405258871
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.2508733397
Short name T625
Test name
Test status
Simulation time 129514098364 ps
CPU time 681.77 seconds
Started Jul 01 04:48:57 PM PDT 24
Finished Jul 01 05:00:24 PM PDT 24
Peak memory 198912 kb
Host smart-8e1e3f6a-9b68-4398-a49f-404d63ea2575
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2508733397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.2508733397
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.2825060988
Short name T401
Test name
Test status
Simulation time 90632135 ps
CPU time 0.58 seconds
Started Jul 01 04:49:04 PM PDT 24
Finished Jul 01 04:49:09 PM PDT 24
Peak memory 194880 kb
Host smart-e692cfbd-e3af-401b-8fcc-fb3f468e2a90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825060988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.2825060988
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.1674125751
Short name T366
Test name
Test status
Simulation time 14715351 ps
CPU time 0.67 seconds
Started Jul 01 04:49:05 PM PDT 24
Finished Jul 01 04:49:11 PM PDT 24
Peak memory 195028 kb
Host smart-700dfe54-950c-43c4-8a3a-5760353c0cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674125751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.1674125751
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.449363434
Short name T148
Test name
Test status
Simulation time 213595319 ps
CPU time 5.64 seconds
Started Jul 01 04:49:07 PM PDT 24
Finished Jul 01 04:49:19 PM PDT 24
Peak memory 196912 kb
Host smart-944fe3d8-faaf-4c0a-b28d-ae835138c97a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449363434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres
s.449363434
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.1932460467
Short name T405
Test name
Test status
Simulation time 132355655 ps
CPU time 1.03 seconds
Started Jul 01 04:49:08 PM PDT 24
Finished Jul 01 04:49:15 PM PDT 24
Peak memory 196740 kb
Host smart-e5e42807-2a9f-404e-8ad4-10174ee38c37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932460467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1932460467
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.547633771
Short name T584
Test name
Test status
Simulation time 483673859 ps
CPU time 1.33 seconds
Started Jul 01 04:49:06 PM PDT 24
Finished Jul 01 04:49:13 PM PDT 24
Peak memory 197760 kb
Host smart-b4339c59-6be1-4c75-bf07-828fa5e41979
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547633771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.547633771
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.550543670
Short name T268
Test name
Test status
Simulation time 307832972 ps
CPU time 2.96 seconds
Started Jul 01 04:49:04 PM PDT 24
Finished Jul 01 04:49:12 PM PDT 24
Peak memory 197108 kb
Host smart-598182e1-8196-4939-9333-2f6f01e18b95
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550543670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.gpio_intr_with_filter_rand_intr_event.550543670
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.1781390177
Short name T369
Test name
Test status
Simulation time 240020162 ps
CPU time 3.27 seconds
Started Jul 01 04:49:05 PM PDT 24
Finished Jul 01 04:49:14 PM PDT 24
Peak memory 198708 kb
Host smart-860f34d1-9f83-4348-8005-78ae748d62d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781390177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.1781390177
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.4132465529
Short name T563
Test name
Test status
Simulation time 40783687 ps
CPU time 0.95 seconds
Started Jul 01 04:49:08 PM PDT 24
Finished Jul 01 04:49:16 PM PDT 24
Peak memory 198096 kb
Host smart-e6319676-3b39-49ab-9d60-66b71075dbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132465529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.4132465529
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1663004858
Short name T217
Test name
Test status
Simulation time 48617640 ps
CPU time 1.19 seconds
Started Jul 01 04:49:04 PM PDT 24
Finished Jul 01 04:49:09 PM PDT 24
Peak memory 196552 kb
Host smart-eef044ff-ad16-4f1c-98f5-f526496e8edd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663004858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1663004858
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1557910948
Short name T288
Test name
Test status
Simulation time 517976642 ps
CPU time 6.67 seconds
Started Jul 01 04:49:06 PM PDT 24
Finished Jul 01 04:49:18 PM PDT 24
Peak memory 198640 kb
Host smart-3088b002-ea65-4f3e-ad04-870ca353cc18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557910948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1557910948
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.4116707408
Short name T239
Test name
Test status
Simulation time 148977270 ps
CPU time 1.08 seconds
Started Jul 01 04:49:07 PM PDT 24
Finished Jul 01 04:49:14 PM PDT 24
Peak memory 196556 kb
Host smart-1ce31265-ed5c-438b-9ea3-684aa41f5559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116707408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.4116707408
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3154570560
Short name T292
Test name
Test status
Simulation time 37990805 ps
CPU time 1.18 seconds
Started Jul 01 04:49:13 PM PDT 24
Finished Jul 01 04:49:21 PM PDT 24
Peak memory 196588 kb
Host smart-afa70812-a295-4ab6-a510-aa66c1505f84
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154570560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3154570560
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.4188214398
Short name T659
Test name
Test status
Simulation time 13950950406 ps
CPU time 138.35 seconds
Started Jul 01 04:49:05 PM PDT 24
Finished Jul 01 04:51:28 PM PDT 24
Peak memory 198884 kb
Host smart-c028c361-8cc6-43a8-8f63-22311dc80087
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188214398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.4188214398
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3994920538
Short name T447
Test name
Test status
Simulation time 33367210 ps
CPU time 0.59 seconds
Started Jul 01 04:49:04 PM PDT 24
Finished Jul 01 04:49:09 PM PDT 24
Peak memory 194664 kb
Host smart-99df09f8-372f-492a-92ea-03dff1ba69c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994920538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3994920538
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.4262558940
Short name T700
Test name
Test status
Simulation time 34892066 ps
CPU time 0.7 seconds
Started Jul 01 04:49:06 PM PDT 24
Finished Jul 01 04:49:12 PM PDT 24
Peak memory 194820 kb
Host smart-9cdb233f-3c37-4e1c-9715-43d6a29c7769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262558940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.4262558940
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.713330595
Short name T603
Test name
Test status
Simulation time 1605441149 ps
CPU time 16.14 seconds
Started Jul 01 04:49:05 PM PDT 24
Finished Jul 01 04:49:26 PM PDT 24
Peak memory 197492 kb
Host smart-ba73f736-0ed0-454d-9e38-0825539d5b88
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713330595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.713330595
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.3453723691
Short name T301
Test name
Test status
Simulation time 63259948 ps
CPU time 0.87 seconds
Started Jul 01 04:49:12 PM PDT 24
Finished Jul 01 04:49:19 PM PDT 24
Peak memory 197440 kb
Host smart-7d1e8580-4c18-4052-b14c-f0b5613e7f0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453723691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3453723691
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1818782987
Short name T566
Test name
Test status
Simulation time 58976835 ps
CPU time 1.02 seconds
Started Jul 01 04:49:07 PM PDT 24
Finished Jul 01 04:49:13 PM PDT 24
Peak memory 196788 kb
Host smart-c0073945-9f99-41c8-98b3-eb7b94d94fd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818782987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1818782987
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1620075996
Short name T181
Test name
Test status
Simulation time 92589391 ps
CPU time 3.67 seconds
Started Jul 01 04:49:16 PM PDT 24
Finished Jul 01 04:49:26 PM PDT 24
Peak memory 198776 kb
Host smart-74eabfb4-3918-4a3a-94d9-3b4550fc0865
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620075996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1620075996
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.150542927
Short name T617
Test name
Test status
Simulation time 269504031 ps
CPU time 2.08 seconds
Started Jul 01 04:49:04 PM PDT 24
Finished Jul 01 04:49:11 PM PDT 24
Peak memory 196444 kb
Host smart-60d373f1-9a2d-4295-9643-b59ce4b36a64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150542927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger.
150542927
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3375542462
Short name T519
Test name
Test status
Simulation time 226974534 ps
CPU time 1.4 seconds
Started Jul 01 04:49:08 PM PDT 24
Finished Jul 01 04:49:16 PM PDT 24
Peak memory 198764 kb
Host smart-e6590a68-c469-45c9-974f-2c9435211561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375542462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3375542462
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3436134234
Short name T418
Test name
Test status
Simulation time 155812584 ps
CPU time 1.01 seconds
Started Jul 01 04:49:03 PM PDT 24
Finished Jul 01 04:49:09 PM PDT 24
Peak memory 196648 kb
Host smart-6ccd1cd2-11da-4e34-a556-8c313f479bb9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436134234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3436134234
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.667679062
Short name T413
Test name
Test status
Simulation time 885254703 ps
CPU time 3.62 seconds
Started Jul 01 04:49:16 PM PDT 24
Finished Jul 01 04:49:26 PM PDT 24
Peak memory 198620 kb
Host smart-bf26ed1b-db68-46a2-98e7-e5c1877d8788
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667679062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ran
dom_long_reg_writes_reg_reads.667679062
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.3833567330
Short name T212
Test name
Test status
Simulation time 201501494 ps
CPU time 0.93 seconds
Started Jul 01 04:49:05 PM PDT 24
Finished Jul 01 04:49:11 PM PDT 24
Peak memory 196076 kb
Host smart-df08aade-de51-490b-b56d-3bc1ef42367b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833567330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.3833567330
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.323367125
Short name T279
Test name
Test status
Simulation time 140598272 ps
CPU time 1.32 seconds
Started Jul 01 04:49:04 PM PDT 24
Finished Jul 01 04:49:09 PM PDT 24
Peak memory 198724 kb
Host smart-41ab03db-093a-4b63-8d41-cd29919d032f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323367125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.323367125
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1014511031
Short name T661
Test name
Test status
Simulation time 45743285564 ps
CPU time 163.66 seconds
Started Jul 01 04:49:04 PM PDT 24
Finished Jul 01 04:51:53 PM PDT 24
Peak memory 198908 kb
Host smart-5a44c83c-2573-4546-841c-f85d4768f780
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014511031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1014511031
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.1704576429
Short name T489
Test name
Test status
Simulation time 48745159449 ps
CPU time 739.23 seconds
Started Jul 01 04:49:16 PM PDT 24
Finished Jul 01 05:01:42 PM PDT 24
Peak memory 198932 kb
Host smart-ec0a60af-4a1c-43cf-9da3-65b080da41f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1704576429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.1704576429
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.2103677685
Short name T72
Test name
Test status
Simulation time 35852088 ps
CPU time 0.58 seconds
Started Jul 01 04:48:21 PM PDT 24
Finished Jul 01 04:48:23 PM PDT 24
Peak memory 194648 kb
Host smart-93af71fa-32e2-476d-a2c0-9156f1a2c2ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103677685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2103677685
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3406761534
Short name T210
Test name
Test status
Simulation time 37377585 ps
CPU time 0.82 seconds
Started Jul 01 04:48:23 PM PDT 24
Finished Jul 01 04:48:27 PM PDT 24
Peak memory 195760 kb
Host smart-8a0fc056-b49f-4b50-aa93-65a59b6d2c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406761534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3406761534
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2460233895
Short name T436
Test name
Test status
Simulation time 522508418 ps
CPU time 27.43 seconds
Started Jul 01 04:48:27 PM PDT 24
Finished Jul 01 04:48:56 PM PDT 24
Peak memory 197840 kb
Host smart-2d46a087-1831-4fb6-9731-2a4219a1ea4a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460233895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2460233895
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1317361520
Short name T216
Test name
Test status
Simulation time 106311218 ps
CPU time 0.66 seconds
Started Jul 01 04:48:21 PM PDT 24
Finished Jul 01 04:48:23 PM PDT 24
Peak memory 195288 kb
Host smart-0bdbcaa5-3b8b-461b-9b19-6c928892041d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317361520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1317361520
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.19344836
Short name T697
Test name
Test status
Simulation time 77991773 ps
CPU time 1.38 seconds
Started Jul 01 04:48:23 PM PDT 24
Finished Jul 01 04:48:27 PM PDT 24
Peak memory 197496 kb
Host smart-c8bafb4a-9cfa-454e-8437-d25bf88dc15e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19344836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.19344836
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.501964247
Short name T137
Test name
Test status
Simulation time 79937629 ps
CPU time 2.97 seconds
Started Jul 01 04:48:24 PM PDT 24
Finished Jul 01 04:48:30 PM PDT 24
Peak memory 198716 kb
Host smart-33b58afc-8c45-45ef-b42c-0376ff4ff9b0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501964247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.gpio_intr_with_filter_rand_intr_event.501964247
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.1740369072
Short name T615
Test name
Test status
Simulation time 674432744 ps
CPU time 3.33 seconds
Started Jul 01 04:48:22 PM PDT 24
Finished Jul 01 04:48:28 PM PDT 24
Peak memory 197828 kb
Host smart-09eda95d-eda6-49ef-af63-d3dcd7bc7923
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740369072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
1740369072
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.352106166
Short name T252
Test name
Test status
Simulation time 224529975 ps
CPU time 1.17 seconds
Started Jul 01 04:48:24 PM PDT 24
Finished Jul 01 04:48:28 PM PDT 24
Peak memory 196768 kb
Host smart-1181c9a3-5c7c-424a-9743-7ec44b942ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352106166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.352106166
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.714839664
Short name T166
Test name
Test status
Simulation time 301570998 ps
CPU time 1.31 seconds
Started Jul 01 04:48:20 PM PDT 24
Finished Jul 01 04:48:23 PM PDT 24
Peak memory 197544 kb
Host smart-3fea28fe-3ee8-4e5d-b187-6ee85a306e2b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714839664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup_
pulldown.714839664
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.4140453187
Short name T4
Test name
Test status
Simulation time 869337110 ps
CPU time 5.37 seconds
Started Jul 01 04:48:22 PM PDT 24
Finished Jul 01 04:48:30 PM PDT 24
Peak memory 198640 kb
Host smart-87858725-7b23-461b-8d5f-a4354bf42d53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140453187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.4140453187
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1742258118
Short name T41
Test name
Test status
Simulation time 94099042 ps
CPU time 0.96 seconds
Started Jul 01 04:48:28 PM PDT 24
Finished Jul 01 04:48:32 PM PDT 24
Peak memory 215440 kb
Host smart-6b826519-2b0b-496b-b340-028acedbfeab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742258118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1742258118
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.1839163514
Short name T445
Test name
Test status
Simulation time 141611459 ps
CPU time 1.27 seconds
Started Jul 01 04:48:23 PM PDT 24
Finished Jul 01 04:48:27 PM PDT 24
Peak memory 197212 kb
Host smart-1290847d-3318-4ea0-ae12-1c2e4551e062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839163514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1839163514
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3919609537
Short name T249
Test name
Test status
Simulation time 255974414 ps
CPU time 0.95 seconds
Started Jul 01 04:48:22 PM PDT 24
Finished Jul 01 04:48:26 PM PDT 24
Peak memory 196332 kb
Host smart-ae9a7663-a60b-4298-8e4a-7c6e3d206fed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919609537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3919609537
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3387645191
Short name T533
Test name
Test status
Simulation time 28483945889 ps
CPU time 62.79 seconds
Started Jul 01 04:48:25 PM PDT 24
Finished Jul 01 04:49:30 PM PDT 24
Peak memory 198840 kb
Host smart-2981b268-a4be-4705-a510-4d00e72ed837
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387645191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3387645191
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2719098807
Short name T189
Test name
Test status
Simulation time 12367899 ps
CPU time 0.58 seconds
Started Jul 01 04:49:04 PM PDT 24
Finished Jul 01 04:49:08 PM PDT 24
Peak memory 194880 kb
Host smart-c2aacc8c-d407-4751-bf65-f6527027f236
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719098807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2719098807
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.1118778424
Short name T452
Test name
Test status
Simulation time 45107561 ps
CPU time 0.61 seconds
Started Jul 01 04:49:05 PM PDT 24
Finished Jul 01 04:49:11 PM PDT 24
Peak memory 194544 kb
Host smart-eef76fc2-9cb5-4303-aa92-9e64968de958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118778424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.1118778424
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.2054207273
Short name T323
Test name
Test status
Simulation time 373832656 ps
CPU time 19.76 seconds
Started Jul 01 04:49:10 PM PDT 24
Finished Jul 01 04:49:36 PM PDT 24
Peak memory 197612 kb
Host smart-b7f841b6-8c8a-45ce-b704-960b2ee77115
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054207273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.2054207273
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.1890993321
Short name T473
Test name
Test status
Simulation time 102183029 ps
CPU time 0.8 seconds
Started Jul 01 04:49:12 PM PDT 24
Finished Jul 01 04:49:19 PM PDT 24
Peak memory 196656 kb
Host smart-75efda53-f78a-4302-8d83-ecb04247fea2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890993321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.1890993321
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.983374516
Short name T305
Test name
Test status
Simulation time 173646789 ps
CPU time 1.07 seconds
Started Jul 01 04:49:04 PM PDT 24
Finished Jul 01 04:49:09 PM PDT 24
Peak memory 196664 kb
Host smart-02ab0807-9ba8-47cc-ad88-98763c011e86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983374516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.983374516
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.2291918080
Short name T581
Test name
Test status
Simulation time 229235148 ps
CPU time 2.51 seconds
Started Jul 01 04:49:08 PM PDT 24
Finished Jul 01 04:49:17 PM PDT 24
Peak memory 198772 kb
Host smart-4996f16c-2566-440c-aa3a-d7f34afca749
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291918080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.2291918080
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.1512815263
Short name T230
Test name
Test status
Simulation time 2036286153 ps
CPU time 2.13 seconds
Started Jul 01 04:49:08 PM PDT 24
Finished Jul 01 04:49:16 PM PDT 24
Peak memory 196888 kb
Host smart-6ac9625c-6c9d-421f-a449-3566dd5c19f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512815263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.1512815263
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.2750905915
Short name T620
Test name
Test status
Simulation time 173498117 ps
CPU time 1.21 seconds
Started Jul 01 04:49:05 PM PDT 24
Finished Jul 01 04:49:12 PM PDT 24
Peak memory 196716 kb
Host smart-c6fa76ac-5b5d-4955-8dc6-a580bd7449d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750905915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.2750905915
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2294683488
Short name T627
Test name
Test status
Simulation time 57251041 ps
CPU time 1.12 seconds
Started Jul 01 04:49:07 PM PDT 24
Finished Jul 01 04:49:15 PM PDT 24
Peak memory 196736 kb
Host smart-188c879d-0f51-4faa-b984-b4495f60608d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294683488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2294683488
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.4263368581
Short name T320
Test name
Test status
Simulation time 321203425 ps
CPU time 4.32 seconds
Started Jul 01 04:49:10 PM PDT 24
Finished Jul 01 04:49:20 PM PDT 24
Peak memory 198588 kb
Host smart-e6a73ef0-21ea-431e-8b46-c75811f6173a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263368581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.4263368581
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2129077277
Short name T201
Test name
Test status
Simulation time 99327272 ps
CPU time 1.44 seconds
Started Jul 01 04:49:03 PM PDT 24
Finished Jul 01 04:49:09 PM PDT 24
Peak memory 198672 kb
Host smart-90af904e-5e9d-4824-9f67-25df096c57e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129077277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2129077277
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.2102087200
Short name T705
Test name
Test status
Simulation time 58143856 ps
CPU time 0.86 seconds
Started Jul 01 04:49:05 PM PDT 24
Finished Jul 01 04:49:11 PM PDT 24
Peak memory 195804 kb
Host smart-dde68e2b-af90-4734-b078-f429bcc790de
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102087200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.2102087200
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1713124482
Short name T608
Test name
Test status
Simulation time 4077727501 ps
CPU time 25.07 seconds
Started Jul 01 04:49:05 PM PDT 24
Finished Jul 01 04:49:35 PM PDT 24
Peak memory 198768 kb
Host smart-bed754bb-d165-4653-a72f-8a91695f5f2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713124482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1713124482
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.4260217191
Short name T597
Test name
Test status
Simulation time 95258855845 ps
CPU time 2491.3 seconds
Started Jul 01 04:49:06 PM PDT 24
Finished Jul 01 05:30:43 PM PDT 24
Peak memory 198888 kb
Host smart-320acc70-a52f-418d-b143-e2bfb24ac13d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4260217191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.4260217191
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.951002469
Short name T296
Test name
Test status
Simulation time 11356219 ps
CPU time 0.62 seconds
Started Jul 01 04:49:03 PM PDT 24
Finished Jul 01 04:49:08 PM PDT 24
Peak memory 195360 kb
Host smart-5b85ae1f-7618-4d9c-9ce3-b8092aaa15fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951002469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.951002469
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2994140911
Short name T715
Test name
Test status
Simulation time 33858725 ps
CPU time 0.67 seconds
Started Jul 01 04:49:05 PM PDT 24
Finished Jul 01 04:49:11 PM PDT 24
Peak memory 194764 kb
Host smart-9d24a8a4-a8ba-437b-887a-0527a48fa9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994140911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2994140911
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.4106332091
Short name T500
Test name
Test status
Simulation time 485619942 ps
CPU time 16.12 seconds
Started Jul 01 04:49:07 PM PDT 24
Finished Jul 01 04:49:29 PM PDT 24
Peak memory 198724 kb
Host smart-772cf70c-d1d4-44f8-a0bd-db9ebb260d8e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106332091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.4106332091
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2353831493
Short name T614
Test name
Test status
Simulation time 181834263 ps
CPU time 0.81 seconds
Started Jul 01 04:49:16 PM PDT 24
Finished Jul 01 04:49:23 PM PDT 24
Peak memory 196876 kb
Host smart-ce304885-5ca4-4c04-a985-1ffb95f1e5f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353831493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2353831493
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2968714817
Short name T188
Test name
Test status
Simulation time 183121344 ps
CPU time 0.92 seconds
Started Jul 01 04:49:03 PM PDT 24
Finished Jul 01 04:49:09 PM PDT 24
Peak memory 197144 kb
Host smart-3e4378a7-3738-49bb-bda5-0d655b900de6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968714817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2968714817
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.3577214338
Short name T184
Test name
Test status
Simulation time 48512437 ps
CPU time 1.95 seconds
Started Jul 01 04:49:05 PM PDT 24
Finished Jul 01 04:49:12 PM PDT 24
Peak memory 198252 kb
Host smart-3aede44a-42a9-4593-a5f0-d7d99c8c67dc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577214338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.3577214338
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.4198882707
Short name T707
Test name
Test status
Simulation time 84217967 ps
CPU time 0.98 seconds
Started Jul 01 04:49:05 PM PDT 24
Finished Jul 01 04:49:11 PM PDT 24
Peak memory 196776 kb
Host smart-70e1ce54-c656-40cb-bc73-257616e09b31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198882707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.4198882707
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2314413950
Short name T416
Test name
Test status
Simulation time 46847996 ps
CPU time 1.16 seconds
Started Jul 01 04:49:05 PM PDT 24
Finished Jul 01 04:49:11 PM PDT 24
Peak memory 197216 kb
Host smart-7c29b386-1f8a-46cd-972f-550fa6a430b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314413950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2314413950
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1309663971
Short name T538
Test name
Test status
Simulation time 24727677 ps
CPU time 0.96 seconds
Started Jul 01 04:49:05 PM PDT 24
Finished Jul 01 04:49:11 PM PDT 24
Peak memory 196700 kb
Host smart-a49bfa7a-8742-4a83-829c-b8ef85fded04
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309663971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.1309663971
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.3240520174
Short name T20
Test name
Test status
Simulation time 1203373739 ps
CPU time 3.42 seconds
Started Jul 01 04:49:10 PM PDT 24
Finished Jul 01 04:49:19 PM PDT 24
Peak memory 198600 kb
Host smart-3093475a-f06c-4746-ad36-f2352630a93f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240520174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.3240520174
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.3892313152
Short name T219
Test name
Test status
Simulation time 75052998 ps
CPU time 0.98 seconds
Started Jul 01 04:49:04 PM PDT 24
Finished Jul 01 04:49:09 PM PDT 24
Peak memory 196236 kb
Host smart-8447899c-96b8-4b2f-914c-5f495041bce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892313152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.3892313152
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1220033394
Short name T478
Test name
Test status
Simulation time 71532713 ps
CPU time 1.14 seconds
Started Jul 01 04:49:06 PM PDT 24
Finished Jul 01 04:49:13 PM PDT 24
Peak memory 196416 kb
Host smart-9bba3346-0fbe-4f74-86f8-4d84e9295b8b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220033394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.1220033394
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1899907313
Short name T514
Test name
Test status
Simulation time 21315621001 ps
CPU time 115.48 seconds
Started Jul 01 04:49:04 PM PDT 24
Finished Jul 01 04:51:04 PM PDT 24
Peak memory 198780 kb
Host smart-603d2359-7ff6-4511-a80d-8221b04fb037
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899907313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1899907313
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.74652833
Short name T515
Test name
Test status
Simulation time 13167824 ps
CPU time 0.59 seconds
Started Jul 01 04:49:09 PM PDT 24
Finished Jul 01 04:49:16 PM PDT 24
Peak memory 194744 kb
Host smart-dba74f08-216d-454c-b018-6c07287cd125
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74652833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.74652833
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.4233174430
Short name T490
Test name
Test status
Simulation time 165090634 ps
CPU time 0.94 seconds
Started Jul 01 04:49:08 PM PDT 24
Finished Jul 01 04:49:14 PM PDT 24
Peak memory 197064 kb
Host smart-32ec8f2c-b11e-4960-8571-23c3bfa89be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233174430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.4233174430
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.2774467334
Short name T332
Test name
Test status
Simulation time 170972832 ps
CPU time 4.75 seconds
Started Jul 01 04:49:08 PM PDT 24
Finished Jul 01 04:49:18 PM PDT 24
Peak memory 197748 kb
Host smart-b1bc6bda-a4b5-4c08-a9af-bded0748de67
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774467334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.2774467334
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3524611151
Short name T6
Test name
Test status
Simulation time 103913315 ps
CPU time 1.05 seconds
Started Jul 01 04:49:08 PM PDT 24
Finished Jul 01 04:49:14 PM PDT 24
Peak memory 197080 kb
Host smart-1db86e97-9373-4c61-adc2-0869eb7ee3a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524611151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3524611151
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2679417689
Short name T693
Test name
Test status
Simulation time 256541868 ps
CPU time 0.85 seconds
Started Jul 01 04:49:16 PM PDT 24
Finished Jul 01 04:49:23 PM PDT 24
Peak memory 196076 kb
Host smart-e25e1c59-583e-4b68-a6b3-08d8bcbaff90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679417689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2679417689
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.703206813
Short name T354
Test name
Test status
Simulation time 204243711 ps
CPU time 1.69 seconds
Started Jul 01 04:49:05 PM PDT 24
Finished Jul 01 04:49:12 PM PDT 24
Peak memory 196636 kb
Host smart-4a9b3f4d-240b-42af-b650-75efb26c0105
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703206813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
703206813
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.466179973
Short name T190
Test name
Test status
Simulation time 58090881 ps
CPU time 1.3 seconds
Started Jul 01 04:49:08 PM PDT 24
Finished Jul 01 04:49:15 PM PDT 24
Peak memory 198704 kb
Host smart-4994f2ba-95bf-4f29-a533-486c5f2f8b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466179973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.466179973
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.213357301
Short name T242
Test name
Test status
Simulation time 51836459 ps
CPU time 0.69 seconds
Started Jul 01 04:49:07 PM PDT 24
Finished Jul 01 04:49:14 PM PDT 24
Peak memory 194936 kb
Host smart-e5493a45-c1d6-4341-91fd-39f36b97c376
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213357301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup
_pulldown.213357301
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1599065562
Short name T175
Test name
Test status
Simulation time 295671927 ps
CPU time 4.98 seconds
Started Jul 01 04:49:12 PM PDT 24
Finished Jul 01 04:49:24 PM PDT 24
Peak memory 198740 kb
Host smart-cb78d93e-55cb-49f6-967c-58c531c979c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599065562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1599065562
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.1065618335
Short name T120
Test name
Test status
Simulation time 55915687 ps
CPU time 1.19 seconds
Started Jul 01 04:49:13 PM PDT 24
Finished Jul 01 04:49:21 PM PDT 24
Peak memory 196640 kb
Host smart-f3c493cc-db70-4722-8983-2d6e5b9183f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065618335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1065618335
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.1143443094
Short name T628
Test name
Test status
Simulation time 218098075 ps
CPU time 1.16 seconds
Started Jul 01 04:49:07 PM PDT 24
Finished Jul 01 04:49:14 PM PDT 24
Peak memory 197140 kb
Host smart-c38686b6-200c-4317-a438-d1d19c5f3749
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143443094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.1143443094
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.210616457
Short name T274
Test name
Test status
Simulation time 7069386848 ps
CPU time 174.63 seconds
Started Jul 01 04:49:13 PM PDT 24
Finished Jul 01 04:52:14 PM PDT 24
Peak memory 198888 kb
Host smart-0c728d1f-35b8-4da4-8641-87916ae4493b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210616457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.210616457
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.1729151884
Short name T61
Test name
Test status
Simulation time 21691447016 ps
CPU time 388.46 seconds
Started Jul 01 04:49:10 PM PDT 24
Finished Jul 01 04:55:44 PM PDT 24
Peak memory 199024 kb
Host smart-98de8b62-3a71-44e2-ae2d-38c5cec2a977
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1729151884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.1729151884
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.3146559765
Short name T419
Test name
Test status
Simulation time 20659720 ps
CPU time 0.6 seconds
Started Jul 01 04:49:12 PM PDT 24
Finished Jul 01 04:49:19 PM PDT 24
Peak memory 194652 kb
Host smart-fe6e9996-38c5-46a4-8e57-e3022eac4e8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146559765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.3146559765
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3444679840
Short name T637
Test name
Test status
Simulation time 34983400 ps
CPU time 0.61 seconds
Started Jul 01 04:49:10 PM PDT 24
Finished Jul 01 04:49:17 PM PDT 24
Peak memory 194564 kb
Host smart-f9b1370d-7b3c-4222-8341-b4035ad1ddf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444679840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3444679840
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.4208428636
Short name T205
Test name
Test status
Simulation time 896187821 ps
CPU time 22.72 seconds
Started Jul 01 04:49:11 PM PDT 24
Finished Jul 01 04:49:40 PM PDT 24
Peak memory 196212 kb
Host smart-8902e7d1-1027-47a3-83dc-5b62431ae1db
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208428636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.4208428636
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3866546667
Short name T191
Test name
Test status
Simulation time 57303345 ps
CPU time 0.7 seconds
Started Jul 01 04:49:13 PM PDT 24
Finished Jul 01 04:49:21 PM PDT 24
Peak memory 196096 kb
Host smart-37281dea-4914-4e77-8c4d-d903d533893c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866546667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3866546667
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.1572007600
Short name T196
Test name
Test status
Simulation time 425415698 ps
CPU time 1.6 seconds
Started Jul 01 04:49:11 PM PDT 24
Finished Jul 01 04:49:19 PM PDT 24
Peak memory 197676 kb
Host smart-5c0d52f9-0299-46e6-915f-96176fcb2e3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572007600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.1572007600
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3749636513
Short name T474
Test name
Test status
Simulation time 1761855055 ps
CPU time 3.89 seconds
Started Jul 01 04:49:11 PM PDT 24
Finished Jul 01 04:49:22 PM PDT 24
Peak memory 198884 kb
Host smart-67cbd839-c975-4fff-acb4-b55f55a6f324
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749636513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3749636513
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.2305414129
Short name T509
Test name
Test status
Simulation time 121665034 ps
CPU time 3.58 seconds
Started Jul 01 04:49:09 PM PDT 24
Finished Jul 01 04:49:19 PM PDT 24
Peak memory 196596 kb
Host smart-94d4aba0-0ec1-48b7-ab02-200ea148513c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305414129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.2305414129
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.722510409
Short name T461
Test name
Test status
Simulation time 186843287 ps
CPU time 1.12 seconds
Started Jul 01 04:49:07 PM PDT 24
Finished Jul 01 04:49:13 PM PDT 24
Peak memory 197144 kb
Host smart-1574c6f7-6b90-4382-9e1d-c397199030bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722510409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.722510409
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.621381979
Short name T236
Test name
Test status
Simulation time 168892525 ps
CPU time 1.09 seconds
Started Jul 01 04:49:21 PM PDT 24
Finished Jul 01 04:49:27 PM PDT 24
Peak memory 197208 kb
Host smart-0541d4bb-c4ac-4252-832d-0a0a4baf5c62
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621381979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup
_pulldown.621381979
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.729104834
Short name T713
Test name
Test status
Simulation time 422427764 ps
CPU time 3.07 seconds
Started Jul 01 04:49:11 PM PDT 24
Finished Jul 01 04:49:21 PM PDT 24
Peak memory 198648 kb
Host smart-9d01f00b-1200-4f17-bc6b-7b112cc192fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729104834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ran
dom_long_reg_writes_reg_reads.729104834
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.1559733655
Short name T652
Test name
Test status
Simulation time 114137291 ps
CPU time 1.31 seconds
Started Jul 01 04:49:07 PM PDT 24
Finished Jul 01 04:49:14 PM PDT 24
Peak memory 196244 kb
Host smart-3bcff19d-7985-46ef-ba0b-9d860f8a4501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559733655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.1559733655
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.518739126
Short name T638
Test name
Test status
Simulation time 272375903 ps
CPU time 1.17 seconds
Started Jul 01 04:49:05 PM PDT 24
Finished Jul 01 04:49:11 PM PDT 24
Peak memory 196428 kb
Host smart-0782053a-1b26-47d6-9ba0-a052205f2e9e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518739126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.518739126
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2265415683
Short name T692
Test name
Test status
Simulation time 28410415197 ps
CPU time 86.92 seconds
Started Jul 01 04:49:16 PM PDT 24
Finished Jul 01 04:50:49 PM PDT 24
Peak memory 198816 kb
Host smart-02a7bcf7-f968-4ee5-b594-61fe0b3faf14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265415683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2265415683
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.1812406112
Short name T557
Test name
Test status
Simulation time 40216576 ps
CPU time 0.6 seconds
Started Jul 01 04:49:11 PM PDT 24
Finished Jul 01 04:49:18 PM PDT 24
Peak memory 194836 kb
Host smart-97cc15ec-0563-4da3-bfdb-766642986be9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812406112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1812406112
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.2651721400
Short name T656
Test name
Test status
Simulation time 22258575 ps
CPU time 0.81 seconds
Started Jul 01 04:49:14 PM PDT 24
Finished Jul 01 04:49:21 PM PDT 24
Peak memory 196672 kb
Host smart-7bd54893-cda3-4a5a-afc3-6ea55624ad68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651721400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.2651721400
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3237068357
Short name T248
Test name
Test status
Simulation time 118744022 ps
CPU time 5.92 seconds
Started Jul 01 04:49:13 PM PDT 24
Finished Jul 01 04:49:26 PM PDT 24
Peak memory 196208 kb
Host smart-8ae11654-32df-4365-8bae-df708be37ce7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237068357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3237068357
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.4156474552
Short name T442
Test name
Test status
Simulation time 232820971 ps
CPU time 0.91 seconds
Started Jul 01 04:49:10 PM PDT 24
Finished Jul 01 04:49:17 PM PDT 24
Peak memory 198360 kb
Host smart-e7d112e3-8e37-4cb9-8f1b-e279ad944377
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156474552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.4156474552
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3286571895
Short name T255
Test name
Test status
Simulation time 26027283 ps
CPU time 0.87 seconds
Started Jul 01 04:49:12 PM PDT 24
Finished Jul 01 04:49:19 PM PDT 24
Peak memory 197384 kb
Host smart-c40a9450-d3b7-4e62-994e-d77aa2a2f708
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286571895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3286571895
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2478467331
Short name T258
Test name
Test status
Simulation time 149403636 ps
CPU time 3.07 seconds
Started Jul 01 04:49:10 PM PDT 24
Finished Jul 01 04:49:19 PM PDT 24
Peak memory 198720 kb
Host smart-8bf40cea-c009-48c5-9bd3-d25ca3c42ca6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478467331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2478467331
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.858560836
Short name T270
Test name
Test status
Simulation time 113427057 ps
CPU time 1.12 seconds
Started Jul 01 04:49:12 PM PDT 24
Finished Jul 01 04:49:21 PM PDT 24
Peak memory 196384 kb
Host smart-7b032535-f02a-4c2b-b532-1d8f8ebeffe0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858560836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
858560836
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3041009189
Short name T159
Test name
Test status
Simulation time 192577175 ps
CPU time 1.13 seconds
Started Jul 01 04:49:11 PM PDT 24
Finished Jul 01 04:49:19 PM PDT 24
Peak memory 197740 kb
Host smart-e3800038-1ea8-4729-b434-64957a4e6f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041009189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3041009189
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.2141227760
Short name T211
Test name
Test status
Simulation time 145962307 ps
CPU time 1.35 seconds
Started Jul 01 04:49:12 PM PDT 24
Finished Jul 01 04:49:20 PM PDT 24
Peak memory 197672 kb
Host smart-d0cdcd16-51f8-449e-a158-d066fcf40821
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141227760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.2141227760
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.4095187980
Short name T454
Test name
Test status
Simulation time 537910893 ps
CPU time 3.55 seconds
Started Jul 01 04:49:11 PM PDT 24
Finished Jul 01 04:49:21 PM PDT 24
Peak memory 198476 kb
Host smart-1e50c81a-fd5d-4621-b933-cd73581fb1db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095187980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.4095187980
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.868028280
Short name T587
Test name
Test status
Simulation time 31707652 ps
CPU time 0.96 seconds
Started Jul 01 04:49:10 PM PDT 24
Finished Jul 01 04:49:18 PM PDT 24
Peak memory 197212 kb
Host smart-2f57e767-1808-4e16-bc7d-87383035d3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868028280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.868028280
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.235201775
Short name T621
Test name
Test status
Simulation time 307240160 ps
CPU time 1.2 seconds
Started Jul 01 04:49:11 PM PDT 24
Finished Jul 01 04:49:18 PM PDT 24
Peak memory 197192 kb
Host smart-95c81d2c-7407-45f4-a1d3-8d9b7b6910dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235201775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.235201775
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.866515717
Short name T640
Test name
Test status
Simulation time 4781247177 ps
CPU time 106.27 seconds
Started Jul 01 04:49:11 PM PDT 24
Finished Jul 01 04:51:04 PM PDT 24
Peak memory 198792 kb
Host smart-dc6ed94a-6c5a-4aff-82d6-24cb815743ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866515717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.g
pio_stress_all.866515717
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.2160601537
Short name T67
Test name
Test status
Simulation time 80125521883 ps
CPU time 1405.72 seconds
Started Jul 01 04:49:21 PM PDT 24
Finished Jul 01 05:12:52 PM PDT 24
Peak memory 198908 kb
Host smart-18c5d808-31c2-46e0-a10e-33e753125e53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2160601537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.2160601537
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2696479728
Short name T161
Test name
Test status
Simulation time 11733445 ps
CPU time 0.57 seconds
Started Jul 01 04:49:14 PM PDT 24
Finished Jul 01 04:49:21 PM PDT 24
Peak memory 194652 kb
Host smart-7b04d621-4cbf-4282-b945-1822def0b43c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696479728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2696479728
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2590168397
Short name T316
Test name
Test status
Simulation time 25828274 ps
CPU time 0.64 seconds
Started Jul 01 04:49:10 PM PDT 24
Finished Jul 01 04:49:17 PM PDT 24
Peak memory 194520 kb
Host smart-24a94b19-258e-472a-98a1-cec6742e37d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590168397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2590168397
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.401308912
Short name T644
Test name
Test status
Simulation time 2294673048 ps
CPU time 10.42 seconds
Started Jul 01 04:49:16 PM PDT 24
Finished Jul 01 04:49:33 PM PDT 24
Peak memory 197268 kb
Host smart-f24451f3-bb83-44aa-bcee-9af34d42aedb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401308912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.401308912
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.1817352809
Short name T59
Test name
Test status
Simulation time 337070398 ps
CPU time 1.02 seconds
Started Jul 01 04:49:18 PM PDT 24
Finished Jul 01 04:49:25 PM PDT 24
Peak memory 198404 kb
Host smart-1098e0a7-e9a8-4a64-91b9-c27fdd93ca9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817352809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1817352809
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2170074198
Short name T73
Test name
Test status
Simulation time 391875525 ps
CPU time 0.86 seconds
Started Jul 01 04:49:12 PM PDT 24
Finished Jul 01 04:49:19 PM PDT 24
Peak memory 196476 kb
Host smart-0113c090-c252-44bf-a80b-1d9832805488
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170074198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2170074198
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2006253912
Short name T477
Test name
Test status
Simulation time 148391322 ps
CPU time 1.84 seconds
Started Jul 01 04:49:12 PM PDT 24
Finished Jul 01 04:49:20 PM PDT 24
Peak memory 198716 kb
Host smart-9af94b83-bb3f-4979-83c8-891eed96c6f0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006253912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2006253912
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.2021919291
Short name T280
Test name
Test status
Simulation time 35439439 ps
CPU time 0.96 seconds
Started Jul 01 04:49:21 PM PDT 24
Finished Jul 01 04:49:27 PM PDT 24
Peak memory 195128 kb
Host smart-e9152a44-ba77-43cf-bc46-17847650527f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021919291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.2021919291
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.854142081
Short name T80
Test name
Test status
Simulation time 61483380 ps
CPU time 0.73 seconds
Started Jul 01 04:49:10 PM PDT 24
Finished Jul 01 04:49:17 PM PDT 24
Peak memory 195020 kb
Host smart-a4933911-b0e1-45fb-ab61-a383a05ca9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854142081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.854142081
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.1825151585
Short name T341
Test name
Test status
Simulation time 70412577 ps
CPU time 0.79 seconds
Started Jul 01 04:49:11 PM PDT 24
Finished Jul 01 04:49:18 PM PDT 24
Peak memory 197108 kb
Host smart-9185b9d0-9b9a-4ece-bdd6-0f9b950d362d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825151585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.1825151585
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1658514684
Short name T576
Test name
Test status
Simulation time 504620689 ps
CPU time 6.21 seconds
Started Jul 01 04:49:10 PM PDT 24
Finished Jul 01 04:49:22 PM PDT 24
Peak memory 198624 kb
Host smart-2cbdafcc-2102-4117-920b-9191f8a36488
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658514684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.1658514684
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3369071430
Short name T180
Test name
Test status
Simulation time 140753783 ps
CPU time 1.26 seconds
Started Jul 01 04:49:21 PM PDT 24
Finished Jul 01 04:49:27 PM PDT 24
Peak memory 198700 kb
Host smart-17f39c65-85cc-49e4-aa2b-e24b54bffd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369071430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3369071430
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1774441087
Short name T337
Test name
Test status
Simulation time 839433696 ps
CPU time 1.14 seconds
Started Jul 01 04:49:14 PM PDT 24
Finished Jul 01 04:49:22 PM PDT 24
Peak memory 196580 kb
Host smart-70c44e27-af3b-4d8c-90b7-bbd3230b77a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774441087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1774441087
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1555150502
Short name T498
Test name
Test status
Simulation time 34822874533 ps
CPU time 103.24 seconds
Started Jul 01 04:49:10 PM PDT 24
Finished Jul 01 04:50:59 PM PDT 24
Peak memory 198760 kb
Host smart-184bb9c1-3653-48d9-af30-b0043cecb0e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555150502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1555150502
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.952650405
Short name T66
Test name
Test status
Simulation time 104320259742 ps
CPU time 1530.62 seconds
Started Jul 01 04:49:12 PM PDT 24
Finished Jul 01 05:14:50 PM PDT 24
Peak memory 198924 kb
Host smart-ca2d835c-efab-4337-87cb-8c01a6cd9c78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=952650405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.952650405
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.4291571448
Short name T294
Test name
Test status
Simulation time 11672853 ps
CPU time 0.58 seconds
Started Jul 01 04:49:23 PM PDT 24
Finished Jul 01 04:49:28 PM PDT 24
Peak memory 194660 kb
Host smart-83b71f1d-154a-46b7-aa32-17b1aca14a41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291571448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.4291571448
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2327723029
Short name T650
Test name
Test status
Simulation time 43892859 ps
CPU time 0.69 seconds
Started Jul 01 04:49:12 PM PDT 24
Finished Jul 01 04:49:20 PM PDT 24
Peak memory 194812 kb
Host smart-3ca01070-9ff2-4c56-861f-ef315d765ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327723029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2327723029
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2671742189
Short name T676
Test name
Test status
Simulation time 212486488 ps
CPU time 10.28 seconds
Started Jul 01 04:49:20 PM PDT 24
Finished Jul 01 04:49:35 PM PDT 24
Peak memory 196208 kb
Host smart-944f3f44-ab74-4a4b-a1ef-f0e1426b35fa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671742189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2671742189
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.3806395358
Short name T695
Test name
Test status
Simulation time 30159718 ps
CPU time 0.64 seconds
Started Jul 01 04:49:24 PM PDT 24
Finished Jul 01 04:49:29 PM PDT 24
Peak memory 195880 kb
Host smart-b756bc0b-ce4b-4438-8b7a-24d6a0bf080a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806395358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.3806395358
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2423511579
Short name T208
Test name
Test status
Simulation time 18628311 ps
CPU time 0.76 seconds
Started Jul 01 04:49:17 PM PDT 24
Finished Jul 01 04:49:24 PM PDT 24
Peak memory 195176 kb
Host smart-40617cf0-cbb7-44d4-b39c-3ec0bf5cb15a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423511579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2423511579
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.1484510622
Short name T308
Test name
Test status
Simulation time 30925226 ps
CPU time 1.29 seconds
Started Jul 01 04:49:12 PM PDT 24
Finished Jul 01 04:49:20 PM PDT 24
Peak memory 196764 kb
Host smart-dcca56d6-4961-44c5-abea-a334f700ca70
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484510622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.1484510622
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3857349583
Short name T469
Test name
Test status
Simulation time 241851254 ps
CPU time 2.79 seconds
Started Jul 01 04:49:12 PM PDT 24
Finished Jul 01 04:49:22 PM PDT 24
Peak memory 196504 kb
Host smart-024ad315-f9cb-475c-8b5a-14b5ee8b9ba6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857349583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3857349583
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2227193280
Short name T339
Test name
Test status
Simulation time 40084511 ps
CPU time 0.89 seconds
Started Jul 01 04:49:12 PM PDT 24
Finished Jul 01 04:49:19 PM PDT 24
Peak memory 196628 kb
Host smart-f0a0cc2c-30c1-4fe0-a4e8-9d653fb00dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227193280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2227193280
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3718529768
Short name T328
Test name
Test status
Simulation time 171633683 ps
CPU time 0.82 seconds
Started Jul 01 04:49:11 PM PDT 24
Finished Jul 01 04:49:19 PM PDT 24
Peak memory 197096 kb
Host smart-85d3b4b3-7654-4852-ad75-74b04f126a11
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718529768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3718529768
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1771748149
Short name T670
Test name
Test status
Simulation time 85061188 ps
CPU time 3.81 seconds
Started Jul 01 04:49:18 PM PDT 24
Finished Jul 01 04:49:28 PM PDT 24
Peak memory 198900 kb
Host smart-4be925da-d3b4-4208-9bc9-c28944463d86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771748149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1771748149
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.3334158761
Short name T365
Test name
Test status
Simulation time 147391619 ps
CPU time 1.24 seconds
Started Jul 01 04:49:12 PM PDT 24
Finished Jul 01 04:49:19 PM PDT 24
Peak memory 197476 kb
Host smart-54d44742-5102-484e-9599-5ea27cc53ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334158761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.3334158761
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3913413877
Short name T244
Test name
Test status
Simulation time 40312806 ps
CPU time 1.2 seconds
Started Jul 01 04:49:12 PM PDT 24
Finished Jul 01 04:49:19 PM PDT 24
Peak memory 196220 kb
Host smart-bd1061be-ab7e-4456-9055-abcdf09ccb55
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913413877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.3913413877
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.907423704
Short name T163
Test name
Test status
Simulation time 8201608957 ps
CPU time 119.61 seconds
Started Jul 01 04:49:21 PM PDT 24
Finished Jul 01 04:51:25 PM PDT 24
Peak memory 198776 kb
Host smart-c35b218b-6389-449f-a8ed-8508b880fcfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907423704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.g
pio_stress_all.907423704
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.725507602
Short name T536
Test name
Test status
Simulation time 23617023 ps
CPU time 0.58 seconds
Started Jul 01 04:49:19 PM PDT 24
Finished Jul 01 04:49:25 PM PDT 24
Peak memory 195452 kb
Host smart-ee51f5dd-456f-4267-beaf-9dfc683357fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725507602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.725507602
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1494632085
Short name T297
Test name
Test status
Simulation time 53549221 ps
CPU time 0.76 seconds
Started Jul 01 04:49:19 PM PDT 24
Finished Jul 01 04:49:25 PM PDT 24
Peak memory 195976 kb
Host smart-c720c3f2-d487-434a-8f5f-201ce9c51aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494632085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1494632085
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.3696186169
Short name T312
Test name
Test status
Simulation time 493135590 ps
CPU time 4.87 seconds
Started Jul 01 04:49:20 PM PDT 24
Finished Jul 01 04:49:30 PM PDT 24
Peak memory 196664 kb
Host smart-14539cca-a2f8-49dc-a0e6-185ef8039f73
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696186169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.3696186169
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3851817596
Short name T553
Test name
Test status
Simulation time 25032443 ps
CPU time 0.62 seconds
Started Jul 01 04:49:18 PM PDT 24
Finished Jul 01 04:49:24 PM PDT 24
Peak memory 194924 kb
Host smart-14d73847-0c13-4914-873e-a4f12828291b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851817596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3851817596
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.334655879
Short name T15
Test name
Test status
Simulation time 58025001 ps
CPU time 1.19 seconds
Started Jul 01 04:49:18 PM PDT 24
Finished Jul 01 04:49:25 PM PDT 24
Peak memory 196548 kb
Host smart-cae8aad3-9eb4-4543-b1a0-86525688900f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334655879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.334655879
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3508271346
Short name T140
Test name
Test status
Simulation time 117425161 ps
CPU time 2.41 seconds
Started Jul 01 04:49:22 PM PDT 24
Finished Jul 01 04:49:29 PM PDT 24
Peak memory 198700 kb
Host smart-ba13ac99-88da-4d52-95e3-9a17bc944088
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508271346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3508271346
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.839482630
Short name T622
Test name
Test status
Simulation time 254534777 ps
CPU time 2.66 seconds
Started Jul 01 04:49:17 PM PDT 24
Finished Jul 01 04:49:26 PM PDT 24
Peak memory 197916 kb
Host smart-b9db67c2-dede-47c1-af9f-57966159494f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839482630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.
839482630
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.865611849
Short name T16
Test name
Test status
Simulation time 48030947 ps
CPU time 0.74 seconds
Started Jul 01 04:49:16 PM PDT 24
Finished Jul 01 04:49:24 PM PDT 24
Peak memory 196680 kb
Host smart-e18cd35d-a1d6-4ae5-ae25-6d092dd0e806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865611849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.865611849
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1162901835
Short name T626
Test name
Test status
Simulation time 131544864 ps
CPU time 1.21 seconds
Started Jul 01 04:49:24 PM PDT 24
Finished Jul 01 04:49:29 PM PDT 24
Peak memory 198716 kb
Host smart-972d394c-5b7b-4c64-901f-67c3f17db4fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162901835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1162901835
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2354519059
Short name T359
Test name
Test status
Simulation time 359115298 ps
CPU time 4.03 seconds
Started Jul 01 04:49:22 PM PDT 24
Finished Jul 01 04:49:31 PM PDT 24
Peak memory 198616 kb
Host smart-d81d3110-5f3d-44d6-858a-557583e652af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354519059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.2354519059
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.39258590
Short name T133
Test name
Test status
Simulation time 91599596 ps
CPU time 1.1 seconds
Started Jul 01 04:49:20 PM PDT 24
Finished Jul 01 04:49:26 PM PDT 24
Peak memory 196164 kb
Host smart-cbf0852e-6f5f-421b-90ed-29594d77d93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39258590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.39258590
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.1222580374
Short name T594
Test name
Test status
Simulation time 37533740 ps
CPU time 1.21 seconds
Started Jul 01 04:49:23 PM PDT 24
Finished Jul 01 04:49:29 PM PDT 24
Peak memory 196292 kb
Host smart-9087315c-368c-4632-b575-0bfbd831a6ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222580374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.1222580374
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1973167980
Short name T247
Test name
Test status
Simulation time 58835612163 ps
CPU time 44.9 seconds
Started Jul 01 04:49:18 PM PDT 24
Finished Jul 01 04:50:09 PM PDT 24
Peak memory 198760 kb
Host smart-5608d2bc-a059-4941-90fb-ae2c98c7d6a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973167980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1973167980
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.1195337887
Short name T685
Test name
Test status
Simulation time 37349212 ps
CPU time 0.58 seconds
Started Jul 01 04:49:19 PM PDT 24
Finished Jul 01 04:49:25 PM PDT 24
Peak memory 195360 kb
Host smart-9f622855-cd9f-4be7-beff-77bd1a66a294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195337887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1195337887
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1594966317
Short name T12
Test name
Test status
Simulation time 62556425 ps
CPU time 0.78 seconds
Started Jul 01 04:49:19 PM PDT 24
Finished Jul 01 04:49:25 PM PDT 24
Peak memory 195840 kb
Host smart-8d91f960-5877-4999-830b-3a0a81ef29f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594966317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1594966317
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.2625682256
Short name T435
Test name
Test status
Simulation time 1483149890 ps
CPU time 19.75 seconds
Started Jul 01 04:49:18 PM PDT 24
Finished Jul 01 04:49:43 PM PDT 24
Peak memory 197664 kb
Host smart-de629734-339e-4d9b-bf12-0698475da6e8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625682256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.2625682256
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.1187285690
Short name T157
Test name
Test status
Simulation time 226593752 ps
CPU time 0.96 seconds
Started Jul 01 04:49:19 PM PDT 24
Finished Jul 01 04:49:25 PM PDT 24
Peak memory 197872 kb
Host smart-25d0579c-99b1-4501-97db-cfc13ae74f76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187285690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.1187285690
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.1800244724
Short name T653
Test name
Test status
Simulation time 130586372 ps
CPU time 1.03 seconds
Started Jul 01 04:49:18 PM PDT 24
Finished Jul 01 04:49:24 PM PDT 24
Peak memory 196796 kb
Host smart-d755205b-e0d0-4866-94a9-4194a2314970
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800244724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.1800244724
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.2795615137
Short name T192
Test name
Test status
Simulation time 295059128 ps
CPU time 2.87 seconds
Started Jul 01 04:49:20 PM PDT 24
Finished Jul 01 04:49:28 PM PDT 24
Peak memory 198724 kb
Host smart-11b597f5-4e19-4ce8-ba30-6492bc5da2af
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795615137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.2795615137
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.2879371755
Short name T513
Test name
Test status
Simulation time 163282775 ps
CPU time 3.08 seconds
Started Jul 01 04:49:22 PM PDT 24
Finished Jul 01 04:49:29 PM PDT 24
Peak memory 198660 kb
Host smart-a6564453-8e11-4a89-a7a7-e2bd79d80e45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879371755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.2879371755
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3494008449
Short name T664
Test name
Test status
Simulation time 62771071 ps
CPU time 0.79 seconds
Started Jul 01 04:49:19 PM PDT 24
Finished Jul 01 04:49:25 PM PDT 24
Peak memory 196812 kb
Host smart-d744a79e-d39e-4640-bb51-80b077315df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494008449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3494008449
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2855097994
Short name T56
Test name
Test status
Simulation time 44172739 ps
CPU time 1 seconds
Started Jul 01 04:49:20 PM PDT 24
Finished Jul 01 04:49:26 PM PDT 24
Peak memory 197368 kb
Host smart-c4f431a6-0b3b-44c5-a44f-e4b3c3f5dc32
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855097994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2855097994
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2357971258
Short name T156
Test name
Test status
Simulation time 3047834781 ps
CPU time 4.46 seconds
Started Jul 01 04:49:20 PM PDT 24
Finished Jul 01 04:49:29 PM PDT 24
Peak memory 198712 kb
Host smart-6f707190-18e1-45e4-9a79-9060e3b7031f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357971258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.2357971258
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.2730345600
Short name T459
Test name
Test status
Simulation time 1073842444 ps
CPU time 1.12 seconds
Started Jul 01 04:49:23 PM PDT 24
Finished Jul 01 04:49:28 PM PDT 24
Peak memory 196200 kb
Host smart-68707a0a-9de2-4233-84e3-642801c4420d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730345600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.2730345600
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3850623788
Short name T667
Test name
Test status
Simulation time 370969587 ps
CPU time 1.21 seconds
Started Jul 01 04:49:20 PM PDT 24
Finished Jul 01 04:49:26 PM PDT 24
Peak memory 196540 kb
Host smart-49d576f7-21fb-4a80-86b6-7541f7b170fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850623788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3850623788
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.277053481
Short name T512
Test name
Test status
Simulation time 6890055404 ps
CPU time 181.45 seconds
Started Jul 01 04:49:23 PM PDT 24
Finished Jul 01 04:52:28 PM PDT 24
Peak memory 198888 kb
Host smart-babffa89-a285-4be6-8e86-04eb0df150f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277053481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.g
pio_stress_all.277053481
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.2451262459
Short name T493
Test name
Test status
Simulation time 15410354527 ps
CPU time 528.94 seconds
Started Jul 01 04:49:24 PM PDT 24
Finished Jul 01 04:58:17 PM PDT 24
Peak memory 198956 kb
Host smart-5215685d-71e0-42ef-9b70-ef1f34dfa3af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2451262459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.2451262459
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1403168302
Short name T471
Test name
Test status
Simulation time 36784419 ps
CPU time 0.64 seconds
Started Jul 01 04:49:27 PM PDT 24
Finished Jul 01 04:49:32 PM PDT 24
Peak memory 193440 kb
Host smart-f722bd11-cf33-4346-8ea6-b482c91bc9ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403168302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1403168302
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.3623119497
Short name T150
Test name
Test status
Simulation time 21438095 ps
CPU time 0.78 seconds
Started Jul 01 04:49:33 PM PDT 24
Finished Jul 01 04:49:37 PM PDT 24
Peak memory 196680 kb
Host smart-2cc8a070-4897-4928-b2b2-8ba44cee5c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623119497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.3623119497
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.2665942675
Short name T374
Test name
Test status
Simulation time 1777709322 ps
CPU time 21.6 seconds
Started Jul 01 04:49:29 PM PDT 24
Finished Jul 01 04:49:56 PM PDT 24
Peak memory 197152 kb
Host smart-c10f7ceb-b267-43d1-82d8-79491907d539
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665942675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.2665942675
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.2257622991
Short name T9
Test name
Test status
Simulation time 235120529 ps
CPU time 0.91 seconds
Started Jul 01 04:49:29 PM PDT 24
Finished Jul 01 04:49:34 PM PDT 24
Peak memory 196720 kb
Host smart-67f0ae08-b0b0-4424-b720-58a52400ac78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257622991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.2257622991
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2393393648
Short name T497
Test name
Test status
Simulation time 320307847 ps
CPU time 1.29 seconds
Started Jul 01 04:49:28 PM PDT 24
Finished Jul 01 04:49:34 PM PDT 24
Peak memory 197836 kb
Host smart-5541722f-dc17-4514-9ae4-7eed19e55429
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393393648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2393393648
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3122610887
Short name T209
Test name
Test status
Simulation time 251860317 ps
CPU time 2.83 seconds
Started Jul 01 04:49:32 PM PDT 24
Finished Jul 01 04:49:39 PM PDT 24
Peak memory 198720 kb
Host smart-17f2f95c-bc72-4b88-8427-a0fba8bba1fd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122610887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.3122610887
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.551129050
Short name T146
Test name
Test status
Simulation time 145245423 ps
CPU time 3.26 seconds
Started Jul 01 04:49:27 PM PDT 24
Finished Jul 01 04:49:36 PM PDT 24
Peak memory 198736 kb
Host smart-940093f3-d781-4006-8544-9c404b70b41a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551129050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger.
551129050
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1294542164
Short name T634
Test name
Test status
Simulation time 130269074 ps
CPU time 0.77 seconds
Started Jul 01 04:49:17 PM PDT 24
Finished Jul 01 04:49:24 PM PDT 24
Peak memory 196728 kb
Host smart-13ce4d75-7922-4f55-8775-d329fdbf0b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294542164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1294542164
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3319171507
Short name T484
Test name
Test status
Simulation time 54887300 ps
CPU time 1.09 seconds
Started Jul 01 04:49:19 PM PDT 24
Finished Jul 01 04:49:25 PM PDT 24
Peak memory 196508 kb
Host smart-92e1bc94-8076-4624-81c3-77cb8ed74ff7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319171507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3319171507
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2877127476
Short name T464
Test name
Test status
Simulation time 346483914 ps
CPU time 4.16 seconds
Started Jul 01 04:49:26 PM PDT 24
Finished Jul 01 04:49:34 PM PDT 24
Peak memory 198704 kb
Host smart-3d2118c5-2ea8-4eab-b154-7367eff1ecf9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877127476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2877127476
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.4025394477
Short name T468
Test name
Test status
Simulation time 103297509 ps
CPU time 0.97 seconds
Started Jul 01 04:49:19 PM PDT 24
Finished Jul 01 04:49:26 PM PDT 24
Peak memory 197180 kb
Host smart-286389f6-39e9-4850-b93d-54cc8072e29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025394477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.4025394477
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.15289299
Short name T689
Test name
Test status
Simulation time 72380507 ps
CPU time 0.89 seconds
Started Jul 01 04:49:19 PM PDT 24
Finished Jul 01 04:49:25 PM PDT 24
Peak memory 196812 kb
Host smart-ba8efaac-5113-4e6f-a2d0-f7b8d994aec3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15289299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.15289299
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.1874774511
Short name T273
Test name
Test status
Simulation time 13151261813 ps
CPU time 177.17 seconds
Started Jul 01 04:49:26 PM PDT 24
Finished Jul 01 04:52:28 PM PDT 24
Peak memory 198796 kb
Host smart-4e6e1402-aa2c-42da-a636-ffe286aec324
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874774511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.1874774511
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.4294790203
Short name T407
Test name
Test status
Simulation time 71431201238 ps
CPU time 1532.98 seconds
Started Jul 01 04:49:28 PM PDT 24
Finished Jul 01 05:15:06 PM PDT 24
Peak memory 199060 kb
Host smart-97f55047-b12b-4bcd-92c8-75475a0c15c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4294790203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.4294790203
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2090452201
Short name T11
Test name
Test status
Simulation time 35782865 ps
CPU time 0.56 seconds
Started Jul 01 04:48:28 PM PDT 24
Finished Jul 01 04:48:31 PM PDT 24
Peak memory 194668 kb
Host smart-3cbc6cfc-4cfe-43c0-a949-00b38ecc0b7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090452201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2090452201
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3683963220
Short name T671
Test name
Test status
Simulation time 48081639 ps
CPU time 0.99 seconds
Started Jul 01 04:48:26 PM PDT 24
Finished Jul 01 04:48:29 PM PDT 24
Peak memory 197208 kb
Host smart-8de101ac-1479-4ec9-b85e-b33b3a3fb1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683963220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3683963220
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1662097083
Short name T355
Test name
Test status
Simulation time 2302194270 ps
CPU time 19.9 seconds
Started Jul 01 04:48:27 PM PDT 24
Finished Jul 01 04:48:50 PM PDT 24
Peak memory 197740 kb
Host smart-ae3cee59-c77b-46ed-8fa3-c834684a0078
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662097083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1662097083
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.255808814
Short name T238
Test name
Test status
Simulation time 74420721 ps
CPU time 0.92 seconds
Started Jul 01 04:48:37 PM PDT 24
Finished Jul 01 04:48:41 PM PDT 24
Peak memory 197264 kb
Host smart-324786a3-26db-4094-807e-b0ba792960f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255808814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.255808814
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.539548759
Short name T220
Test name
Test status
Simulation time 19676272 ps
CPU time 0.71 seconds
Started Jul 01 04:48:27 PM PDT 24
Finished Jul 01 04:48:31 PM PDT 24
Peak memory 194920 kb
Host smart-0f843b7c-599e-47cd-8d05-39db9f71f9ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539548759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.539548759
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1856992975
Short name T422
Test name
Test status
Simulation time 160471478 ps
CPU time 3.04 seconds
Started Jul 01 04:48:28 PM PDT 24
Finished Jul 01 04:48:35 PM PDT 24
Peak memory 197140 kb
Host smart-4333e823-f919-461f-ba1d-494b638e3dae
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856992975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1856992975
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.3373146624
Short name T26
Test name
Test status
Simulation time 79674288 ps
CPU time 2.44 seconds
Started Jul 01 04:48:29 PM PDT 24
Finished Jul 01 04:48:35 PM PDT 24
Peak memory 197808 kb
Host smart-ea24cc13-821b-4886-be9b-30489234389c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373146624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
3373146624
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.2198482399
Short name T618
Test name
Test status
Simulation time 44622034 ps
CPU time 0.89 seconds
Started Jul 01 04:48:26 PM PDT 24
Finished Jul 01 04:48:28 PM PDT 24
Peak memory 196684 kb
Host smart-cabb4ce9-7be5-4396-a255-38218c24292c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198482399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.2198482399
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2773965721
Short name T177
Test name
Test status
Simulation time 189761983 ps
CPU time 1.05 seconds
Started Jul 01 04:48:25 PM PDT 24
Finished Jul 01 04:48:28 PM PDT 24
Peak memory 196612 kb
Host smart-a7e200b8-3048-4464-af01-1bc3ab3e0ced
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773965721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2773965721
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2650603567
Short name T368
Test name
Test status
Simulation time 194204210 ps
CPU time 3.41 seconds
Started Jul 01 04:48:33 PM PDT 24
Finished Jul 01 04:48:38 PM PDT 24
Peak memory 198672 kb
Host smart-2cf47992-9c3b-4121-b2e4-2c37b0e63b0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650603567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.2650603567
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.3019892745
Short name T42
Test name
Test status
Simulation time 384585909 ps
CPU time 0.89 seconds
Started Jul 01 04:48:30 PM PDT 24
Finished Jul 01 04:48:34 PM PDT 24
Peak memory 214232 kb
Host smart-cd5e5190-03f9-4cf4-9f16-d39ae89e3919
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019892745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.3019892745
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.3064344533
Short name T285
Test name
Test status
Simulation time 364594853 ps
CPU time 1.4 seconds
Started Jul 01 04:48:24 PM PDT 24
Finished Jul 01 04:48:28 PM PDT 24
Peak memory 197416 kb
Host smart-3aedb86a-028b-4114-a7fb-ae881003ed5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064344533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3064344533
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.4100102092
Short name T204
Test name
Test status
Simulation time 432541401 ps
CPU time 1.11 seconds
Started Jul 01 04:48:22 PM PDT 24
Finished Jul 01 04:48:25 PM PDT 24
Peak memory 196920 kb
Host smart-e17a342a-f92c-429c-9d2f-525d637e6db1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100102092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.4100102092
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.470329541
Short name T272
Test name
Test status
Simulation time 17347108953 ps
CPU time 195.32 seconds
Started Jul 01 04:48:27 PM PDT 24
Finished Jul 01 04:51:44 PM PDT 24
Peak memory 198776 kb
Host smart-50d0149d-18fd-4af5-89d8-826b7ced22d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470329541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gp
io_stress_all.470329541
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1328002644
Short name T654
Test name
Test status
Simulation time 46780800 ps
CPU time 0.59 seconds
Started Jul 01 04:49:27 PM PDT 24
Finished Jul 01 04:49:31 PM PDT 24
Peak memory 194684 kb
Host smart-9cbb3a0d-ddd7-4414-9f05-ed75aa6d87a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328002644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1328002644
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.3087700423
Short name T186
Test name
Test status
Simulation time 486389215 ps
CPU time 0.87 seconds
Started Jul 01 04:49:27 PM PDT 24
Finished Jul 01 04:49:31 PM PDT 24
Peak memory 196640 kb
Host smart-e826b23b-8031-4671-bb1f-4438c5dbb91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087700423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.3087700423
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.878330605
Short name T58
Test name
Test status
Simulation time 257491241 ps
CPU time 4.46 seconds
Started Jul 01 04:49:27 PM PDT 24
Finished Jul 01 04:49:37 PM PDT 24
Peak memory 196552 kb
Host smart-f67ffd7d-721b-44cd-a271-9f4fe858b155
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878330605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stres
s.878330605
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.34745333
Short name T185
Test name
Test status
Simulation time 60244578 ps
CPU time 0.95 seconds
Started Jul 01 04:49:28 PM PDT 24
Finished Jul 01 04:49:34 PM PDT 24
Peak memory 197492 kb
Host smart-211d6b0a-f71a-4779-8c13-3dd73c779a0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34745333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.34745333
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.264189714
Short name T466
Test name
Test status
Simulation time 168782491 ps
CPU time 1.3 seconds
Started Jul 01 04:49:27 PM PDT 24
Finished Jul 01 04:49:32 PM PDT 24
Peak memory 198728 kb
Host smart-9610be0e-4a84-43e6-86d5-e15478cd7dd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264189714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.264189714
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3164693468
Short name T389
Test name
Test status
Simulation time 41958684 ps
CPU time 1.78 seconds
Started Jul 01 04:49:29 PM PDT 24
Finished Jul 01 04:49:36 PM PDT 24
Peak memory 198784 kb
Host smart-20efca53-2c7c-4273-85da-6843626663aa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164693468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3164693468
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.4133893637
Short name T346
Test name
Test status
Simulation time 389968761 ps
CPU time 2.94 seconds
Started Jul 01 04:49:32 PM PDT 24
Finished Jul 01 04:49:39 PM PDT 24
Peak memory 198708 kb
Host smart-007d1d2a-641d-47eb-9925-235d01f3c6b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133893637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.4133893637
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.460148730
Short name T574
Test name
Test status
Simulation time 275458397 ps
CPU time 1.27 seconds
Started Jul 01 04:49:29 PM PDT 24
Finished Jul 01 04:49:35 PM PDT 24
Peak memory 197872 kb
Host smart-14f1a35e-70c5-4bee-8b2f-166e0a21f591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460148730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.460148730
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.3463764397
Short name T586
Test name
Test status
Simulation time 32271559 ps
CPU time 1.14 seconds
Started Jul 01 04:49:31 PM PDT 24
Finished Jul 01 04:49:36 PM PDT 24
Peak memory 197796 kb
Host smart-685eaeca-7c1a-4075-ae48-fd0edf4ffef3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463764397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.3463764397
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.1715913913
Short name T611
Test name
Test status
Simulation time 129256811 ps
CPU time 1.44 seconds
Started Jul 01 04:49:26 PM PDT 24
Finished Jul 01 04:49:32 PM PDT 24
Peak memory 198660 kb
Host smart-9aab624e-4281-49cd-928e-0c95b3312a52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715913913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.1715913913
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.1957040160
Short name T531
Test name
Test status
Simulation time 112259045 ps
CPU time 0.81 seconds
Started Jul 01 04:49:31 PM PDT 24
Finished Jul 01 04:49:36 PM PDT 24
Peak memory 196512 kb
Host smart-e5737697-6576-408e-be7e-c58f75dd7038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957040160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.1957040160
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.1621408893
Short name T709
Test name
Test status
Simulation time 64160675 ps
CPU time 0.73 seconds
Started Jul 01 04:49:32 PM PDT 24
Finished Jul 01 04:49:36 PM PDT 24
Peak memory 195772 kb
Host smart-0652d0b0-7271-4479-8224-f74b4ee296f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621408893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.1621408893
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2216037689
Short name T632
Test name
Test status
Simulation time 6456579583 ps
CPU time 167.09 seconds
Started Jul 01 04:49:30 PM PDT 24
Finished Jul 01 04:52:22 PM PDT 24
Peak memory 198556 kb
Host smart-1f6cbfee-e47e-40d3-baea-d4f1fdace698
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216037689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2216037689
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.352277942
Short name T450
Test name
Test status
Simulation time 30768471 ps
CPU time 0.61 seconds
Started Jul 01 04:49:33 PM PDT 24
Finished Jul 01 04:49:37 PM PDT 24
Peak memory 194864 kb
Host smart-a3e2637d-6d08-4a51-b7e8-3b426a2fc790
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352277942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.352277942
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2361555838
Short name T499
Test name
Test status
Simulation time 109781934 ps
CPU time 0.84 seconds
Started Jul 01 04:49:27 PM PDT 24
Finished Jul 01 04:49:31 PM PDT 24
Peak memory 197980 kb
Host smart-bf7ed2ed-2e86-4160-bfe3-d14cbb6f6dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361555838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2361555838
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.3320774633
Short name T139
Test name
Test status
Simulation time 128690446 ps
CPU time 3.94 seconds
Started Jul 01 04:49:26 PM PDT 24
Finished Jul 01 04:49:33 PM PDT 24
Peak memory 197232 kb
Host smart-8c82af08-9523-435c-8d9d-39f561bcbfad
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320774633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.3320774633
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.1669693149
Short name T567
Test name
Test status
Simulation time 33426967 ps
CPU time 0.78 seconds
Started Jul 01 04:49:30 PM PDT 24
Finished Jul 01 04:49:35 PM PDT 24
Peak memory 196216 kb
Host smart-4eb21ab1-f8ad-41c1-9249-7ede4564d0cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669693149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.1669693149
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.1476427960
Short name T623
Test name
Test status
Simulation time 302083421 ps
CPU time 1.33 seconds
Started Jul 01 04:49:27 PM PDT 24
Finished Jul 01 04:49:34 PM PDT 24
Peak memory 197812 kb
Host smart-627f44c6-77d1-4c89-89e0-5f9c8cda75ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476427960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.1476427960
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1417381853
Short name T370
Test name
Test status
Simulation time 91160015 ps
CPU time 3.69 seconds
Started Jul 01 04:49:27 PM PDT 24
Finished Jul 01 04:49:36 PM PDT 24
Peak memory 198744 kb
Host smart-06cb8087-cf3c-431c-9d7e-c8d018688d7b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417381853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1417381853
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.3785232355
Short name T257
Test name
Test status
Simulation time 108728758 ps
CPU time 2.6 seconds
Started Jul 01 04:49:34 PM PDT 24
Finished Jul 01 04:49:39 PM PDT 24
Peak memory 197836 kb
Host smart-54ed1624-3ebf-4976-b51a-0940a33a470f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785232355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.3785232355
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.4093530514
Short name T60
Test name
Test status
Simulation time 120802406 ps
CPU time 1.26 seconds
Started Jul 01 04:49:31 PM PDT 24
Finished Jul 01 04:49:36 PM PDT 24
Peak memory 197236 kb
Host smart-47f1b88e-36fc-4e21-8a2d-93199b61199d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093530514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.4093530514
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2443490662
Short name T465
Test name
Test status
Simulation time 22536182 ps
CPU time 0.68 seconds
Started Jul 01 04:49:28 PM PDT 24
Finished Jul 01 04:49:33 PM PDT 24
Peak memory 194968 kb
Host smart-172adf9b-6751-4643-adcb-bafe11a5091f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443490662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2443490662
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2870049746
Short name T378
Test name
Test status
Simulation time 429428220 ps
CPU time 1.78 seconds
Started Jul 01 04:49:28 PM PDT 24
Finished Jul 01 04:49:34 PM PDT 24
Peak memory 198580 kb
Host smart-1d05a30c-8083-4409-83de-eaa2afde7460
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870049746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2870049746
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.1784019694
Short name T677
Test name
Test status
Simulation time 234735616 ps
CPU time 1.04 seconds
Started Jul 01 04:49:33 PM PDT 24
Finished Jul 01 04:49:38 PM PDT 24
Peak memory 196540 kb
Host smart-82ceae84-6397-42ab-a9a0-832846c502d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784019694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.1784019694
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3628884091
Short name T439
Test name
Test status
Simulation time 250275149 ps
CPU time 0.72 seconds
Started Jul 01 04:49:29 PM PDT 24
Finished Jul 01 04:49:35 PM PDT 24
Peak memory 195776 kb
Host smart-62a9eeb0-b0a4-42af-a2de-998e47d884bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628884091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3628884091
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.4009139432
Short name T307
Test name
Test status
Simulation time 6828059262 ps
CPU time 48.72 seconds
Started Jul 01 04:49:28 PM PDT 24
Finished Jul 01 04:50:21 PM PDT 24
Peak memory 198796 kb
Host smart-9804e33b-8984-44e2-a4a0-25d4b0cee1a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009139432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.4009139432
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.2217281220
Short name T647
Test name
Test status
Simulation time 58466973576 ps
CPU time 1532.67 seconds
Started Jul 01 04:49:29 PM PDT 24
Finished Jul 01 05:15:07 PM PDT 24
Peak memory 198940 kb
Host smart-5ce276b7-d773-4cdc-984e-6fbf4b880acd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2217281220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.2217281220
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.220480967
Short name T384
Test name
Test status
Simulation time 17297667 ps
CPU time 0.6 seconds
Started Jul 01 04:49:38 PM PDT 24
Finished Jul 01 04:49:41 PM PDT 24
Peak memory 195560 kb
Host smart-706f3796-b125-4b62-96cb-70dbd62233c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220480967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.220480967
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2392454321
Short name T237
Test name
Test status
Simulation time 27566641 ps
CPU time 0.73 seconds
Started Jul 01 04:49:39 PM PDT 24
Finished Jul 01 04:49:42 PM PDT 24
Peak memory 196576 kb
Host smart-b016ce55-4a84-4ec4-9651-08856bcf3e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392454321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2392454321
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1199226456
Short name T456
Test name
Test status
Simulation time 910549740 ps
CPU time 21.73 seconds
Started Jul 01 04:49:40 PM PDT 24
Finished Jul 01 04:50:05 PM PDT 24
Peak memory 197576 kb
Host smart-14a033b9-89c7-4d66-b558-6a30f7de6596
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199226456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1199226456
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1773789490
Short name T349
Test name
Test status
Simulation time 126272462 ps
CPU time 0.87 seconds
Started Jul 01 04:49:37 PM PDT 24
Finished Jul 01 04:49:41 PM PDT 24
Peak memory 197200 kb
Host smart-293c0d65-1e41-4453-9c93-97c82b3d1a61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773789490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1773789490
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.149917203
Short name T410
Test name
Test status
Simulation time 103738945 ps
CPU time 1.55 seconds
Started Jul 01 04:49:36 PM PDT 24
Finished Jul 01 04:49:40 PM PDT 24
Peak memory 197816 kb
Host smart-c914920d-ccc9-4d8f-b60e-41d06fbe5e99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149917203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.149917203
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2651506087
Short name T14
Test name
Test status
Simulation time 530796877 ps
CPU time 2.9 seconds
Started Jul 01 04:49:37 PM PDT 24
Finished Jul 01 04:49:42 PM PDT 24
Peak memory 198668 kb
Host smart-63282328-b182-457b-97e7-1581a1eedd54
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651506087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2651506087
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.322609498
Short name T30
Test name
Test status
Simulation time 109091290 ps
CPU time 1.76 seconds
Started Jul 01 04:49:37 PM PDT 24
Finished Jul 01 04:49:42 PM PDT 24
Peak memory 197520 kb
Host smart-8f0c35d4-e4d2-45ca-b754-89cdb81483d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322609498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.
322609498
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3136445765
Short name T590
Test name
Test status
Simulation time 25429464 ps
CPU time 0.75 seconds
Started Jul 01 04:49:26 PM PDT 24
Finished Jul 01 04:49:31 PM PDT 24
Peak memory 196792 kb
Host smart-d5f5c828-1d6d-47d1-b556-c0cfa5fc452b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136445765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3136445765
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2651031528
Short name T28
Test name
Test status
Simulation time 18236954 ps
CPU time 0.73 seconds
Started Jul 01 04:49:28 PM PDT 24
Finished Jul 01 04:49:33 PM PDT 24
Peak memory 196708 kb
Host smart-e0486785-0b35-4073-b9c2-e002934cfa59
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651031528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2651031528
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.455311578
Short name T631
Test name
Test status
Simulation time 1789943358 ps
CPU time 2.48 seconds
Started Jul 01 04:49:37 PM PDT 24
Finished Jul 01 04:49:42 PM PDT 24
Peak memory 198748 kb
Host smart-0ea0d7c1-2a52-4ea7-a067-268d90c6de7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455311578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ran
dom_long_reg_writes_reg_reads.455311578
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2709527398
Short name T540
Test name
Test status
Simulation time 197900829 ps
CPU time 1.06 seconds
Started Jul 01 04:49:30 PM PDT 24
Finished Jul 01 04:49:36 PM PDT 24
Peak memory 196264 kb
Host smart-6c5b2866-f46b-4564-a3c3-1bf68139c4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709527398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2709527398
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3283237835
Short name T723
Test name
Test status
Simulation time 207715487 ps
CPU time 1.15 seconds
Started Jul 01 04:49:24 PM PDT 24
Finished Jul 01 04:49:29 PM PDT 24
Peak memory 196948 kb
Host smart-8ffcaf3d-481d-4ee2-a903-d751830f3d58
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283237835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3283237835
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.571266893
Short name T411
Test name
Test status
Simulation time 30181845426 ps
CPU time 197.84 seconds
Started Jul 01 04:49:38 PM PDT 24
Finished Jul 01 04:52:58 PM PDT 24
Peak memory 198792 kb
Host smart-02fa00d4-1de8-4852-91b9-21927132478d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571266893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.571266893
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.243898275
Short name T358
Test name
Test status
Simulation time 19147945 ps
CPU time 0.58 seconds
Started Jul 01 04:49:41 PM PDT 24
Finished Jul 01 04:49:45 PM PDT 24
Peak memory 194676 kb
Host smart-1f0580c3-9c7a-4bc6-afcf-5b5991bb6160
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243898275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.243898275
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.1579561497
Short name T304
Test name
Test status
Simulation time 30168370 ps
CPU time 0.93 seconds
Started Jul 01 04:49:40 PM PDT 24
Finished Jul 01 04:49:44 PM PDT 24
Peak memory 196632 kb
Host smart-016479c8-218f-44f3-8c47-ac356a0ed4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579561497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.1579561497
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.1186331727
Short name T356
Test name
Test status
Simulation time 1481767685 ps
CPU time 10.97 seconds
Started Jul 01 04:49:41 PM PDT 24
Finished Jul 01 04:49:55 PM PDT 24
Peak memory 198680 kb
Host smart-32fb5039-5542-4469-8359-ad065f3542d5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186331727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1186331727
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1873376484
Short name T27
Test name
Test status
Simulation time 121565540 ps
CPU time 0.7 seconds
Started Jul 01 04:49:37 PM PDT 24
Finished Jul 01 04:49:41 PM PDT 24
Peak memory 195188 kb
Host smart-f24b1d64-934e-44b7-8a86-9b03ec8dd7cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873376484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1873376484
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.1254030634
Short name T202
Test name
Test status
Simulation time 112620612 ps
CPU time 0.9 seconds
Started Jul 01 04:49:36 PM PDT 24
Finished Jul 01 04:49:39 PM PDT 24
Peak memory 196788 kb
Host smart-9292f59e-f93d-46bd-bc7d-c97027d483d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254030634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.1254030634
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.901265480
Short name T388
Test name
Test status
Simulation time 211224080 ps
CPU time 1.52 seconds
Started Jul 01 04:49:39 PM PDT 24
Finished Jul 01 04:49:43 PM PDT 24
Peak memory 196932 kb
Host smart-92825213-2532-4f5b-a410-c8c46edd2dd0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901265480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.gpio_intr_with_filter_rand_intr_event.901265480
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.1451806551
Short name T78
Test name
Test status
Simulation time 207419101 ps
CPU time 2.23 seconds
Started Jul 01 04:49:40 PM PDT 24
Finished Jul 01 04:49:45 PM PDT 24
Peak memory 197896 kb
Host smart-341a0c91-5822-415c-8d1b-08a9d072ff14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451806551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.1451806551
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.4028255303
Short name T453
Test name
Test status
Simulation time 91338494 ps
CPU time 0.94 seconds
Started Jul 01 04:49:37 PM PDT 24
Finished Jul 01 04:49:41 PM PDT 24
Peak memory 196688 kb
Host smart-eb5c1d29-b626-4053-9d66-d84aed2f5c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028255303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.4028255303
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.1869608836
Short name T585
Test name
Test status
Simulation time 141045428 ps
CPU time 1.01 seconds
Started Jul 01 04:49:39 PM PDT 24
Finished Jul 01 04:49:43 PM PDT 24
Peak memory 197416 kb
Host smart-062ab93f-f051-4567-a8d8-05f4d18ba65b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869608836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.1869608836
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.468437358
Short name T2
Test name
Test status
Simulation time 440190243 ps
CPU time 4.49 seconds
Started Jul 01 04:49:39 PM PDT 24
Finished Jul 01 04:49:46 PM PDT 24
Peak memory 198636 kb
Host smart-6605a3ce-810d-44cf-ac5d-848e90d464bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468437358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran
dom_long_reg_writes_reg_reads.468437358
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.1829398014
Short name T363
Test name
Test status
Simulation time 43355796 ps
CPU time 1.18 seconds
Started Jul 01 04:49:37 PM PDT 24
Finished Jul 01 04:49:41 PM PDT 24
Peak memory 196228 kb
Host smart-e5310e03-0b1b-4699-8bbe-8bb8b5146b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829398014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.1829398014
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.1446062748
Short name T119
Test name
Test status
Simulation time 354132238 ps
CPU time 1.38 seconds
Started Jul 01 04:49:37 PM PDT 24
Finished Jul 01 04:49:41 PM PDT 24
Peak memory 197092 kb
Host smart-c6ec3c62-e9cc-4c69-983a-001cd0f33cc1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446062748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.1446062748
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1627645420
Short name T448
Test name
Test status
Simulation time 64448793008 ps
CPU time 170.39 seconds
Started Jul 01 04:49:39 PM PDT 24
Finished Jul 01 04:52:32 PM PDT 24
Peak memory 198996 kb
Host smart-f837e6d5-10df-4084-a7ae-74fe1a46a5b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627645420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1627645420
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.772274535
Short name T658
Test name
Test status
Simulation time 11448646 ps
CPU time 0.6 seconds
Started Jul 01 04:49:36 PM PDT 24
Finished Jul 01 04:49:39 PM PDT 24
Peak memory 194908 kb
Host smart-6350f416-68fa-43ba-a64c-ce6b2f4353f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772274535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.772274535
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.2646990186
Short name T144
Test name
Test status
Simulation time 16216436 ps
CPU time 0.66 seconds
Started Jul 01 04:49:38 PM PDT 24
Finished Jul 01 04:49:41 PM PDT 24
Peak memory 194752 kb
Host smart-8f94b475-c301-4e7a-a1c2-13db79c43001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646990186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.2646990186
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.1520446812
Short name T379
Test name
Test status
Simulation time 197700529 ps
CPU time 6.63 seconds
Started Jul 01 04:49:37 PM PDT 24
Finished Jul 01 04:49:47 PM PDT 24
Peak memory 197060 kb
Host smart-c3db69ee-2322-4907-b217-5f0476d7084c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520446812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.1520446812
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2987293436
Short name T600
Test name
Test status
Simulation time 305259100 ps
CPU time 0.93 seconds
Started Jul 01 04:49:38 PM PDT 24
Finished Jul 01 04:49:41 PM PDT 24
Peak memory 198612 kb
Host smart-d18b446a-3f75-44be-ac86-610d010dd9bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987293436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2987293436
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1586870135
Short name T291
Test name
Test status
Simulation time 56620946 ps
CPU time 0.86 seconds
Started Jul 01 04:49:36 PM PDT 24
Finished Jul 01 04:49:39 PM PDT 24
Peak memory 198020 kb
Host smart-fe7c9ff1-b0a9-4001-b4a8-fe976353147f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586870135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1586870135
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.994526562
Short name T579
Test name
Test status
Simulation time 172520201 ps
CPU time 3.7 seconds
Started Jul 01 04:49:39 PM PDT 24
Finished Jul 01 04:49:45 PM PDT 24
Peak memory 198696 kb
Host smart-bc54747c-c8fd-4bbc-a9d5-10daf4b358cd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994526562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.gpio_intr_with_filter_rand_intr_event.994526562
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.1950884685
Short name T245
Test name
Test status
Simulation time 114432021 ps
CPU time 2.56 seconds
Started Jul 01 04:49:41 PM PDT 24
Finished Jul 01 04:49:46 PM PDT 24
Peak memory 198772 kb
Host smart-183f3223-cfed-4e18-820e-fb1fc944f76d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950884685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.1950884685
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2001482120
Short name T342
Test name
Test status
Simulation time 67119226 ps
CPU time 0.68 seconds
Started Jul 01 04:49:39 PM PDT 24
Finished Jul 01 04:49:43 PM PDT 24
Peak memory 194968 kb
Host smart-c9afe8f2-5bed-49e3-8a14-4d13d4961f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001482120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2001482120
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.2801194305
Short name T409
Test name
Test status
Simulation time 16809956 ps
CPU time 0.75 seconds
Started Jul 01 04:49:37 PM PDT 24
Finished Jul 01 04:49:41 PM PDT 24
Peak memory 195964 kb
Host smart-ee8cae9a-36dd-4d83-aaaf-2402fd5a444e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801194305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.2801194305
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2926107783
Short name T467
Test name
Test status
Simulation time 397346451 ps
CPU time 1.53 seconds
Started Jul 01 04:49:37 PM PDT 24
Finished Jul 01 04:49:41 PM PDT 24
Peak memory 198792 kb
Host smart-33df08a7-bb90-4d5c-b25a-1f14d0025d46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926107783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2926107783
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.3208930595
Short name T254
Test name
Test status
Simulation time 62084685 ps
CPU time 0.74 seconds
Started Jul 01 04:49:41 PM PDT 24
Finished Jul 01 04:49:44 PM PDT 24
Peak memory 195880 kb
Host smart-445319a9-c971-4ecc-94df-9eb6d93c00ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208930595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.3208930595
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2865032999
Short name T381
Test name
Test status
Simulation time 39104809 ps
CPU time 1.1 seconds
Started Jul 01 04:49:38 PM PDT 24
Finished Jul 01 04:49:42 PM PDT 24
Peak memory 197172 kb
Host smart-cf121d85-d411-4f0e-b085-414e044ac35b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865032999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2865032999
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.3292867680
Short name T193
Test name
Test status
Simulation time 29197961828 ps
CPU time 194.16 seconds
Started Jul 01 04:49:35 PM PDT 24
Finished Jul 01 04:52:52 PM PDT 24
Peak memory 198744 kb
Host smart-49da64a6-f1ea-48a5-8f7c-3c4c9f0c3150
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292867680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.3292867680
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.1831593051
Short name T424
Test name
Test status
Simulation time 73071272908 ps
CPU time 1834.31 seconds
Started Jul 01 04:49:38 PM PDT 24
Finished Jul 01 05:20:15 PM PDT 24
Peak memory 198904 kb
Host smart-330ea505-351a-4d75-a8c4-3d5c96a806c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1831593051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.1831593051
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.3787464409
Short name T521
Test name
Test status
Simulation time 14690873 ps
CPU time 0.6 seconds
Started Jul 01 04:49:45 PM PDT 24
Finished Jul 01 04:49:49 PM PDT 24
Peak memory 195536 kb
Host smart-29f0d981-566f-48ff-82e7-74790f1d742d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787464409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3787464409
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1468984100
Short name T351
Test name
Test status
Simulation time 219724894 ps
CPU time 0.86 seconds
Started Jul 01 04:49:50 PM PDT 24
Finished Jul 01 04:49:53 PM PDT 24
Peak memory 195976 kb
Host smart-e4d61c93-8c5c-4e7b-a189-de4e38f1a1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468984100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1468984100
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.3090302734
Short name T253
Test name
Test status
Simulation time 382962604 ps
CPU time 20.19 seconds
Started Jul 01 04:49:45 PM PDT 24
Finished Jul 01 04:50:08 PM PDT 24
Peak memory 197808 kb
Host smart-e16561b1-1106-49a6-8a43-6e43b7fe5116
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090302734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.3090302734
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2004088457
Short name T508
Test name
Test status
Simulation time 73448422 ps
CPU time 0.93 seconds
Started Jul 01 04:49:45 PM PDT 24
Finished Jul 01 04:49:49 PM PDT 24
Peak memory 197864 kb
Host smart-7ae94ea5-3f42-4db7-a219-4110adc30ae0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004088457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2004088457
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.3120613584
Short name T263
Test name
Test status
Simulation time 48419562 ps
CPU time 1.04 seconds
Started Jul 01 04:49:45 PM PDT 24
Finished Jul 01 04:49:50 PM PDT 24
Peak memory 197324 kb
Host smart-f3e9957a-2f08-48c5-94dd-572acd5b2605
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120613584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.3120613584
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1498836179
Short name T267
Test name
Test status
Simulation time 54810735 ps
CPU time 2.5 seconds
Started Jul 01 04:49:45 PM PDT 24
Finished Jul 01 04:49:50 PM PDT 24
Peak memory 198720 kb
Host smart-948c271a-e84c-4e00-9fab-4b7040e2a0ec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498836179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1498836179
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1119441006
Short name T183
Test name
Test status
Simulation time 133807632 ps
CPU time 1.21 seconds
Started Jul 01 04:49:44 PM PDT 24
Finished Jul 01 04:49:48 PM PDT 24
Peak memory 197220 kb
Host smart-1bacf338-7cc5-43f8-9d91-f42983069005
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119441006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1119441006
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.4198396652
Short name T526
Test name
Test status
Simulation time 130403210 ps
CPU time 0.82 seconds
Started Jul 01 04:49:41 PM PDT 24
Finished Jul 01 04:49:45 PM PDT 24
Peak memory 197252 kb
Host smart-a850111a-6b68-4fb6-beb4-510c9372b15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198396652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.4198396652
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.4063664284
Short name T683
Test name
Test status
Simulation time 77929597 ps
CPU time 0.96 seconds
Started Jul 01 04:49:38 PM PDT 24
Finished Jul 01 04:49:42 PM PDT 24
Peak memory 197364 kb
Host smart-0eee78b4-ee52-418c-855d-8f4add835260
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063664284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.4063664284
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_smoke.4238990928
Short name T57
Test name
Test status
Simulation time 244669863 ps
CPU time 1.32 seconds
Started Jul 01 04:49:40 PM PDT 24
Finished Jul 01 04:49:44 PM PDT 24
Peak memory 197160 kb
Host smart-7def3679-9942-497e-bef7-3c6a6e064746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238990928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.4238990928
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2159847771
Short name T414
Test name
Test status
Simulation time 42521386 ps
CPU time 1.19 seconds
Started Jul 01 04:49:39 PM PDT 24
Finished Jul 01 04:49:43 PM PDT 24
Peak memory 197128 kb
Host smart-977f2af1-a885-4d91-ae37-c44e555ca0a5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159847771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2159847771
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.1199041921
Short name T380
Test name
Test status
Simulation time 21616739468 ps
CPU time 148.31 seconds
Started Jul 01 04:49:44 PM PDT 24
Finished Jul 01 04:52:15 PM PDT 24
Peak memory 198800 kb
Host smart-2e1face8-b9f4-4708-840d-c10b828eddbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199041921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.1199041921
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1687961284
Short name T376
Test name
Test status
Simulation time 28785088 ps
CPU time 0.62 seconds
Started Jul 01 04:49:43 PM PDT 24
Finished Jul 01 04:49:47 PM PDT 24
Peak memory 194624 kb
Host smart-7abf8414-79c9-4036-a24b-e590ed4005ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687961284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1687961284
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3243148923
Short name T604
Test name
Test status
Simulation time 269106425 ps
CPU time 0.69 seconds
Started Jul 01 04:49:43 PM PDT 24
Finished Jul 01 04:49:46 PM PDT 24
Peak memory 194896 kb
Host smart-81a4411c-60b8-4b6a-867a-7949e306f119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243148923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3243148923
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.4187788869
Short name T83
Test name
Test status
Simulation time 654018507 ps
CPU time 19.19 seconds
Started Jul 01 04:49:49 PM PDT 24
Finished Jul 01 04:50:11 PM PDT 24
Peak memory 198648 kb
Host smart-9eeab2df-4f6c-47b5-8acc-ccefd710dd57
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187788869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.4187788869
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2721059573
Short name T233
Test name
Test status
Simulation time 118880867 ps
CPU time 0.85 seconds
Started Jul 01 04:49:43 PM PDT 24
Finished Jul 01 04:49:47 PM PDT 24
Peak memory 197888 kb
Host smart-49a38651-497c-4431-b83a-3ec1e5c64a9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721059573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2721059573
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1039150133
Short name T118
Test name
Test status
Simulation time 197154471 ps
CPU time 1.11 seconds
Started Jul 01 04:49:43 PM PDT 24
Finished Jul 01 04:49:46 PM PDT 24
Peak memory 196688 kb
Host smart-a41edd53-f3c9-4686-b283-7d217911fd63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039150133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1039150133
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.223864759
Short name T223
Test name
Test status
Simulation time 78689471 ps
CPU time 3.08 seconds
Started Jul 01 04:49:53 PM PDT 24
Finished Jul 01 04:50:00 PM PDT 24
Peak memory 198672 kb
Host smart-f23beb12-7fb3-4cd9-97aa-855f1fb12ee0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223864759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.gpio_intr_with_filter_rand_intr_event.223864759
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.1059310830
Short name T32
Test name
Test status
Simulation time 325781165 ps
CPU time 2.57 seconds
Started Jul 01 04:49:46 PM PDT 24
Finished Jul 01 04:49:52 PM PDT 24
Peak memory 198696 kb
Host smart-755a95a2-43c6-43bc-ab66-52eefc028f60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059310830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.1059310830
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.971680195
Short name T124
Test name
Test status
Simulation time 295791296 ps
CPU time 0.85 seconds
Started Jul 01 04:49:44 PM PDT 24
Finished Jul 01 04:49:48 PM PDT 24
Peak memory 196584 kb
Host smart-0e72615a-a7a9-48c9-9153-5d36d4c3ec47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971680195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.971680195
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.704303628
Short name T76
Test name
Test status
Simulation time 128741345 ps
CPU time 0.91 seconds
Started Jul 01 04:49:44 PM PDT 24
Finished Jul 01 04:49:48 PM PDT 24
Peak memory 198000 kb
Host smart-c630d085-8207-498c-a278-a9c5bfe37a42
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704303628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup
_pulldown.704303628
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1533850767
Short name T675
Test name
Test status
Simulation time 90671764 ps
CPU time 1.81 seconds
Started Jul 01 04:49:46 PM PDT 24
Finished Jul 01 04:49:51 PM PDT 24
Peak memory 198620 kb
Host smart-d755b8c9-4f63-450d-af3f-86e3de5b1a19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533850767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.1533850767
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.4040299891
Short name T194
Test name
Test status
Simulation time 79693357 ps
CPU time 1.4 seconds
Started Jul 01 04:49:43 PM PDT 24
Finished Jul 01 04:49:47 PM PDT 24
Peak memory 197536 kb
Host smart-05f20868-0cdf-447d-9bf0-ad8b26294046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040299891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.4040299891
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.2710242158
Short name T68
Test name
Test status
Simulation time 50503150 ps
CPU time 0.95 seconds
Started Jul 01 04:49:42 PM PDT 24
Finished Jul 01 04:49:45 PM PDT 24
Peak memory 196576 kb
Host smart-c2a6f0b4-3dcb-4cc3-87d3-45286bdf28bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710242158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.2710242158
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.3977068768
Short name T251
Test name
Test status
Simulation time 18300928474 ps
CPU time 136.03 seconds
Started Jul 01 04:49:45 PM PDT 24
Finished Jul 01 04:52:04 PM PDT 24
Peak memory 198804 kb
Host smart-efd9e7c9-7c26-4984-b904-ef65e80830a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977068768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.3977068768
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.912734405
Short name T630
Test name
Test status
Simulation time 43587098 ps
CPU time 0.58 seconds
Started Jul 01 04:49:45 PM PDT 24
Finished Jul 01 04:49:49 PM PDT 24
Peak memory 195256 kb
Host smart-b00a74e4-6cb6-4bea-8a7b-1de148efb352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912734405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.912734405
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.370128950
Short name T313
Test name
Test status
Simulation time 86454327 ps
CPU time 0.86 seconds
Started Jul 01 04:49:49 PM PDT 24
Finished Jul 01 04:49:52 PM PDT 24
Peak memory 196396 kb
Host smart-d1f55539-9812-4ae7-8b67-caf52593cd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370128950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.370128950
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.3646049348
Short name T311
Test name
Test status
Simulation time 364789702 ps
CPU time 12.95 seconds
Started Jul 01 04:49:46 PM PDT 24
Finished Jul 01 04:50:02 PM PDT 24
Peak memory 197128 kb
Host smart-85e12dc9-3c28-475a-9911-995a6da5029e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646049348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.3646049348
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.1443265162
Short name T325
Test name
Test status
Simulation time 131451386 ps
CPU time 0.65 seconds
Started Jul 01 04:49:45 PM PDT 24
Finished Jul 01 04:49:50 PM PDT 24
Peak memory 194992 kb
Host smart-884e991f-fff2-408a-b059-e585bd6cd5e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443265162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.1443265162
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1307846121
Short name T394
Test name
Test status
Simulation time 43725568 ps
CPU time 1.23 seconds
Started Jul 01 04:49:45 PM PDT 24
Finished Jul 01 04:49:50 PM PDT 24
Peak memory 197640 kb
Host smart-88c28f3a-f367-45d9-972e-0a04e0449489
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307846121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1307846121
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1419990592
Short name T430
Test name
Test status
Simulation time 73625996 ps
CPU time 3 seconds
Started Jul 01 04:49:46 PM PDT 24
Finished Jul 01 04:49:52 PM PDT 24
Peak memory 197032 kb
Host smart-1cbba59f-b03b-4a4a-b849-be43ece4549b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419990592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1419990592
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3599955001
Short name T487
Test name
Test status
Simulation time 70126157 ps
CPU time 1.69 seconds
Started Jul 01 04:49:53 PM PDT 24
Finished Jul 01 04:49:59 PM PDT 24
Peak memory 196716 kb
Host smart-5468d137-df94-420e-866d-67f120da1455
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599955001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3599955001
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.2741835100
Short name T549
Test name
Test status
Simulation time 41154876 ps
CPU time 0.95 seconds
Started Jul 01 04:49:45 PM PDT 24
Finished Jul 01 04:49:49 PM PDT 24
Peak memory 197228 kb
Host smart-b3a309db-1475-4576-a769-6019d7d9a18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741835100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.2741835100
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1082344119
Short name T322
Test name
Test status
Simulation time 32207114 ps
CPU time 0.76 seconds
Started Jul 01 04:49:53 PM PDT 24
Finished Jul 01 04:49:58 PM PDT 24
Peak memory 196084 kb
Host smart-754cf223-3b9d-41de-a217-03d03dac707c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082344119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1082344119
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3161967031
Short name T218
Test name
Test status
Simulation time 354087350 ps
CPU time 4.75 seconds
Started Jul 01 04:49:47 PM PDT 24
Finished Jul 01 04:49:55 PM PDT 24
Peak memory 198632 kb
Host smart-5aef9e87-284b-44bb-907d-912527daecc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161967031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3161967031
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.3040067343
Short name T250
Test name
Test status
Simulation time 46439078 ps
CPU time 0.94 seconds
Started Jul 01 04:49:47 PM PDT 24
Finished Jul 01 04:49:52 PM PDT 24
Peak memory 195948 kb
Host smart-d1f00037-cf51-4cdf-8de0-37a8484a9682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040067343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.3040067343
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1368447486
Short name T591
Test name
Test status
Simulation time 69699337 ps
CPU time 1.33 seconds
Started Jul 01 04:49:44 PM PDT 24
Finished Jul 01 04:49:48 PM PDT 24
Peak memory 197440 kb
Host smart-369f9fb8-491d-434a-b7a3-2726b974b0be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368447486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1368447486
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1401470192
Short name T179
Test name
Test status
Simulation time 10813140742 ps
CPU time 131.78 seconds
Started Jul 01 04:49:46 PM PDT 24
Finished Jul 01 04:52:01 PM PDT 24
Peak memory 198744 kb
Host smart-73f13523-f350-4161-8c05-ea2bf5737060
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401470192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1401470192
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.684643721
Short name T74
Test name
Test status
Simulation time 98774828289 ps
CPU time 2324.41 seconds
Started Jul 01 04:49:50 PM PDT 24
Finished Jul 01 05:28:37 PM PDT 24
Peak memory 198904 kb
Host smart-761ca535-e9ac-40e3-b99c-9d55642d9646
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=684643721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.684643721
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2855814123
Short name T143
Test name
Test status
Simulation time 85408715 ps
CPU time 0.57 seconds
Started Jul 01 04:49:52 PM PDT 24
Finished Jul 01 04:49:55 PM PDT 24
Peak memory 194612 kb
Host smart-9f7b6b41-2628-4092-a9c1-003e48685146
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855814123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2855814123
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.1474606046
Short name T564
Test name
Test status
Simulation time 86272630 ps
CPU time 0.73 seconds
Started Jul 01 04:49:43 PM PDT 24
Finished Jul 01 04:49:47 PM PDT 24
Peak memory 195992 kb
Host smart-b99574b0-6c5e-4355-93a4-4d71340743c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474606046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.1474606046
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.717119545
Short name T619
Test name
Test status
Simulation time 594934519 ps
CPU time 17.54 seconds
Started Jul 01 04:49:53 PM PDT 24
Finished Jul 01 04:50:14 PM PDT 24
Peak memory 197216 kb
Host smart-611658e9-0bd0-4892-b3af-81007a6e9374
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717119545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stres
s.717119545
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.2898987788
Short name T276
Test name
Test status
Simulation time 54896626 ps
CPU time 0.9 seconds
Started Jul 01 04:49:52 PM PDT 24
Finished Jul 01 04:49:56 PM PDT 24
Peak memory 196448 kb
Host smart-9fed9cd8-ad81-48b9-a8d3-d23b70318506
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898987788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2898987788
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.1411627863
Short name T386
Test name
Test status
Simulation time 22329920 ps
CPU time 0.77 seconds
Started Jul 01 04:49:53 PM PDT 24
Finished Jul 01 04:49:58 PM PDT 24
Peak memory 196148 kb
Host smart-449c1d37-4534-4673-9ddc-e54e93e5a7bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411627863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.1411627863
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.450362817
Short name T568
Test name
Test status
Simulation time 64891170 ps
CPU time 2.62 seconds
Started Jul 01 04:49:53 PM PDT 24
Finished Jul 01 04:50:00 PM PDT 24
Peak memory 198708 kb
Host smart-6e388de5-979e-4848-bbfd-d63e73f79137
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450362817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.450362817
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.785765405
Short name T555
Test name
Test status
Simulation time 245076146 ps
CPU time 1.31 seconds
Started Jul 01 04:49:49 PM PDT 24
Finished Jul 01 04:49:53 PM PDT 24
Peak memory 198084 kb
Host smart-38f539bf-be45-4883-8ae5-fe4a4f0c322a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785765405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger.
785765405
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.1902658752
Short name T123
Test name
Test status
Simulation time 82523052 ps
CPU time 0.77 seconds
Started Jul 01 04:49:50 PM PDT 24
Finished Jul 01 04:49:53 PM PDT 24
Peak memory 196688 kb
Host smart-431379c0-33ad-4dd6-8018-c40621e96a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902658752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.1902658752
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.2368800835
Short name T69
Test name
Test status
Simulation time 80414332 ps
CPU time 0.85 seconds
Started Jul 01 04:49:46 PM PDT 24
Finished Jul 01 04:49:50 PM PDT 24
Peak memory 197976 kb
Host smart-07043cd6-bab0-4d9e-b119-50a826d580f5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368800835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.2368800835
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.4116059112
Short name T225
Test name
Test status
Simulation time 40836000 ps
CPU time 1.93 seconds
Started Jul 01 04:49:54 PM PDT 24
Finished Jul 01 04:50:00 PM PDT 24
Peak memory 198648 kb
Host smart-22a6b4f5-6cde-4ff9-a6b3-dc04b7f87c20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116059112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.4116059112
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3377244959
Short name T545
Test name
Test status
Simulation time 197786796 ps
CPU time 1.14 seconds
Started Jul 01 04:49:43 PM PDT 24
Finished Jul 01 04:49:46 PM PDT 24
Peak memory 196552 kb
Host smart-537a9383-cd9a-438b-8bf1-726d27d2fcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377244959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3377244959
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1510448268
Short name T428
Test name
Test status
Simulation time 33911369 ps
CPU time 0.7 seconds
Started Jul 01 04:49:53 PM PDT 24
Finished Jul 01 04:49:58 PM PDT 24
Peak memory 194804 kb
Host smart-528fe869-53ea-4ea3-8196-32536a8762d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510448268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1510448268
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3166550104
Short name T602
Test name
Test status
Simulation time 65956613242 ps
CPU time 168.16 seconds
Started Jul 01 04:49:53 PM PDT 24
Finished Jul 01 04:52:46 PM PDT 24
Peak memory 198780 kb
Host smart-6da00c48-e062-45d4-9620-7a32fbb40886
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166550104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3166550104
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.1391796846
Short name T65
Test name
Test status
Simulation time 153953827222 ps
CPU time 443.55 seconds
Started Jul 01 04:49:54 PM PDT 24
Finished Jul 01 04:57:22 PM PDT 24
Peak memory 198968 kb
Host smart-68287a09-3d3f-4da7-8a10-09daa23e1df7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1391796846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.1391796846
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1490966724
Short name T556
Test name
Test status
Simulation time 23628050 ps
CPU time 0.57 seconds
Started Jul 01 04:49:54 PM PDT 24
Finished Jul 01 04:49:59 PM PDT 24
Peak memory 194676 kb
Host smart-35484d64-ef31-4a9d-be4d-a3d61922c236
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490966724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1490966724
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2560070737
Short name T516
Test name
Test status
Simulation time 56648209 ps
CPU time 0.97 seconds
Started Jul 01 04:49:53 PM PDT 24
Finished Jul 01 04:49:58 PM PDT 24
Peak memory 196592 kb
Host smart-2c4ff8ee-5396-414d-8fa4-3507a96c48f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560070737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2560070737
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3601884500
Short name T155
Test name
Test status
Simulation time 3091085801 ps
CPU time 26.09 seconds
Started Jul 01 04:49:54 PM PDT 24
Finished Jul 01 04:50:25 PM PDT 24
Peak memory 197580 kb
Host smart-c280c34f-cb7c-489b-a890-dc0c1117ef11
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601884500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3601884500
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.3355432024
Short name T547
Test name
Test status
Simulation time 53943881 ps
CPU time 0.88 seconds
Started Jul 01 04:49:54 PM PDT 24
Finished Jul 01 04:49:59 PM PDT 24
Peak memory 196556 kb
Host smart-f19c63ed-3a84-438e-8b07-0a38a380148a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355432024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.3355432024
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.2305121099
Short name T207
Test name
Test status
Simulation time 93015258 ps
CPU time 1.25 seconds
Started Jul 01 04:49:55 PM PDT 24
Finished Jul 01 04:50:00 PM PDT 24
Peak memory 197788 kb
Host smart-270ef799-624f-41b7-a2f6-ffd4f1f81324
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305121099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.2305121099
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2478772912
Short name T116
Test name
Test status
Simulation time 523667031 ps
CPU time 2.47 seconds
Started Jul 01 04:49:52 PM PDT 24
Finished Jul 01 04:49:56 PM PDT 24
Peak memory 196916 kb
Host smart-531657ae-b749-4733-8b7f-33eea6d31541
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478772912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2478772912
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.2891340875
Short name T404
Test name
Test status
Simulation time 629134251 ps
CPU time 3.07 seconds
Started Jul 01 04:49:52 PM PDT 24
Finished Jul 01 04:49:58 PM PDT 24
Peak memory 197904 kb
Host smart-f77a2dce-5f61-4c8e-9447-c9317798003e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891340875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.2891340875
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.651725610
Short name T492
Test name
Test status
Simulation time 255629702 ps
CPU time 1.2 seconds
Started Jul 01 04:49:51 PM PDT 24
Finished Jul 01 04:49:54 PM PDT 24
Peak memory 197260 kb
Host smart-60a72f2e-2b6b-47c6-8b14-b2db3809ce2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651725610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.651725610
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.88147752
Short name T532
Test name
Test status
Simulation time 39155213 ps
CPU time 0.85 seconds
Started Jul 01 04:49:53 PM PDT 24
Finished Jul 01 04:49:57 PM PDT 24
Peak memory 197992 kb
Host smart-caba34fd-5b12-44a7-9dde-6cc3a33d46b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88147752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullup_
pulldown.88147752
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.4039951459
Short name T582
Test name
Test status
Simulation time 73030232 ps
CPU time 1.45 seconds
Started Jul 01 04:49:52 PM PDT 24
Finished Jul 01 04:49:57 PM PDT 24
Peak memory 198636 kb
Host smart-05e77497-0e3a-419d-b96b-02ce60219d02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039951459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.4039951459
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.283120585
Short name T423
Test name
Test status
Simulation time 82301637 ps
CPU time 1.41 seconds
Started Jul 01 04:49:51 PM PDT 24
Finished Jul 01 04:49:54 PM PDT 24
Peak memory 198672 kb
Host smart-ecfd1730-f69a-4cdb-83aa-94418a0ee9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283120585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.283120585
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.3216856071
Short name T528
Test name
Test status
Simulation time 219234477 ps
CPU time 1.17 seconds
Started Jul 01 04:49:54 PM PDT 24
Finished Jul 01 04:50:00 PM PDT 24
Peak memory 198596 kb
Host smart-38e77c9c-5bd0-441b-bb21-1535af950ac7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216856071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.3216856071
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3931157643
Short name T197
Test name
Test status
Simulation time 20630091645 ps
CPU time 139.56 seconds
Started Jul 01 04:49:52 PM PDT 24
Finished Jul 01 04:52:15 PM PDT 24
Peak memory 198796 kb
Host smart-5890bd84-0a97-4d8b-b492-f903bef03dda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931157643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3931157643
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.4255236832
Short name T648
Test name
Test status
Simulation time 41050059 ps
CPU time 0.56 seconds
Started Jul 01 04:48:30 PM PDT 24
Finished Jul 01 04:48:34 PM PDT 24
Peak memory 195352 kb
Host smart-fd11c7e9-0370-4b3d-a1ce-51d3b7352bd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255236832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.4255236832
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1824429739
Short name T362
Test name
Test status
Simulation time 380813661 ps
CPU time 0.97 seconds
Started Jul 01 04:48:27 PM PDT 24
Finished Jul 01 04:48:31 PM PDT 24
Peak memory 197348 kb
Host smart-c69b6b41-52af-44ea-a500-c34b4b888a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824429739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1824429739
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.65676284
Short name T364
Test name
Test status
Simulation time 242575336 ps
CPU time 8.6 seconds
Started Jul 01 04:48:29 PM PDT 24
Finished Jul 01 04:48:40 PM PDT 24
Peak memory 196900 kb
Host smart-205612c6-8d03-434e-8464-86841a9c7914
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65676284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stress.65676284
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.3974958781
Short name T607
Test name
Test status
Simulation time 43071147 ps
CPU time 0.65 seconds
Started Jul 01 04:48:29 PM PDT 24
Finished Jul 01 04:48:33 PM PDT 24
Peak memory 195864 kb
Host smart-1045cb25-f0df-4df7-aad3-f719a2ca72eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974958781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.3974958781
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.268490464
Short name T319
Test name
Test status
Simulation time 50151783 ps
CPU time 1.06 seconds
Started Jul 01 04:48:29 PM PDT 24
Finished Jul 01 04:48:33 PM PDT 24
Peak memory 196452 kb
Host smart-7c8c99c2-b67f-4a30-a165-8cc1657a07e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268490464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.268490464
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.269554554
Short name T171
Test name
Test status
Simulation time 243824570 ps
CPU time 2.6 seconds
Started Jul 01 04:48:28 PM PDT 24
Finished Jul 01 04:48:34 PM PDT 24
Peak memory 198720 kb
Host smart-ef487d88-3210-491b-81a2-6b28ef278650
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269554554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.269554554
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.4240895311
Short name T142
Test name
Test status
Simulation time 342303935 ps
CPU time 3.12 seconds
Started Jul 01 04:48:27 PM PDT 24
Finished Jul 01 04:48:33 PM PDT 24
Peak memory 197740 kb
Host smart-95ad1699-57eb-488a-8555-e9d4a2cd2ff8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240895311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
4240895311
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.1052654308
Short name T642
Test name
Test status
Simulation time 53629026 ps
CPU time 1.09 seconds
Started Jul 01 04:48:27 PM PDT 24
Finished Jul 01 04:48:31 PM PDT 24
Peak memory 196684 kb
Host smart-dc9af5cf-bda1-4f63-a867-35e624042b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052654308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.1052654308
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2968875930
Short name T170
Test name
Test status
Simulation time 47391089 ps
CPU time 1.04 seconds
Started Jul 01 04:48:29 PM PDT 24
Finished Jul 01 04:48:33 PM PDT 24
Peak memory 196456 kb
Host smart-a1497f20-8c47-4474-8b1d-d40020ac3e49
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968875930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2968875930
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2830505770
Short name T278
Test name
Test status
Simulation time 45438341 ps
CPU time 2.19 seconds
Started Jul 01 04:48:28 PM PDT 24
Finished Jul 01 04:48:33 PM PDT 24
Peak memory 198688 kb
Host smart-dbac7241-6b7e-42ef-a7a4-263d99c992b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830505770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.2830505770
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3264716851
Short name T51
Test name
Test status
Simulation time 711691154 ps
CPU time 0.92 seconds
Started Jul 01 04:48:37 PM PDT 24
Finished Jul 01 04:48:40 PM PDT 24
Peak memory 215416 kb
Host smart-55ad6a1c-886a-489a-ae16-7edd588ac4f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264716851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3264716851
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.388852883
Short name T524
Test name
Test status
Simulation time 59065035 ps
CPU time 1.1 seconds
Started Jul 01 04:48:29 PM PDT 24
Finished Jul 01 04:48:34 PM PDT 24
Peak memory 197240 kb
Host smart-b8a2274c-e039-4450-91da-7a11a3493a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388852883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.388852883
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.260173239
Short name T353
Test name
Test status
Simulation time 62285830 ps
CPU time 1.19 seconds
Started Jul 01 04:48:26 PM PDT 24
Finished Jul 01 04:48:29 PM PDT 24
Peak memory 196392 kb
Host smart-9d69aa3a-c36b-4fbc-a697-7a11b6e20a76
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260173239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.260173239
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.262897198
Short name T511
Test name
Test status
Simulation time 8862681048 ps
CPU time 53.94 seconds
Started Jul 01 04:48:35 PM PDT 24
Finished Jul 01 04:49:31 PM PDT 24
Peak memory 198808 kb
Host smart-07b190fe-3f48-4f84-a9dd-f2996dd9abc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262897198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gp
io_stress_all.262897198
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3015468819
Short name T240
Test name
Test status
Simulation time 15123690 ps
CPU time 0.59 seconds
Started Jul 01 04:49:54 PM PDT 24
Finished Jul 01 04:49:59 PM PDT 24
Peak memory 194664 kb
Host smart-e2e22120-9bdb-4edd-b323-9fae8dbc3fd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015468819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3015468819
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.2082146083
Short name T687
Test name
Test status
Simulation time 42514488 ps
CPU time 0.81 seconds
Started Jul 01 04:49:56 PM PDT 24
Finished Jul 01 04:50:01 PM PDT 24
Peak memory 196080 kb
Host smart-23d04979-c4ac-4649-bb7b-0e9c18f6d62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082146083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.2082146083
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.902222712
Short name T121
Test name
Test status
Simulation time 437413753 ps
CPU time 13.86 seconds
Started Jul 01 04:49:57 PM PDT 24
Finished Jul 01 04:50:15 PM PDT 24
Peak memory 196900 kb
Host smart-0889ebfe-809b-4cbe-943c-9061cf20f702
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902222712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres
s.902222712
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.298124369
Short name T475
Test name
Test status
Simulation time 27677537 ps
CPU time 0.58 seconds
Started Jul 01 04:49:55 PM PDT 24
Finished Jul 01 04:50:00 PM PDT 24
Peak memory 194856 kb
Host smart-22673e5d-e564-4e7f-85e7-ea66fee98a98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298124369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.298124369
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1259091164
Short name T682
Test name
Test status
Simulation time 65298530 ps
CPU time 1.18 seconds
Started Jul 01 04:49:53 PM PDT 24
Finished Jul 01 04:49:57 PM PDT 24
Peak memory 196644 kb
Host smart-ba9f03a9-3b9d-49f2-bce9-ff1f0e6f1767
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259091164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1259091164
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.1785356991
Short name T558
Test name
Test status
Simulation time 164028346 ps
CPU time 3.65 seconds
Started Jul 01 04:49:54 PM PDT 24
Finished Jul 01 04:50:02 PM PDT 24
Peak memory 198788 kb
Host smart-56914329-8510-4cdf-9dfe-c3e07c7326ff
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785356991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.1785356991
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.931306356
Short name T455
Test name
Test status
Simulation time 574857433 ps
CPU time 2.93 seconds
Started Jul 01 04:49:56 PM PDT 24
Finished Jul 01 04:50:03 PM PDT 24
Peak memory 198728 kb
Host smart-1ccf8e79-ca07-478b-9c32-71f3b1c03c10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931306356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.
931306356
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1458014235
Short name T324
Test name
Test status
Simulation time 41628779 ps
CPU time 0.71 seconds
Started Jul 01 04:49:54 PM PDT 24
Finished Jul 01 04:49:59 PM PDT 24
Peak memory 195644 kb
Host smart-b259c88b-fc8c-4107-9798-daba538cb127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458014235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1458014235
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.1224245021
Short name T126
Test name
Test status
Simulation time 36469229 ps
CPU time 0.89 seconds
Started Jul 01 04:49:56 PM PDT 24
Finished Jul 01 04:50:02 PM PDT 24
Peak memory 196600 kb
Host smart-2d02df6c-1fcb-4cc1-82c9-be835e70daf5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224245021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.1224245021
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2851323558
Short name T706
Test name
Test status
Simulation time 266910880 ps
CPU time 3.04 seconds
Started Jul 01 04:49:55 PM PDT 24
Finished Jul 01 04:50:02 PM PDT 24
Peak memory 198628 kb
Host smart-9a3633f6-a369-40cd-a882-5ac6587a385d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851323558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2851323558
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2978841205
Short name T710
Test name
Test status
Simulation time 81793088 ps
CPU time 0.88 seconds
Started Jul 01 04:49:56 PM PDT 24
Finished Jul 01 04:50:01 PM PDT 24
Peak memory 196032 kb
Host smart-f042ba52-fcd5-4409-a3c0-c62b180acc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978841205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2978841205
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.1624025299
Short name T575
Test name
Test status
Simulation time 75246657 ps
CPU time 1.14 seconds
Started Jul 01 04:49:52 PM PDT 24
Finished Jul 01 04:49:57 PM PDT 24
Peak memory 196404 kb
Host smart-e991d373-25eb-4a68-90ae-f7f3f60863e1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624025299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.1624025299
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.1995313104
Short name T560
Test name
Test status
Simulation time 19755897203 ps
CPU time 70.43 seconds
Started Jul 01 04:49:54 PM PDT 24
Finished Jul 01 04:51:09 PM PDT 24
Peak memory 198804 kb
Host smart-ec08a271-0c94-47c7-b07d-4c78d009d2f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995313104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.1995313104
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2875524957
Short name T321
Test name
Test status
Simulation time 14083433 ps
CPU time 0.59 seconds
Started Jul 01 04:49:59 PM PDT 24
Finished Jul 01 04:50:03 PM PDT 24
Peak memory 194864 kb
Host smart-28bac1ec-08d9-422e-8017-316990c8e7cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875524957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2875524957
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.440509160
Short name T694
Test name
Test status
Simulation time 108565562 ps
CPU time 0.73 seconds
Started Jul 01 04:49:54 PM PDT 24
Finished Jul 01 04:49:59 PM PDT 24
Peak memory 195936 kb
Host smart-21deefd5-0857-4b8a-8028-46a0ce09d4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440509160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.440509160
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.1138247586
Short name T82
Test name
Test status
Simulation time 686730963 ps
CPU time 5.91 seconds
Started Jul 01 04:49:55 PM PDT 24
Finished Jul 01 04:50:06 PM PDT 24
Peak memory 197204 kb
Host smart-9c59eed9-e2f3-4495-ab54-9c5e0440af7f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138247586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.1138247586
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.127198235
Short name T309
Test name
Test status
Simulation time 60874026 ps
CPU time 0.9 seconds
Started Jul 01 04:50:02 PM PDT 24
Finished Jul 01 04:50:06 PM PDT 24
Peak memory 196660 kb
Host smart-9fca138d-b919-463d-b25c-fa6a146499ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127198235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.127198235
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2098402418
Short name T372
Test name
Test status
Simulation time 156940889 ps
CPU time 1.16 seconds
Started Jul 01 04:49:54 PM PDT 24
Finished Jul 01 04:50:00 PM PDT 24
Peak memory 196632 kb
Host smart-b25b6f32-7e37-4d0c-bf84-c5fb680d8b84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098402418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2098402418
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3043426630
Short name T437
Test name
Test status
Simulation time 250837620 ps
CPU time 2.55 seconds
Started Jul 01 04:49:52 PM PDT 24
Finished Jul 01 04:49:57 PM PDT 24
Peak memory 198740 kb
Host smart-05df9ede-ceb6-4235-9c0e-ca4b8ce52e8d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043426630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.3043426630
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3607177738
Short name T660
Test name
Test status
Simulation time 103087905 ps
CPU time 2.9 seconds
Started Jul 01 04:49:53 PM PDT 24
Finished Jul 01 04:50:00 PM PDT 24
Peak memory 196532 kb
Host smart-cdf362c4-7caf-415d-8230-660ced0105d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607177738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3607177738
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.4039188295
Short name T609
Test name
Test status
Simulation time 26145343 ps
CPU time 0.96 seconds
Started Jul 01 04:49:54 PM PDT 24
Finished Jul 01 04:49:59 PM PDT 24
Peak memory 196712 kb
Host smart-a7fced4d-949f-44ad-a0af-cab6ddf5ab1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039188295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.4039188295
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2012039569
Short name T203
Test name
Test status
Simulation time 29987888 ps
CPU time 0.88 seconds
Started Jul 01 04:49:56 PM PDT 24
Finished Jul 01 04:50:01 PM PDT 24
Peak memory 196704 kb
Host smart-51f7b751-91c9-481c-b1e4-f5ce79736522
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012039569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.2012039569
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.548627816
Short name T570
Test name
Test status
Simulation time 407617925 ps
CPU time 5.78 seconds
Started Jul 01 04:49:53 PM PDT 24
Finished Jul 01 04:50:02 PM PDT 24
Peak memory 198632 kb
Host smart-043aaeb8-a151-4870-a772-0d7fddd53f82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548627816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ran
dom_long_reg_writes_reg_reads.548627816
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.3277473825
Short name T645
Test name
Test status
Simulation time 130039292 ps
CPU time 1.35 seconds
Started Jul 01 04:49:56 PM PDT 24
Finished Jul 01 04:50:02 PM PDT 24
Peak memory 197496 kb
Host smart-81b20108-a098-49fa-a033-e0fcd21e7a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277473825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.3277473825
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3669466584
Short name T269
Test name
Test status
Simulation time 62510408 ps
CPU time 1.01 seconds
Started Jul 01 04:49:56 PM PDT 24
Finished Jul 01 04:50:02 PM PDT 24
Peak memory 196532 kb
Host smart-8f970a77-e984-4e36-8d3d-00839df7db3a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669466584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3669466584
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.224805891
Short name T392
Test name
Test status
Simulation time 5198347264 ps
CPU time 70.13 seconds
Started Jul 01 04:50:00 PM PDT 24
Finished Jul 01 04:51:14 PM PDT 24
Peak memory 198792 kb
Host smart-08c3e324-6cda-4cf7-84f3-69a64624807f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224805891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.g
pio_stress_all.224805891
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2198460613
Short name T501
Test name
Test status
Simulation time 121421092 ps
CPU time 0.63 seconds
Started Jul 01 04:50:00 PM PDT 24
Finished Jul 01 04:50:04 PM PDT 24
Peak memory 195328 kb
Host smart-3934f7f2-a3fd-428f-8bba-8133f8f8cf6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198460613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2198460613
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3895455040
Short name T265
Test name
Test status
Simulation time 29542885 ps
CPU time 0.77 seconds
Started Jul 01 04:50:02 PM PDT 24
Finished Jul 01 04:50:07 PM PDT 24
Peak memory 195948 kb
Host smart-40bda6cc-18db-4d56-8ff5-dd14243201d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895455040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3895455040
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2711315115
Short name T551
Test name
Test status
Simulation time 1794566650 ps
CPU time 23.64 seconds
Started Jul 01 04:50:00 PM PDT 24
Finished Jul 01 04:50:28 PM PDT 24
Peak memory 198676 kb
Host smart-2cf001e6-53c8-496b-8484-c347554cbb72
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711315115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2711315115
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.4200473257
Short name T383
Test name
Test status
Simulation time 67957854 ps
CPU time 0.99 seconds
Started Jul 01 04:50:03 PM PDT 24
Finished Jul 01 04:50:08 PM PDT 24
Peak memory 197532 kb
Host smart-0ba18b6c-d270-407b-9a23-1f10541c2ea1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200473257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.4200473257
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.879050670
Short name T451
Test name
Test status
Simulation time 53543022 ps
CPU time 0.99 seconds
Started Jul 01 04:50:00 PM PDT 24
Finished Jul 01 04:50:05 PM PDT 24
Peak memory 197536 kb
Host smart-1e8741bb-137f-4864-b9b6-6f56b6ac186f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879050670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.879050670
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.1379304213
Short name T256
Test name
Test status
Simulation time 252843329 ps
CPU time 2.77 seconds
Started Jul 01 04:50:02 PM PDT 24
Finished Jul 01 04:50:08 PM PDT 24
Peak memory 198608 kb
Host smart-7975fb7c-0b62-46d5-a587-b4d2cc94dde7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379304213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.1379304213
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.22380938
Short name T315
Test name
Test status
Simulation time 372542376 ps
CPU time 3.03 seconds
Started Jul 01 04:50:04 PM PDT 24
Finished Jul 01 04:50:11 PM PDT 24
Peak memory 198672 kb
Host smart-025691c9-3aa2-4c31-a2d3-c16e7199af67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22380938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.22380938
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3224942999
Short name T433
Test name
Test status
Simulation time 249400622 ps
CPU time 0.88 seconds
Started Jul 01 04:50:03 PM PDT 24
Finished Jul 01 04:50:07 PM PDT 24
Peak memory 196708 kb
Host smart-ea115321-785e-4ff7-bb20-18987355cdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224942999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3224942999
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1458183320
Short name T578
Test name
Test status
Simulation time 229368641 ps
CPU time 1.12 seconds
Started Jul 01 04:50:03 PM PDT 24
Finished Jul 01 04:50:08 PM PDT 24
Peak memory 196500 kb
Host smart-43a79893-08e4-45cd-960f-153ebd743176
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458183320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1458183320
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3727430201
Short name T382
Test name
Test status
Simulation time 482054065 ps
CPU time 1.91 seconds
Started Jul 01 04:50:04 PM PDT 24
Finished Jul 01 04:50:10 PM PDT 24
Peak memory 198560 kb
Host smart-a13645c3-96dc-4239-a5a8-88cce299ae52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727430201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3727430201
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.1088694136
Short name T542
Test name
Test status
Simulation time 51305728 ps
CPU time 1.32 seconds
Started Jul 01 04:50:05 PM PDT 24
Finished Jul 01 04:50:10 PM PDT 24
Peak memory 198684 kb
Host smart-7ef5cdf9-e695-460c-a4d8-f33a0f57e52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088694136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.1088694136
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.1770948036
Short name T387
Test name
Test status
Simulation time 158840849 ps
CPU time 1.15 seconds
Started Jul 01 04:50:01 PM PDT 24
Finished Jul 01 04:50:06 PM PDT 24
Peak memory 196524 kb
Host smart-b5d13ad8-db9a-4e0e-b6e8-e63077b261b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770948036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.1770948036
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.2501381861
Short name T472
Test name
Test status
Simulation time 8806090143 ps
CPU time 43.14 seconds
Started Jul 01 04:49:59 PM PDT 24
Finished Jul 01 04:50:46 PM PDT 24
Peak memory 198804 kb
Host smart-d0a788b6-fe12-4a89-a0e3-c6ecdadb412c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501381861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.2501381861
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.2169916808
Short name T504
Test name
Test status
Simulation time 64723659 ps
CPU time 0.55 seconds
Started Jul 01 04:50:00 PM PDT 24
Finished Jul 01 04:50:04 PM PDT 24
Peak memory 194664 kb
Host smart-68e80ace-1af3-4916-87bc-698fc2bff343
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169916808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2169916808
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2716907256
Short name T125
Test name
Test status
Simulation time 20509493 ps
CPU time 0.77 seconds
Started Jul 01 04:50:04 PM PDT 24
Finished Jul 01 04:50:09 PM PDT 24
Peak memory 195232 kb
Host smart-bb7911c3-80cc-4ec0-9cc2-4b9676ae1711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716907256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2716907256
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.3750271677
Short name T479
Test name
Test status
Simulation time 429084484 ps
CPU time 21.03 seconds
Started Jul 01 04:50:02 PM PDT 24
Finished Jul 01 04:50:26 PM PDT 24
Peak memory 197544 kb
Host smart-83c92202-7042-495d-a463-e380a2672660
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750271677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.3750271677
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.4247655553
Short name T561
Test name
Test status
Simulation time 74958990 ps
CPU time 0.6 seconds
Started Jul 01 04:49:59 PM PDT 24
Finished Jul 01 04:50:03 PM PDT 24
Peak memory 195180 kb
Host smart-2e4a3688-ecd0-4a40-be03-92e14f3dc59e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247655553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.4247655553
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.3254822082
Short name T580
Test name
Test status
Simulation time 204489857 ps
CPU time 1.42 seconds
Started Jul 01 04:50:04 PM PDT 24
Finished Jul 01 04:50:10 PM PDT 24
Peak memory 196916 kb
Host smart-c0bbeb99-7b83-4ea0-a670-bc65be49ff87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254822082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.3254822082
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.1293496773
Short name T572
Test name
Test status
Simulation time 43104537 ps
CPU time 1.77 seconds
Started Jul 01 04:50:00 PM PDT 24
Finished Jul 01 04:50:06 PM PDT 24
Peak memory 198772 kb
Host smart-74d33cf8-7243-42bd-beb8-34472660d7c9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293496773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.1293496773
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.1108566932
Short name T198
Test name
Test status
Simulation time 167060999 ps
CPU time 3.19 seconds
Started Jul 01 04:50:04 PM PDT 24
Finished Jul 01 04:50:12 PM PDT 24
Peak memory 198676 kb
Host smart-99ea30b7-a733-480a-9cec-9d687715df8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108566932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.1108566932
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2650642600
Short name T643
Test name
Test status
Simulation time 193998491 ps
CPU time 0.88 seconds
Started Jul 01 04:49:59 PM PDT 24
Finished Jul 01 04:50:04 PM PDT 24
Peak memory 197204 kb
Host smart-c919361b-b910-4e1e-be0e-e6254c61e751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650642600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2650642600
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2583901804
Short name T554
Test name
Test status
Simulation time 58327129 ps
CPU time 1.18 seconds
Started Jul 01 04:50:02 PM PDT 24
Finished Jul 01 04:50:07 PM PDT 24
Peak memory 196524 kb
Host smart-f2b0385b-2dec-47f8-b00b-dcdd88cff8b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583901804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2583901804
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2157469955
Short name T302
Test name
Test status
Simulation time 592504839 ps
CPU time 4.63 seconds
Started Jul 01 04:50:02 PM PDT 24
Finished Jul 01 04:50:11 PM PDT 24
Peak memory 198736 kb
Host smart-2296c2ed-8934-48fb-a66f-0cdea4f7ed2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157469955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2157469955
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.3002405484
Short name T397
Test name
Test status
Simulation time 150806990 ps
CPU time 1.24 seconds
Started Jul 01 04:50:01 PM PDT 24
Finished Jul 01 04:50:06 PM PDT 24
Peak memory 196504 kb
Host smart-b174f592-ea75-4d7f-a4f9-4b766d7b13d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002405484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.3002405484
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.307950748
Short name T616
Test name
Test status
Simulation time 139106924 ps
CPU time 0.83 seconds
Started Jul 01 04:50:00 PM PDT 24
Finished Jul 01 04:50:05 PM PDT 24
Peak memory 195928 kb
Host smart-741ffd02-c5f6-4dba-8c71-24b0c0860751
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307950748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.307950748
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.3493731599
Short name T153
Test name
Test status
Simulation time 16827824850 ps
CPU time 135.78 seconds
Started Jul 01 04:50:01 PM PDT 24
Finished Jul 01 04:52:20 PM PDT 24
Peak memory 198856 kb
Host smart-9c69ca21-b84f-4c92-9393-681806a3e7f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493731599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.3493731599
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.3079929570
Short name T495
Test name
Test status
Simulation time 203091709666 ps
CPU time 1270.98 seconds
Started Jul 01 04:49:59 PM PDT 24
Finished Jul 01 05:11:14 PM PDT 24
Peak memory 198936 kb
Host smart-9606fba7-9bfd-4f52-b075-8360a78fc891
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3079929570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.3079929570
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1973074070
Short name T215
Test name
Test status
Simulation time 21074502 ps
CPU time 0.64 seconds
Started Jul 01 04:50:06 PM PDT 24
Finished Jul 01 04:50:11 PM PDT 24
Peak memory 194848 kb
Host smart-d956796c-19b9-4830-9242-ffa8a3dc1aee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973074070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1973074070
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1917714974
Short name T290
Test name
Test status
Simulation time 100747942 ps
CPU time 0.68 seconds
Started Jul 01 04:50:00 PM PDT 24
Finished Jul 01 04:50:04 PM PDT 24
Peak memory 194684 kb
Host smart-1e4e063f-34c6-459c-9290-73e114f3e91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917714974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1917714974
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.1402263435
Short name T357
Test name
Test status
Simulation time 749515280 ps
CPU time 5.61 seconds
Started Jul 01 04:50:05 PM PDT 24
Finished Jul 01 04:50:14 PM PDT 24
Peak memory 196208 kb
Host smart-f30f0504-a925-4bbc-8c6d-b0e28fc46de9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402263435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.1402263435
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.1188476105
Short name T115
Test name
Test status
Simulation time 75404000 ps
CPU time 1.02 seconds
Started Jul 01 04:50:02 PM PDT 24
Finished Jul 01 04:50:07 PM PDT 24
Peak memory 197160 kb
Host smart-dab6f625-04e1-4ecc-8d96-d25c5413893e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188476105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1188476105
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.2857498582
Short name T443
Test name
Test status
Simulation time 106840682 ps
CPU time 1.03 seconds
Started Jul 01 04:50:06 PM PDT 24
Finished Jul 01 04:50:10 PM PDT 24
Peak memory 196512 kb
Host smart-39c215be-b15b-4306-a301-35a3f340c5df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857498582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.2857498582
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.195394818
Short name T486
Test name
Test status
Simulation time 30742597 ps
CPU time 1.21 seconds
Started Jul 01 04:50:03 PM PDT 24
Finished Jul 01 04:50:09 PM PDT 24
Peak memory 197112 kb
Host smart-f972f965-27c4-41b2-82ec-6d037c88af41
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195394818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.gpio_intr_with_filter_rand_intr_event.195394818
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.3212985800
Short name T141
Test name
Test status
Simulation time 73064858 ps
CPU time 1.22 seconds
Started Jul 01 04:49:58 PM PDT 24
Finished Jul 01 04:50:03 PM PDT 24
Peak memory 197432 kb
Host smart-1ca673ea-ea89-46b3-80c7-7c8d1e9443c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212985800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.3212985800
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.4026995458
Short name T649
Test name
Test status
Simulation time 48198388 ps
CPU time 1.13 seconds
Started Jul 01 04:50:02 PM PDT 24
Finished Jul 01 04:50:07 PM PDT 24
Peak memory 196844 kb
Host smart-8827ac46-abfc-4556-b21b-1baac9bf4a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026995458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.4026995458
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.2287481581
Short name T213
Test name
Test status
Simulation time 31669870 ps
CPU time 1.2 seconds
Started Jul 01 04:50:00 PM PDT 24
Finished Jul 01 04:50:04 PM PDT 24
Peak memory 197724 kb
Host smart-b665d60c-44c4-47e2-a6ab-8df529c8b2df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287481581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.2287481581
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.95469529
Short name T672
Test name
Test status
Simulation time 97719772 ps
CPU time 1.23 seconds
Started Jul 01 04:50:03 PM PDT 24
Finished Jul 01 04:50:09 PM PDT 24
Peak memory 198616 kb
Host smart-ab4848f5-93fa-490f-aeb9-c59022cc1ecf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95469529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand
om_long_reg_writes_reg_reads.95469529
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.2386235597
Short name T703
Test name
Test status
Simulation time 89319035 ps
CPU time 1.02 seconds
Started Jul 01 04:50:02 PM PDT 24
Finished Jul 01 04:50:07 PM PDT 24
Peak memory 196584 kb
Host smart-3aca36c8-beaf-49f6-9694-d6273e13c369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386235597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.2386235597
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3381983848
Short name T172
Test name
Test status
Simulation time 163139705 ps
CPU time 1.15 seconds
Started Jul 01 04:50:03 PM PDT 24
Finished Jul 01 04:50:09 PM PDT 24
Peak memory 196208 kb
Host smart-fa3a0497-e015-41b6-a040-15c0e5b486f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381983848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3381983848
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.590082481
Short name T344
Test name
Test status
Simulation time 76865666071 ps
CPU time 181.61 seconds
Started Jul 01 04:50:03 PM PDT 24
Finished Jul 01 04:53:09 PM PDT 24
Peak memory 198776 kb
Host smart-fe30b0ae-5223-46dd-a14c-0c2d874e0657
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590082481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.590082481
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.2322846360
Short name T583
Test name
Test status
Simulation time 21017553650 ps
CPU time 492.81 seconds
Started Jul 01 04:50:06 PM PDT 24
Finished Jul 01 04:58:23 PM PDT 24
Peak memory 198904 kb
Host smart-62e81da4-684f-4364-9163-320bbfdeed8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2322846360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.2322846360
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2304941336
Short name T722
Test name
Test status
Simulation time 15097370 ps
CPU time 0.59 seconds
Started Jul 01 04:50:09 PM PDT 24
Finished Jul 01 04:50:14 PM PDT 24
Peak memory 194524 kb
Host smart-29a7ebc6-86c9-4f94-853e-95ce7b8cc5a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304941336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2304941336
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.1457292878
Short name T199
Test name
Test status
Simulation time 39625561 ps
CPU time 0.88 seconds
Started Jul 01 04:50:05 PM PDT 24
Finished Jul 01 04:50:10 PM PDT 24
Peak memory 196084 kb
Host smart-d52aeecd-f28b-469d-b584-c13059c752a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457292878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.1457292878
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.3148492784
Short name T720
Test name
Test status
Simulation time 686906609 ps
CPU time 9.55 seconds
Started Jul 01 04:50:03 PM PDT 24
Finished Jul 01 04:50:16 PM PDT 24
Peak memory 197536 kb
Host smart-ee563112-8077-4db5-8f43-a4be9c510e60
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148492784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.3148492784
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1064905805
Short name T235
Test name
Test status
Simulation time 134861996 ps
CPU time 1.21 seconds
Started Jul 01 04:50:05 PM PDT 24
Finished Jul 01 04:50:10 PM PDT 24
Peak memory 197196 kb
Host smart-1e8535ce-4e56-4e0e-a078-719139e08609
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064905805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1064905805
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.3822297393
Short name T589
Test name
Test status
Simulation time 526078114 ps
CPU time 3.63 seconds
Started Jul 01 04:50:05 PM PDT 24
Finished Jul 01 04:50:12 PM PDT 24
Peak memory 198740 kb
Host smart-8341df05-25aa-423a-89c4-28ce81cfcaff
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822297393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.3822297393
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.2867064989
Short name T559
Test name
Test status
Simulation time 230373850 ps
CPU time 1.63 seconds
Started Jul 01 04:50:03 PM PDT 24
Finished Jul 01 04:50:09 PM PDT 24
Peak memory 196832 kb
Host smart-c1d4fb32-083e-4433-bff4-ceb5bbac01af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867064989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.2867064989
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1330554052
Short name T129
Test name
Test status
Simulation time 37244155 ps
CPU time 1.13 seconds
Started Jul 01 04:50:03 PM PDT 24
Finished Jul 01 04:50:08 PM PDT 24
Peak memory 197248 kb
Host smart-364f2534-e45f-4573-b4dc-4fe8abf76d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330554052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1330554052
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3899755323
Short name T444
Test name
Test status
Simulation time 31442570 ps
CPU time 0.76 seconds
Started Jul 01 04:50:03 PM PDT 24
Finished Jul 01 04:50:08 PM PDT 24
Peak memory 196100 kb
Host smart-6358801b-2dd8-48e1-b3ac-98b82098db25
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899755323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.3899755323
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2234011715
Short name T396
Test name
Test status
Simulation time 88943967 ps
CPU time 2.24 seconds
Started Jul 01 04:50:05 PM PDT 24
Finished Jul 01 04:50:11 PM PDT 24
Peak memory 198664 kb
Host smart-8ec447d4-a24b-4b45-9267-2eb2d4f0e440
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234011715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2234011715
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.2839623076
Short name T507
Test name
Test status
Simulation time 88150269 ps
CPU time 0.69 seconds
Started Jul 01 04:50:05 PM PDT 24
Finished Jul 01 04:50:09 PM PDT 24
Peak memory 195492 kb
Host smart-5e11e9ca-f3ee-46ea-8077-ef9de9b14d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839623076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2839623076
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.507713665
Short name T425
Test name
Test status
Simulation time 49022980 ps
CPU time 0.93 seconds
Started Jul 01 04:50:03 PM PDT 24
Finished Jul 01 04:50:07 PM PDT 24
Peak memory 196044 kb
Host smart-4f7d95d3-aebe-4062-b03a-f0c569be0979
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507713665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.507713665
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1042534483
Short name T234
Test name
Test status
Simulation time 2464996873 ps
CPU time 58.47 seconds
Started Jul 01 04:50:01 PM PDT 24
Finished Jul 01 04:51:03 PM PDT 24
Peak memory 198760 kb
Host smart-5503a1b3-8887-4d17-bba0-480757ab33db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042534483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1042534483
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.3496460875
Short name T64
Test name
Test status
Simulation time 200209238807 ps
CPU time 847 seconds
Started Jul 01 04:50:09 PM PDT 24
Finished Jul 01 05:04:20 PM PDT 24
Peak memory 198920 kb
Host smart-903b1d4b-3b26-4051-b8c0-fd772f170458
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3496460875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.3496460875
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2710823844
Short name T293
Test name
Test status
Simulation time 36788531 ps
CPU time 0.63 seconds
Started Jul 01 04:50:07 PM PDT 24
Finished Jul 01 04:50:11 PM PDT 24
Peak memory 194652 kb
Host smart-a96fbe3f-1a82-4f8a-b52a-8460383eee05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710823844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2710823844
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1239619340
Short name T338
Test name
Test status
Simulation time 165620598 ps
CPU time 0.89 seconds
Started Jul 01 04:50:09 PM PDT 24
Finished Jul 01 04:50:13 PM PDT 24
Peak memory 197000 kb
Host smart-846f7c96-7cf5-42ab-bd7a-5d92e326983c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239619340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1239619340
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.2548491769
Short name T679
Test name
Test status
Simulation time 852044783 ps
CPU time 12.25 seconds
Started Jul 01 04:50:10 PM PDT 24
Finished Jul 01 04:50:26 PM PDT 24
Peak memory 196956 kb
Host smart-1acb84c8-917a-4d63-bbb9-f723838ce448
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548491769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.2548491769
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.1168806700
Short name T543
Test name
Test status
Simulation time 74207019 ps
CPU time 0.79 seconds
Started Jul 01 04:50:08 PM PDT 24
Finished Jul 01 04:50:13 PM PDT 24
Peak memory 197192 kb
Host smart-018f6d1e-920d-4b89-a1dc-cac95ec4d53c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168806700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.1168806700
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.3508209327
Short name T712
Test name
Test status
Simulation time 131446282 ps
CPU time 1.09 seconds
Started Jul 01 04:50:09 PM PDT 24
Finished Jul 01 04:50:14 PM PDT 24
Peak memory 197156 kb
Host smart-17a42203-efc7-4760-a771-30ef0de6e172
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508209327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.3508209327
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.484664726
Short name T134
Test name
Test status
Simulation time 161894670 ps
CPU time 1.76 seconds
Started Jul 01 04:50:12 PM PDT 24
Finished Jul 01 04:50:17 PM PDT 24
Peak memory 198652 kb
Host smart-7e548f53-9e39-438f-a55e-7993edce4f35
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484664726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.gpio_intr_with_filter_rand_intr_event.484664726
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.1984324592
Short name T527
Test name
Test status
Simulation time 286018818 ps
CPU time 1.11 seconds
Started Jul 01 04:50:09 PM PDT 24
Finished Jul 01 04:50:14 PM PDT 24
Peak memory 196416 kb
Host smart-c293e6e8-54e1-4303-8c0c-bd0e84357c9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984324592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.1984324592
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3007697937
Short name T229
Test name
Test status
Simulation time 303897143 ps
CPU time 1.46 seconds
Started Jul 01 04:50:09 PM PDT 24
Finished Jul 01 04:50:14 PM PDT 24
Peak memory 197652 kb
Host smart-3da15576-16ca-441b-8b49-dcd625b9a25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007697937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3007697937
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2210707487
Short name T427
Test name
Test status
Simulation time 36856179 ps
CPU time 0.76 seconds
Started Jul 01 04:50:08 PM PDT 24
Finished Jul 01 04:50:12 PM PDT 24
Peak memory 196152 kb
Host smart-07f7c277-b54b-4060-87cc-80c4bf9a08be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210707487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2210707487
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3180538881
Short name T277
Test name
Test status
Simulation time 119866298 ps
CPU time 1.89 seconds
Started Jul 01 04:50:13 PM PDT 24
Finished Jul 01 04:50:18 PM PDT 24
Peak memory 198736 kb
Host smart-903205d1-dc3c-40ee-80ce-8009c902b7c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180538881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3180538881
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.439189594
Short name T721
Test name
Test status
Simulation time 186158897 ps
CPU time 1.3 seconds
Started Jul 01 04:50:07 PM PDT 24
Finished Jul 01 04:50:12 PM PDT 24
Peak memory 197400 kb
Host smart-05f2828d-b12d-4e0b-8664-6ac6968bbd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439189594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.439189594
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.3543027848
Short name T494
Test name
Test status
Simulation time 853584226 ps
CPU time 1.28 seconds
Started Jul 01 04:50:09 PM PDT 24
Finished Jul 01 04:50:15 PM PDT 24
Peak memory 196784 kb
Host smart-636ab1ca-b255-4d04-a7ef-eaa36c0104ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543027848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.3543027848
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1412928342
Short name T373
Test name
Test status
Simulation time 2632033164 ps
CPU time 60.48 seconds
Started Jul 01 04:50:09 PM PDT 24
Finished Jul 01 04:51:13 PM PDT 24
Peak memory 198772 kb
Host smart-3cdd4300-2bb2-4cde-8496-8821bb5b0a87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412928342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1412928342
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.1012151740
Short name T544
Test name
Test status
Simulation time 171122082900 ps
CPU time 2170.13 seconds
Started Jul 01 04:50:10 PM PDT 24
Finished Jul 01 05:26:24 PM PDT 24
Peak memory 198932 kb
Host smart-d5ba8cbf-868f-4c72-b9b9-06096b652cf7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1012151740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.1012151740
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.577466504
Short name T132
Test name
Test status
Simulation time 13421516 ps
CPU time 0.57 seconds
Started Jul 01 04:50:08 PM PDT 24
Finished Jul 01 04:50:12 PM PDT 24
Peak memory 194144 kb
Host smart-0f031ecd-81ac-499f-855a-037bd81b5147
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577466504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.577466504
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3178367238
Short name T476
Test name
Test status
Simulation time 103302968 ps
CPU time 0.76 seconds
Started Jul 01 04:50:11 PM PDT 24
Finished Jul 01 04:50:15 PM PDT 24
Peak memory 196624 kb
Host smart-3b84ecc5-9d18-4303-a327-d813386673e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178367238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3178367238
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3183219462
Short name T412
Test name
Test status
Simulation time 722670526 ps
CPU time 4.18 seconds
Started Jul 01 04:50:11 PM PDT 24
Finished Jul 01 04:50:19 PM PDT 24
Peak memory 196912 kb
Host smart-3589749b-78fb-4d81-b557-296621ed1689
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183219462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3183219462
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.1806523546
Short name T674
Test name
Test status
Simulation time 89263249 ps
CPU time 0.67 seconds
Started Jul 01 04:50:07 PM PDT 24
Finished Jul 01 04:50:11 PM PDT 24
Peak memory 195972 kb
Host smart-43aa9ea1-33c1-405f-b95f-20806320866c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806523546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.1806523546
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.2962610339
Short name T75
Test name
Test status
Simulation time 101999145 ps
CPU time 1.45 seconds
Started Jul 01 04:50:09 PM PDT 24
Finished Jul 01 04:50:14 PM PDT 24
Peak memory 197228 kb
Host smart-74540ca3-3135-48b5-ba5b-43aa3aa7c319
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962610339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2962610339
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.3508548903
Short name T673
Test name
Test status
Simulation time 68778793 ps
CPU time 1.54 seconds
Started Jul 01 04:50:09 PM PDT 24
Finished Jul 01 04:50:14 PM PDT 24
Peak memory 197544 kb
Host smart-486050e5-b1aa-4e50-8c9b-5eb1ccafdf4d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508548903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.3508548903
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3297863622
Short name T668
Test name
Test status
Simulation time 228560326 ps
CPU time 1.94 seconds
Started Jul 01 04:50:09 PM PDT 24
Finished Jul 01 04:50:15 PM PDT 24
Peak memory 197964 kb
Host smart-cb8fcf91-afeb-4458-9b59-3b96f008d535
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297863622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3297863622
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.1355103578
Short name T482
Test name
Test status
Simulation time 113748787 ps
CPU time 1.16 seconds
Started Jul 01 04:50:12 PM PDT 24
Finished Jul 01 04:50:16 PM PDT 24
Peak memory 196524 kb
Host smart-f3e50ce0-06b4-4bf6-a1d8-fc65a0b51db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355103578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.1355103578
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.3286633284
Short name T261
Test name
Test status
Simulation time 18247643 ps
CPU time 0.66 seconds
Started Jul 01 04:50:07 PM PDT 24
Finished Jul 01 04:50:12 PM PDT 24
Peak memory 195680 kb
Host smart-10bea500-8d3c-4251-aca4-d4e9c4dd8d94
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286633284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.3286633284
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2879072361
Short name T195
Test name
Test status
Simulation time 67200950 ps
CPU time 2.94 seconds
Started Jul 01 04:50:11 PM PDT 24
Finished Jul 01 04:50:17 PM PDT 24
Peak memory 198704 kb
Host smart-9c0c0272-f31a-42f0-968a-4b40f42039dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879072361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2879072361
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.3826998514
Short name T333
Test name
Test status
Simulation time 65195706 ps
CPU time 1.22 seconds
Started Jul 01 04:50:09 PM PDT 24
Finished Jul 01 04:50:14 PM PDT 24
Peak memory 196572 kb
Host smart-c055ce30-682b-43cf-b6a4-4f69252136d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826998514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.3826998514
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1047318743
Short name T231
Test name
Test status
Simulation time 127080420 ps
CPU time 1.21 seconds
Started Jul 01 04:50:07 PM PDT 24
Finished Jul 01 04:50:12 PM PDT 24
Peak memory 196668 kb
Host smart-f75fcc8a-1ce1-4270-8c60-5a8b3ef25ad5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047318743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1047318743
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.2644432973
Short name T421
Test name
Test status
Simulation time 21501600947 ps
CPU time 134.51 seconds
Started Jul 01 04:50:10 PM PDT 24
Finished Jul 01 04:52:28 PM PDT 24
Peak memory 198740 kb
Host smart-551ac592-ec42-48a4-8234-35e4697722d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644432973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.2644432973
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.908189364
Short name T657
Test name
Test status
Simulation time 15148422558 ps
CPU time 99.4 seconds
Started Jul 01 04:50:17 PM PDT 24
Finished Jul 01 04:51:59 PM PDT 24
Peak memory 198772 kb
Host smart-38987081-5dde-4ae5-86ef-32d9ec17fc04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=908189364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.908189364
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.2264054251
Short name T633
Test name
Test status
Simulation time 14629292 ps
CPU time 0.59 seconds
Started Jul 01 04:50:15 PM PDT 24
Finished Jul 01 04:50:19 PM PDT 24
Peak memory 194556 kb
Host smart-0db4c2db-52fa-4a1c-983a-02db69e47b8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264054251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2264054251
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3036547567
Short name T226
Test name
Test status
Simulation time 16270359 ps
CPU time 0.6 seconds
Started Jul 01 04:50:17 PM PDT 24
Finished Jul 01 04:50:20 PM PDT 24
Peak memory 194452 kb
Host smart-143f9add-4a46-4d14-aecd-38e9b8c15182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036547567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3036547567
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1349657292
Short name T635
Test name
Test status
Simulation time 483926085 ps
CPU time 25.95 seconds
Started Jul 01 04:50:12 PM PDT 24
Finished Jul 01 04:50:41 PM PDT 24
Peak memory 198628 kb
Host smart-165f5efa-7abe-498e-9012-3aa9b6b88521
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349657292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1349657292
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2351621079
Short name T395
Test name
Test status
Simulation time 26389327 ps
CPU time 0.72 seconds
Started Jul 01 04:50:10 PM PDT 24
Finished Jul 01 04:50:15 PM PDT 24
Peak memory 195256 kb
Host smart-ded0f1f7-cdb7-4cd7-980a-a02a75a644c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351621079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2351621079
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.588083881
Short name T281
Test name
Test status
Simulation time 2025725386 ps
CPU time 1.47 seconds
Started Jul 01 04:50:15 PM PDT 24
Finished Jul 01 04:50:20 PM PDT 24
Peak memory 197552 kb
Host smart-ed025ec6-d717-4688-b5e0-82819c1e9e7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588083881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.588083881
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2718003662
Short name T246
Test name
Test status
Simulation time 86342401 ps
CPU time 3.16 seconds
Started Jul 01 04:50:09 PM PDT 24
Finished Jul 01 04:50:15 PM PDT 24
Peak memory 198708 kb
Host smart-19aace79-09d4-4bcc-a70b-dbb5841ad6bf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718003662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2718003662
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3803546182
Short name T463
Test name
Test status
Simulation time 90244790 ps
CPU time 2.06 seconds
Started Jul 01 04:50:08 PM PDT 24
Finished Jul 01 04:50:14 PM PDT 24
Peak memory 196484 kb
Host smart-d2800818-189b-474f-acc5-6ea57191a507
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803546182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3803546182
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.3900953748
Short name T310
Test name
Test status
Simulation time 32171912 ps
CPU time 0.85 seconds
Started Jul 01 04:50:07 PM PDT 24
Finished Jul 01 04:50:12 PM PDT 24
Peak memory 197224 kb
Host smart-3cdfc9b0-7670-4811-ad96-c94927107b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900953748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.3900953748
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2370004112
Short name T441
Test name
Test status
Simulation time 201813848 ps
CPU time 1.24 seconds
Started Jul 01 04:50:08 PM PDT 24
Finished Jul 01 04:50:13 PM PDT 24
Peak memory 196792 kb
Host smart-28897097-2ac5-4d17-966c-48f953c9d2fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370004112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2370004112
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1542723895
Short name T681
Test name
Test status
Simulation time 1036075082 ps
CPU time 4.21 seconds
Started Jul 01 04:50:10 PM PDT 24
Finished Jul 01 04:50:18 PM PDT 24
Peak memory 198552 kb
Host smart-633ecbe2-5043-4c4c-82fb-8110e1979480
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542723895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1542723895
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.739536435
Short name T29
Test name
Test status
Simulation time 77805540 ps
CPU time 1.25 seconds
Started Jul 01 04:50:10 PM PDT 24
Finished Jul 01 04:50:15 PM PDT 24
Peak memory 196152 kb
Host smart-251ef869-5326-4130-9925-8dbbcd2b0af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739536435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.739536435
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.395159306
Short name T335
Test name
Test status
Simulation time 52199654 ps
CPU time 1.05 seconds
Started Jul 01 04:50:07 PM PDT 24
Finished Jul 01 04:50:12 PM PDT 24
Peak memory 196404 kb
Host smart-e6b5fe90-7545-41cb-80ad-a427a5b4cd2f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395159306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.395159306
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2007251641
Short name T535
Test name
Test status
Simulation time 2399922751 ps
CPU time 59.21 seconds
Started Jul 01 04:50:09 PM PDT 24
Finished Jul 01 04:51:13 PM PDT 24
Peak memory 198808 kb
Host smart-9eca57e2-4f8f-40ad-b327-b36a70c278e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007251641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2007251641
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3985725725
Short name T577
Test name
Test status
Simulation time 42065900 ps
CPU time 0.59 seconds
Started Jul 01 04:50:16 PM PDT 24
Finished Jul 01 04:50:20 PM PDT 24
Peak memory 195476 kb
Host smart-c90e5d45-24d1-42da-9ce1-2fc7f81fbc21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985725725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3985725725
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.404651146
Short name T624
Test name
Test status
Simulation time 79068969 ps
CPU time 0.9 seconds
Started Jul 01 04:50:17 PM PDT 24
Finished Jul 01 04:50:20 PM PDT 24
Peak memory 196076 kb
Host smart-c3258fb9-a096-419c-9431-316ec4025c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404651146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.404651146
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.2019851799
Short name T127
Test name
Test status
Simulation time 97450437 ps
CPU time 3.63 seconds
Started Jul 01 04:50:16 PM PDT 24
Finished Jul 01 04:50:22 PM PDT 24
Peak memory 196632 kb
Host smart-26c25681-4512-497f-9031-e296c8e898d1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019851799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.2019851799
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.1458085991
Short name T402
Test name
Test status
Simulation time 49193004 ps
CPU time 0.74 seconds
Started Jul 01 04:50:17 PM PDT 24
Finished Jul 01 04:50:20 PM PDT 24
Peak memory 195496 kb
Host smart-1c39aed1-e986-47db-9c5a-9af0379ae358
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458085991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.1458085991
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2823816143
Short name T173
Test name
Test status
Simulation time 86603803 ps
CPU time 1.22 seconds
Started Jul 01 04:50:15 PM PDT 24
Finished Jul 01 04:50:19 PM PDT 24
Peak memory 197412 kb
Host smart-9893f295-e2ab-46fa-82e5-3659231961f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823816143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2823816143
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3780591859
Short name T300
Test name
Test status
Simulation time 93476270 ps
CPU time 1.84 seconds
Started Jul 01 04:50:15 PM PDT 24
Finished Jul 01 04:50:19 PM PDT 24
Peak memory 198744 kb
Host smart-883e6f1e-02cc-4154-9dc1-aa18ddde8458
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780591859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3780591859
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.263372084
Short name T79
Test name
Test status
Simulation time 117397348 ps
CPU time 3.12 seconds
Started Jul 01 04:50:16 PM PDT 24
Finished Jul 01 04:50:22 PM PDT 24
Peak memory 197796 kb
Host smart-0039a2a6-62e8-4ff8-ab5d-a284cd4fe2d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263372084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.
263372084
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1100257787
Short name T287
Test name
Test status
Simulation time 32805979 ps
CPU time 1.3 seconds
Started Jul 01 04:50:17 PM PDT 24
Finished Jul 01 04:50:21 PM PDT 24
Peak memory 196516 kb
Host smart-de9bce5c-4f36-45ca-9be6-e5ebba45d28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100257787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1100257787
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.658401400
Short name T18
Test name
Test status
Simulation time 99906575 ps
CPU time 0.83 seconds
Started Jul 01 04:50:17 PM PDT 24
Finished Jul 01 04:50:21 PM PDT 24
Peak memory 196880 kb
Host smart-ff96e903-0135-478f-960c-4835f0ed1b64
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658401400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup
_pulldown.658401400
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.3050575499
Short name T289
Test name
Test status
Simulation time 86046887 ps
CPU time 1.49 seconds
Started Jul 01 04:50:15 PM PDT 24
Finished Jul 01 04:50:19 PM PDT 24
Peak memory 198660 kb
Host smart-d614be7d-376d-4f5a-ac0f-5775a78cd1b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050575499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.3050575499
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.2182031902
Short name T565
Test name
Test status
Simulation time 127020574 ps
CPU time 1.09 seconds
Started Jul 01 04:50:18 PM PDT 24
Finished Jul 01 04:50:22 PM PDT 24
Peak memory 196536 kb
Host smart-24a7f6ef-b401-4cd6-867e-71ef58785673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182031902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.2182031902
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2713181748
Short name T70
Test name
Test status
Simulation time 300798649 ps
CPU time 1.3 seconds
Started Jul 01 04:50:17 PM PDT 24
Finished Jul 01 04:50:21 PM PDT 24
Peak memory 197376 kb
Host smart-19067f3d-0f3d-460f-9342-c90fb8678863
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713181748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2713181748
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.388623312
Short name T3
Test name
Test status
Simulation time 41733415174 ps
CPU time 111.91 seconds
Started Jul 01 04:50:16 PM PDT 24
Finished Jul 01 04:52:11 PM PDT 24
Peak memory 198912 kb
Host smart-2fb7a614-a2b2-48e5-bfd1-eb3b388ce12a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388623312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.g
pio_stress_all.388623312
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.3299132779
Short name T33
Test name
Test status
Simulation time 41457296261 ps
CPU time 339.31 seconds
Started Jul 01 04:50:15 PM PDT 24
Finished Jul 01 04:55:57 PM PDT 24
Peak memory 198908 kb
Host smart-969c594c-8fae-4ad0-9a99-d8a06394e39a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3299132779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.3299132779
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.773347321
Short name T541
Test name
Test status
Simulation time 10890243 ps
CPU time 0.57 seconds
Started Jul 01 04:48:28 PM PDT 24
Finished Jul 01 04:48:32 PM PDT 24
Peak memory 194644 kb
Host smart-5973b7e7-57bc-490f-92d4-52b19ec2047d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773347321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.773347321
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.854834707
Short name T149
Test name
Test status
Simulation time 15512879 ps
CPU time 0.62 seconds
Started Jul 01 04:48:30 PM PDT 24
Finished Jul 01 04:48:34 PM PDT 24
Peak memory 194592 kb
Host smart-bd3a77d9-001d-422c-ba63-e6789470c8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854834707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.854834707
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.298480987
Short name T449
Test name
Test status
Simulation time 861996576 ps
CPU time 21.88 seconds
Started Jul 01 04:48:29 PM PDT 24
Finished Jul 01 04:48:54 PM PDT 24
Peak memory 198660 kb
Host smart-8dee129a-600f-4224-be06-bc46b0b7a50b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298480987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress
.298480987
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.958295694
Short name T314
Test name
Test status
Simulation time 27348393 ps
CPU time 0.64 seconds
Started Jul 01 04:48:29 PM PDT 24
Finished Jul 01 04:48:33 PM PDT 24
Peak memory 195304 kb
Host smart-ff5d85a8-6302-426c-8fc3-d1b12f5596eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958295694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.958295694
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1034358619
Short name T400
Test name
Test status
Simulation time 57731889 ps
CPU time 0.76 seconds
Started Jul 01 04:48:28 PM PDT 24
Finished Jul 01 04:48:32 PM PDT 24
Peak memory 194916 kb
Host smart-c6abde04-2da5-4587-a13d-69314470ae44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034358619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1034358619
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.125663050
Short name T262
Test name
Test status
Simulation time 85535609 ps
CPU time 1.89 seconds
Started Jul 01 04:48:32 PM PDT 24
Finished Jul 01 04:48:37 PM PDT 24
Peak memory 198664 kb
Host smart-9fb7d11b-ac57-4a29-a6af-cc3becc2d2a7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125663050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.gpio_intr_with_filter_rand_intr_event.125663050
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.1276304032
Short name T138
Test name
Test status
Simulation time 229500836 ps
CPU time 2.23 seconds
Started Jul 01 04:48:33 PM PDT 24
Finished Jul 01 04:48:37 PM PDT 24
Peak memory 197716 kb
Host smart-7c175c78-137e-4666-abe7-03ee8b6928d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276304032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
1276304032
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.359230241
Short name T701
Test name
Test status
Simulation time 81084468 ps
CPU time 1.1 seconds
Started Jul 01 04:48:30 PM PDT 24
Finished Jul 01 04:48:35 PM PDT 24
Peak memory 196524 kb
Host smart-da6cd04e-b716-482b-9488-dd2f05256ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359230241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.359230241
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3909587073
Short name T200
Test name
Test status
Simulation time 225356664 ps
CPU time 1.38 seconds
Started Jul 01 04:48:28 PM PDT 24
Finished Jul 01 04:48:33 PM PDT 24
Peak memory 197840 kb
Host smart-c0857ab2-c847-4c53-acad-bd05beccba90
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909587073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3909587073
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.758004060
Short name T539
Test name
Test status
Simulation time 1382231767 ps
CPU time 1.56 seconds
Started Jul 01 04:48:27 PM PDT 24
Finished Jul 01 04:48:31 PM PDT 24
Peak memory 198616 kb
Host smart-b948d1f3-9b69-493a-8b55-a77b2485e72e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758004060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand
om_long_reg_writes_reg_reads.758004060
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.557829733
Short name T592
Test name
Test status
Simulation time 425098675 ps
CPU time 1.28 seconds
Started Jul 01 04:48:30 PM PDT 24
Finished Jul 01 04:48:34 PM PDT 24
Peak memory 196620 kb
Host smart-e98325d1-c31a-48e9-a7dc-f1120a47ae36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557829733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.557829733
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1810569606
Short name T525
Test name
Test status
Simulation time 166261681 ps
CPU time 1.01 seconds
Started Jul 01 04:48:29 PM PDT 24
Finished Jul 01 04:48:33 PM PDT 24
Peak memory 196196 kb
Host smart-be93d110-b776-4976-8668-74217662783f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810569606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1810569606
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.80673261
Short name T552
Test name
Test status
Simulation time 26642475544 ps
CPU time 181.33 seconds
Started Jul 01 04:48:28 PM PDT 24
Finished Jul 01 04:51:33 PM PDT 24
Peak memory 198788 kb
Host smart-955041bf-1066-4dba-b178-06c2fc6a3889
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80673261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpi
o_stress_all.80673261
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.1446029909
Short name T718
Test name
Test status
Simulation time 466357775706 ps
CPU time 2151.33 seconds
Started Jul 01 04:48:28 PM PDT 24
Finished Jul 01 05:24:23 PM PDT 24
Peak memory 198884 kb
Host smart-9d8e47cf-d1bd-4737-bab7-53658d1f7aaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1446029909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.1446029909
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3398370999
Short name T152
Test name
Test status
Simulation time 31256782 ps
CPU time 0.57 seconds
Started Jul 01 04:48:37 PM PDT 24
Finished Jul 01 04:48:41 PM PDT 24
Peak memory 194652 kb
Host smart-aa84a757-34bb-4724-ad1a-c8d962fd8023
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398370999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3398370999
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.905044890
Short name T214
Test name
Test status
Simulation time 62447499 ps
CPU time 0.81 seconds
Started Jul 01 04:48:34 PM PDT 24
Finished Jul 01 04:48:37 PM PDT 24
Peak memory 196824 kb
Host smart-48e4ed53-2a63-4791-8c7e-8ea55c27f7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905044890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.905044890
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.1366610521
Short name T537
Test name
Test status
Simulation time 665975770 ps
CPU time 10.72 seconds
Started Jul 01 04:48:35 PM PDT 24
Finished Jul 01 04:48:47 PM PDT 24
Peak memory 197716 kb
Host smart-0f4d0a25-14ec-406e-b543-28c040f0ebc3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366610521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.1366610521
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.3495315152
Short name T598
Test name
Test status
Simulation time 172666810 ps
CPU time 0.84 seconds
Started Jul 01 04:48:34 PM PDT 24
Finished Jul 01 04:48:37 PM PDT 24
Peak memory 196512 kb
Host smart-abc5ba8f-462c-4040-a0d4-9320cfaecf46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495315152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3495315152
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3750222927
Short name T164
Test name
Test status
Simulation time 78160387 ps
CPU time 1.47 seconds
Started Jul 01 04:48:35 PM PDT 24
Finished Jul 01 04:48:38 PM PDT 24
Peak memory 198748 kb
Host smart-b2cd1d5f-4a44-4732-b6ea-3bfce91f773d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750222927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3750222927
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1081946580
Short name T417
Test name
Test status
Simulation time 614333038 ps
CPU time 2.17 seconds
Started Jul 01 04:48:38 PM PDT 24
Finished Jul 01 04:48:43 PM PDT 24
Peak memory 198820 kb
Host smart-fe24878c-f062-43b0-b94b-20f9fd00ba5e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081946580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1081946580
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.526978959
Short name T426
Test name
Test status
Simulation time 476912833 ps
CPU time 1.92 seconds
Started Jul 01 04:48:35 PM PDT 24
Finished Jul 01 04:48:40 PM PDT 24
Peak memory 197772 kb
Host smart-795364e8-c232-4de4-9d0c-b03b3b58af5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526978959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.526978959
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.4117681724
Short name T54
Test name
Test status
Simulation time 161566179 ps
CPU time 0.96 seconds
Started Jul 01 04:48:29 PM PDT 24
Finished Jul 01 04:48:34 PM PDT 24
Peak memory 196800 kb
Host smart-7d521dc0-0b80-4d4e-9f48-3dd1f5c56b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117681724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.4117681724
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.1420257439
Short name T458
Test name
Test status
Simulation time 15111217 ps
CPU time 0.73 seconds
Started Jul 01 04:48:39 PM PDT 24
Finished Jul 01 04:48:43 PM PDT 24
Peak memory 196820 kb
Host smart-a5189ea5-7ca1-41f6-839a-a3e9c844f7ed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420257439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.1420257439
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.4117644946
Short name T178
Test name
Test status
Simulation time 37904354 ps
CPU time 1.63 seconds
Started Jul 01 04:48:36 PM PDT 24
Finished Jul 01 04:48:40 PM PDT 24
Peak memory 197416 kb
Host smart-81832497-ba95-4976-a3f2-c3f666873840
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117644946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.4117644946
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.4152537597
Short name T716
Test name
Test status
Simulation time 154797958 ps
CPU time 1.34 seconds
Started Jul 01 04:48:32 PM PDT 24
Finished Jul 01 04:48:36 PM PDT 24
Peak memory 198688 kb
Host smart-e27be506-7020-4bf3-8a95-1efb7da4b785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152537597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.4152537597
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.792273781
Short name T232
Test name
Test status
Simulation time 195764944 ps
CPU time 1.42 seconds
Started Jul 01 04:48:28 PM PDT 24
Finished Jul 01 04:48:33 PM PDT 24
Peak memory 198812 kb
Host smart-24cdf482-b6db-4d75-b602-cd1d6b7b4230
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792273781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.792273781
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3573598202
Short name T510
Test name
Test status
Simulation time 4502687067 ps
CPU time 105.95 seconds
Started Jul 01 04:48:37 PM PDT 24
Finished Jul 01 04:50:26 PM PDT 24
Peak memory 198784 kb
Host smart-73f0ca5c-984c-4387-bd6d-0eb62a44d5ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573598202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3573598202
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.1102701079
Short name T415
Test name
Test status
Simulation time 44727639 ps
CPU time 0.58 seconds
Started Jul 01 04:48:38 PM PDT 24
Finished Jul 01 04:48:42 PM PDT 24
Peak memory 195352 kb
Host smart-de5e5ec5-4438-4c05-a5f2-ab5c7c9da506
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102701079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.1102701079
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.4196277267
Short name T595
Test name
Test status
Simulation time 26226932 ps
CPU time 0.91 seconds
Started Jul 01 04:48:37 PM PDT 24
Finished Jul 01 04:48:41 PM PDT 24
Peak memory 196840 kb
Host smart-9da69706-cec3-438b-bbbf-4d804e5df8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196277267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.4196277267
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2370535910
Short name T243
Test name
Test status
Simulation time 111388317 ps
CPU time 4.61 seconds
Started Jul 01 04:48:38 PM PDT 24
Finished Jul 01 04:48:46 PM PDT 24
Peak memory 196500 kb
Host smart-be406036-0a58-4c53-a590-fce2bf8e4c5e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370535910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2370535910
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.4282894382
Short name T601
Test name
Test status
Simulation time 46559669 ps
CPU time 0.83 seconds
Started Jul 01 04:48:34 PM PDT 24
Finished Jul 01 04:48:37 PM PDT 24
Peak memory 196412 kb
Host smart-64ad8ed7-6c17-425a-a84a-8f781d30958c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282894382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.4282894382
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.1570894074
Short name T122
Test name
Test status
Simulation time 50635673 ps
CPU time 0.8 seconds
Started Jul 01 04:48:37 PM PDT 24
Finished Jul 01 04:48:41 PM PDT 24
Peak memory 196820 kb
Host smart-ca1c3e76-60f4-4390-8a90-568c2c146856
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570894074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1570894074
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.2921951810
Short name T651
Test name
Test status
Simulation time 394663953 ps
CPU time 1.75 seconds
Started Jul 01 04:48:34 PM PDT 24
Finished Jul 01 04:48:37 PM PDT 24
Peak memory 196968 kb
Host smart-5dcb4a37-61bb-44d5-bb14-9cb4c5ec52cf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921951810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.2921951810
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.638448447
Short name T488
Test name
Test status
Simulation time 163056768 ps
CPU time 3.22 seconds
Started Jul 01 04:48:41 PM PDT 24
Finished Jul 01 04:48:48 PM PDT 24
Peak memory 198664 kb
Host smart-2e6efaf3-99ef-4baf-a0d5-7d919d2708cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638448447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.638448447
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.2599829101
Short name T399
Test name
Test status
Simulation time 98576614 ps
CPU time 0.73 seconds
Started Jul 01 04:48:35 PM PDT 24
Finished Jul 01 04:48:38 PM PDT 24
Peak memory 196756 kb
Host smart-83611c19-1154-4dea-9485-74bd58459c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599829101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.2599829101
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3313372306
Short name T283
Test name
Test status
Simulation time 91629273 ps
CPU time 1 seconds
Started Jul 01 04:48:35 PM PDT 24
Finished Jul 01 04:48:39 PM PDT 24
Peak memory 197172 kb
Host smart-2a20abf9-396e-4b0c-8ff8-ce78e33964d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313372306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3313372306
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.2349041408
Short name T562
Test name
Test status
Simulation time 2483609564 ps
CPU time 7.42 seconds
Started Jul 01 04:48:37 PM PDT 24
Finished Jul 01 04:48:48 PM PDT 24
Peak memory 198700 kb
Host smart-911c5a2c-e973-46ec-8c84-a9d61423b82c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349041408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.2349041408
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.2849104417
Short name T77
Test name
Test status
Simulation time 35710621 ps
CPU time 1.07 seconds
Started Jul 01 04:48:36 PM PDT 24
Finished Jul 01 04:48:39 PM PDT 24
Peak memory 196316 kb
Host smart-6263d882-fcaf-4bfc-9f3c-60a22fea5414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849104417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.2849104417
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.3223279774
Short name T432
Test name
Test status
Simulation time 79374345 ps
CPU time 1.23 seconds
Started Jul 01 04:48:37 PM PDT 24
Finished Jul 01 04:48:41 PM PDT 24
Peak memory 196388 kb
Host smart-e12d9efe-4376-4104-af94-d60b153eb546
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223279774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.3223279774
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.930797956
Short name T350
Test name
Test status
Simulation time 27549686542 ps
CPU time 105.4 seconds
Started Jul 01 04:48:38 PM PDT 24
Finished Jul 01 04:50:26 PM PDT 24
Peak memory 198832 kb
Host smart-bacb5b2c-f0f0-429f-b514-d58a2e1110ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930797956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.930797956
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2104100783
Short name T470
Test name
Test status
Simulation time 229717196 ps
CPU time 0.58 seconds
Started Jul 01 04:48:45 PM PDT 24
Finished Jul 01 04:48:50 PM PDT 24
Peak memory 194836 kb
Host smart-b74c3769-f854-49b7-9605-770d6f84617a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104100783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2104100783
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1999398451
Short name T429
Test name
Test status
Simulation time 145776962 ps
CPU time 0.86 seconds
Started Jul 01 04:48:41 PM PDT 24
Finished Jul 01 04:48:46 PM PDT 24
Peak memory 197136 kb
Host smart-0765118e-86b9-4729-940c-59716d31f94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999398451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1999398451
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.14730973
Short name T128
Test name
Test status
Simulation time 186940122 ps
CPU time 6.01 seconds
Started Jul 01 04:48:41 PM PDT 24
Finished Jul 01 04:48:51 PM PDT 24
Peak memory 198584 kb
Host smart-95396b5c-a716-4df8-a3e7-0f9818f5847d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14730973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress.14730973
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.2753552861
Short name T639
Test name
Test status
Simulation time 742049355 ps
CPU time 0.83 seconds
Started Jul 01 04:48:35 PM PDT 24
Finished Jul 01 04:48:38 PM PDT 24
Peak memory 196604 kb
Host smart-6bba97be-1053-43e8-9e8f-363a8f23fc3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753552861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.2753552861
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.3523160968
Short name T385
Test name
Test status
Simulation time 93218159 ps
CPU time 1.23 seconds
Started Jul 01 04:48:36 PM PDT 24
Finished Jul 01 04:48:40 PM PDT 24
Peak memory 197352 kb
Host smart-d08d48dd-0055-402e-98bc-e9e0532be4d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523160968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.3523160968
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.328521340
Short name T303
Test name
Test status
Simulation time 78263090 ps
CPU time 3.07 seconds
Started Jul 01 04:48:34 PM PDT 24
Finished Jul 01 04:48:39 PM PDT 24
Peak memory 198816 kb
Host smart-1cd4d5a5-4c96-4ebe-ab05-4e5136fb3365
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328521340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.328521340
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2900647498
Short name T711
Test name
Test status
Simulation time 155530649 ps
CPU time 1.64 seconds
Started Jul 01 04:48:38 PM PDT 24
Finished Jul 01 04:48:43 PM PDT 24
Peak memory 196668 kb
Host smart-3e207e9d-f944-4d5d-ad03-64cfc9251474
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900647498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2900647498
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3805285318
Short name T506
Test name
Test status
Simulation time 17438210 ps
CPU time 0.72 seconds
Started Jul 01 04:48:41 PM PDT 24
Finished Jul 01 04:48:46 PM PDT 24
Peak memory 196164 kb
Host smart-74793dcf-b79c-42ce-9df3-009456f518c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805285318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3805285318
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1634304132
Short name T610
Test name
Test status
Simulation time 51354298 ps
CPU time 1.01 seconds
Started Jul 01 04:48:45 PM PDT 24
Finished Jul 01 04:48:50 PM PDT 24
Peak memory 196472 kb
Host smart-d6516f01-ba0a-499a-b0c1-6bd1452f590c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634304132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1634304132
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1663152162
Short name T708
Test name
Test status
Simulation time 580430773 ps
CPU time 4.66 seconds
Started Jul 01 04:48:38 PM PDT 24
Finished Jul 01 04:48:45 PM PDT 24
Peak memory 198580 kb
Host smart-1ea6dd25-7742-4a8e-86be-d868a682ef50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663152162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1663152162
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1308146185
Short name T343
Test name
Test status
Simulation time 69265435 ps
CPU time 1.23 seconds
Started Jul 01 04:48:39 PM PDT 24
Finished Jul 01 04:48:43 PM PDT 24
Peak memory 196240 kb
Host smart-fdea80ba-0034-465f-bfe4-6c1060b43047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308146185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1308146185
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.3114479459
Short name T340
Test name
Test status
Simulation time 1247416118 ps
CPU time 1.33 seconds
Started Jul 01 04:48:36 PM PDT 24
Finished Jul 01 04:48:40 PM PDT 24
Peak memory 197156 kb
Host smart-3e564b6f-afd5-41f7-a451-3653388626c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114479459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.3114479459
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.3513099855
Short name T275
Test name
Test status
Simulation time 3636442570 ps
CPU time 80.3 seconds
Started Jul 01 04:48:35 PM PDT 24
Finished Jul 01 04:49:57 PM PDT 24
Peak memory 198708 kb
Host smart-fd007962-8abb-4cd0-b8bb-3f5f8651cfad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513099855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.3513099855
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.2663893531
Short name T334
Test name
Test status
Simulation time 1615602315108 ps
CPU time 2388.62 seconds
Started Jul 01 04:48:38 PM PDT 24
Finished Jul 01 05:28:30 PM PDT 24
Peak memory 198920 kb
Host smart-ee738247-7be9-4194-bb32-19151ec294f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2663893531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.2663893531
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3629343941
Short name T326
Test name
Test status
Simulation time 17546156 ps
CPU time 0.59 seconds
Started Jul 01 04:48:42 PM PDT 24
Finished Jul 01 04:48:46 PM PDT 24
Peak memory 194624 kb
Host smart-19ab56d1-2556-4b9a-95dd-7c7ba0cba367
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629343941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3629343941
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.250343666
Short name T530
Test name
Test status
Simulation time 120959653 ps
CPU time 0.82 seconds
Started Jul 01 04:48:36 PM PDT 24
Finished Jul 01 04:48:39 PM PDT 24
Peak memory 196064 kb
Host smart-148f20eb-8a2f-45d7-ab79-8251c8831892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250343666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.250343666
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.739825355
Short name T306
Test name
Test status
Simulation time 3188711102 ps
CPU time 22.79 seconds
Started Jul 01 04:48:41 PM PDT 24
Finished Jul 01 04:49:08 PM PDT 24
Peak memory 198764 kb
Host smart-a5f91d22-1f47-454e-b28a-0d27a7b711b5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739825355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stress
.739825355
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.1155025348
Short name T13
Test name
Test status
Simulation time 100034529 ps
CPU time 0.69 seconds
Started Jul 01 04:48:40 PM PDT 24
Finished Jul 01 04:48:45 PM PDT 24
Peak memory 195220 kb
Host smart-a718cba5-1cc0-44fd-bc59-19607f381078
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155025348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.1155025348
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.3767279743
Short name T691
Test name
Test status
Simulation time 206512320 ps
CPU time 1.02 seconds
Started Jul 01 04:48:35 PM PDT 24
Finished Jul 01 04:48:37 PM PDT 24
Peak memory 196756 kb
Host smart-5befebe1-9d4e-4b16-ad58-1542685d3fc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767279743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.3767279743
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1688449686
Short name T330
Test name
Test status
Simulation time 105678387 ps
CPU time 1.14 seconds
Started Jul 01 04:48:37 PM PDT 24
Finished Jul 01 04:48:41 PM PDT 24
Peak memory 197896 kb
Host smart-f29e24df-9307-4257-b192-6214acea295f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688449686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1688449686
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1433733684
Short name T699
Test name
Test status
Simulation time 307113506 ps
CPU time 3.21 seconds
Started Jul 01 04:48:45 PM PDT 24
Finished Jul 01 04:48:52 PM PDT 24
Peak memory 196452 kb
Host smart-d2495846-645b-4c10-b1ed-d7fd31687e98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433733684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1433733684
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.2730851987
Short name T655
Test name
Test status
Simulation time 22099825 ps
CPU time 0.97 seconds
Started Jul 01 04:48:39 PM PDT 24
Finished Jul 01 04:48:43 PM PDT 24
Peak memory 196484 kb
Host smart-686237ae-26d3-4dce-b6c2-8a750f667889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730851987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.2730851987
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.1518324590
Short name T160
Test name
Test status
Simulation time 88189025 ps
CPU time 1.01 seconds
Started Jul 01 04:48:45 PM PDT 24
Finished Jul 01 04:48:50 PM PDT 24
Peak memory 196424 kb
Host smart-371249c3-f0b3-4c51-b672-7f483ad5dd1b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518324590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.1518324590
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1931789920
Short name T224
Test name
Test status
Simulation time 696994991 ps
CPU time 2.34 seconds
Started Jul 01 04:48:42 PM PDT 24
Finished Jul 01 04:48:49 PM PDT 24
Peak memory 198644 kb
Host smart-67c3f2ea-f19e-4ab5-ab02-cb6ccc8d48f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931789920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1931789920
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1892341023
Short name T420
Test name
Test status
Simulation time 37601725 ps
CPU time 0.79 seconds
Started Jul 01 04:48:45 PM PDT 24
Finished Jul 01 04:48:50 PM PDT 24
Peak memory 197596 kb
Host smart-2e5b0d73-fe24-4b61-896c-54ceee6309b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892341023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1892341023
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.976085679
Short name T460
Test name
Test status
Simulation time 140081098 ps
CPU time 1.4 seconds
Started Jul 01 04:48:37 PM PDT 24
Finished Jul 01 04:48:41 PM PDT 24
Peak memory 197404 kb
Host smart-7cf464a9-e629-4107-9eb7-79e098e48c1b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976085679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.976085679
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.2371243413
Short name T480
Test name
Test status
Simulation time 11030809580 ps
CPU time 130.39 seconds
Started Jul 01 04:48:43 PM PDT 24
Finished Jul 01 04:50:58 PM PDT 24
Peak memory 198828 kb
Host smart-68ee613f-dee3-42e5-8c14-1dee60710bae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371243413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.2371243413
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.1109328356
Short name T63
Test name
Test status
Simulation time 350922082476 ps
CPU time 1269.21 seconds
Started Jul 01 04:48:42 PM PDT 24
Finished Jul 01 05:09:55 PM PDT 24
Peak memory 198888 kb
Host smart-3c0e5992-bb39-4f0c-8fd5-794cbf178d7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1109328356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.1109328356
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3365335808
Short name T919
Test name
Test status
Simulation time 39836027 ps
CPU time 1.04 seconds
Started Jul 01 04:25:46 PM PDT 24
Finished Jul 01 04:25:58 PM PDT 24
Peak memory 197032 kb
Host smart-58584abd-8377-46ce-b0d9-5d5302c6bd8e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3365335808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3365335808
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.404716605
Short name T909
Test name
Test status
Simulation time 295184259 ps
CPU time 1.35 seconds
Started Jul 01 04:25:24 PM PDT 24
Finished Jul 01 04:25:38 PM PDT 24
Peak memory 196964 kb
Host smart-634e789d-ef71-4c0e-8702-bba13a2a52c3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404716605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.404716605
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2952714018
Short name T859
Test name
Test status
Simulation time 68425576 ps
CPU time 0.99 seconds
Started Jul 01 04:25:52 PM PDT 24
Finished Jul 01 04:26:04 PM PDT 24
Peak memory 196828 kb
Host smart-71d57249-dc56-4d1f-af59-785970d280ae
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2952714018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.2952714018
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1864198480
Short name T914
Test name
Test status
Simulation time 209171276 ps
CPU time 1.04 seconds
Started Jul 01 04:25:30 PM PDT 24
Finished Jul 01 04:25:42 PM PDT 24
Peak memory 192136 kb
Host smart-56b29486-9bba-4fd8-9311-b9149a6bdbb2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864198480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1864198480
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3327748087
Short name T918
Test name
Test status
Simulation time 137268899 ps
CPU time 1.09 seconds
Started Jul 01 04:25:17 PM PDT 24
Finished Jul 01 04:25:27 PM PDT 24
Peak memory 196044 kb
Host smart-7f15efd6-cc98-4f4d-887f-86e5340dae21
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3327748087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3327748087
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3981412939
Short name T935
Test name
Test status
Simulation time 399332075 ps
CPU time 1.47 seconds
Started Jul 01 04:25:32 PM PDT 24
Finished Jul 01 04:25:44 PM PDT 24
Peak memory 196836 kb
Host smart-0cdbdbc4-8db1-4f46-9a6d-139f3250a10e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981412939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3981412939
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.386604373
Short name T851
Test name
Test status
Simulation time 143803952 ps
CPU time 1.1 seconds
Started Jul 01 04:25:23 PM PDT 24
Finished Jul 01 04:25:35 PM PDT 24
Peak memory 198308 kb
Host smart-786fff56-6b2a-4f88-b0b4-275037996fe1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=386604373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.386604373
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.59131372
Short name T938
Test name
Test status
Simulation time 35475788 ps
CPU time 1.09 seconds
Started Jul 01 04:25:19 PM PDT 24
Finished Jul 01 04:25:30 PM PDT 24
Peak memory 196448 kb
Host smart-a9f75c8c-d0e2-4314-aba1-41dca574738a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59131372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.59131372
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.535071380
Short name T854
Test name
Test status
Simulation time 75260734 ps
CPU time 1.18 seconds
Started Jul 01 04:25:52 PM PDT 24
Finished Jul 01 04:26:04 PM PDT 24
Peak memory 195940 kb
Host smart-981a920f-c167-4951-9dd4-961f84732115
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=535071380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.535071380
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3578456945
Short name T898
Test name
Test status
Simulation time 196976281 ps
CPU time 1.39 seconds
Started Jul 01 04:25:31 PM PDT 24
Finished Jul 01 04:25:43 PM PDT 24
Peak memory 197660 kb
Host smart-bd49af5e-9a1e-433e-9558-ef987effbacc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578456945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3578456945
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.451767169
Short name T912
Test name
Test status
Simulation time 52291957 ps
CPU time 1.11 seconds
Started Jul 01 04:25:20 PM PDT 24
Finished Jul 01 04:25:32 PM PDT 24
Peak memory 196808 kb
Host smart-eab852c0-5440-4776-9081-07a448952110
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=451767169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.451767169
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2697207659
Short name T942
Test name
Test status
Simulation time 130173232 ps
CPU time 1.14 seconds
Started Jul 01 04:25:19 PM PDT 24
Finished Jul 01 04:25:30 PM PDT 24
Peak memory 197120 kb
Host smart-e9046b2d-37ff-46f8-990c-d9eb5f338388
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697207659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2697207659
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.747513370
Short name T865
Test name
Test status
Simulation time 270284501 ps
CPU time 1.22 seconds
Started Jul 01 04:25:44 PM PDT 24
Finished Jul 01 04:25:55 PM PDT 24
Peak memory 195956 kb
Host smart-5a2f2fc8-8f41-4cfc-8394-747070eb4fca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=747513370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.747513370
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1953504494
Short name T900
Test name
Test status
Simulation time 70875652 ps
CPU time 1.22 seconds
Started Jul 01 04:25:32 PM PDT 24
Finished Jul 01 04:25:44 PM PDT 24
Peak memory 196876 kb
Host smart-6cd8d2ee-6c42-4c74-8da2-b671ba851e40
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953504494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1953504494
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.496517824
Short name T870
Test name
Test status
Simulation time 103566262 ps
CPU time 1.59 seconds
Started Jul 01 04:25:22 PM PDT 24
Finished Jul 01 04:25:35 PM PDT 24
Peak memory 196868 kb
Host smart-77968cbd-57aa-460e-8185-708874c80d2a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=496517824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.496517824
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.374048939
Short name T932
Test name
Test status
Simulation time 51161342 ps
CPU time 1.1 seconds
Started Jul 01 04:25:27 PM PDT 24
Finished Jul 01 04:25:41 PM PDT 24
Peak memory 196852 kb
Host smart-49e4f1ab-04e8-4957-bf27-31a26d1d18b8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374048939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.374048939
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2498321303
Short name T850
Test name
Test status
Simulation time 107156179 ps
CPU time 1.02 seconds
Started Jul 01 04:25:27 PM PDT 24
Finished Jul 01 04:25:41 PM PDT 24
Peak memory 196832 kb
Host smart-6e562d74-ad8c-46f7-b245-d0ea82a86d5e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2498321303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2498321303
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3237777604
Short name T945
Test name
Test status
Simulation time 69516516 ps
CPU time 1.23 seconds
Started Jul 01 04:25:20 PM PDT 24
Finished Jul 01 04:25:32 PM PDT 24
Peak memory 197300 kb
Host smart-46ff5f89-73d4-4334-a099-3809d9b7c7ab
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237777604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3237777604
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1260657353
Short name T866
Test name
Test status
Simulation time 47794613 ps
CPU time 1 seconds
Started Jul 01 04:25:22 PM PDT 24
Finished Jul 01 04:25:34 PM PDT 24
Peak memory 197136 kb
Host smart-5e429b2a-aa43-44d4-ab97-b0a8ba172727
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1260657353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1260657353
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2235213760
Short name T920
Test name
Test status
Simulation time 103845614 ps
CPU time 1.59 seconds
Started Jul 01 04:25:24 PM PDT 24
Finished Jul 01 04:25:38 PM PDT 24
Peak memory 197200 kb
Host smart-96fcb5ce-c7a1-46eb-85c5-866facd213bb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235213760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2235213760
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.309678984
Short name T876
Test name
Test status
Simulation time 167895336 ps
CPU time 1.38 seconds
Started Jul 01 04:25:31 PM PDT 24
Finished Jul 01 04:25:43 PM PDT 24
Peak memory 198280 kb
Host smart-9b10c334-54b9-4d5e-8936-4dcd6da77aaa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=309678984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.309678984
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.945662628
Short name T917
Test name
Test status
Simulation time 36845682 ps
CPU time 1.06 seconds
Started Jul 01 04:25:24 PM PDT 24
Finished Jul 01 04:25:37 PM PDT 24
Peak memory 198272 kb
Host smart-0952c531-af5a-483f-9343-8be3adc0f27c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945662628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.945662628
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.336592240
Short name T863
Test name
Test status
Simulation time 82266227 ps
CPU time 1.11 seconds
Started Jul 01 04:25:37 PM PDT 24
Finished Jul 01 04:25:48 PM PDT 24
Peak memory 197124 kb
Host smart-dbfebe15-9026-44d0-9ef8-7b3405619677
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=336592240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.336592240
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4040450468
Short name T874
Test name
Test status
Simulation time 265906650 ps
CPU time 1.05 seconds
Started Jul 01 04:25:22 PM PDT 24
Finished Jul 01 04:25:34 PM PDT 24
Peak memory 196776 kb
Host smart-1375bd4f-71e6-403e-b740-6f8e34e844d9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040450468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4040450468
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.969473755
Short name T872
Test name
Test status
Simulation time 686245228 ps
CPU time 1.11 seconds
Started Jul 01 04:25:18 PM PDT 24
Finished Jul 01 04:25:28 PM PDT 24
Peak memory 194768 kb
Host smart-b580a0d3-b6ec-4d35-a771-0d3e42b3052f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=969473755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.969473755
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2730725519
Short name T868
Test name
Test status
Simulation time 263678587 ps
CPU time 1.24 seconds
Started Jul 01 04:25:23 PM PDT 24
Finished Jul 01 04:25:37 PM PDT 24
Peak memory 198272 kb
Host smart-daac7124-4618-4690-9eb9-7278f06354b5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730725519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2730725519
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.4253472021
Short name T856
Test name
Test status
Simulation time 95866688 ps
CPU time 1.35 seconds
Started Jul 01 04:25:19 PM PDT 24
Finished Jul 01 04:25:30 PM PDT 24
Peak memory 198300 kb
Host smart-5ce8e7fa-83c2-4a51-b477-8e194828eaa5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4253472021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.4253472021
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4082069719
Short name T937
Test name
Test status
Simulation time 70663935 ps
CPU time 1.28 seconds
Started Jul 01 04:25:18 PM PDT 24
Finished Jul 01 04:25:28 PM PDT 24
Peak memory 197552 kb
Host smart-f33282e6-4f70-4804-9366-c92bec737cdb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082069719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4082069719
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.229543764
Short name T901
Test name
Test status
Simulation time 217054946 ps
CPU time 0.94 seconds
Started Jul 01 04:25:16 PM PDT 24
Finished Jul 01 04:25:25 PM PDT 24
Peak memory 196852 kb
Host smart-29392bc5-1295-4d0b-a787-80b5208bc375
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=229543764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.229543764
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3215743037
Short name T929
Test name
Test status
Simulation time 59875644 ps
CPU time 1.02 seconds
Started Jul 01 04:25:36 PM PDT 24
Finished Jul 01 04:25:47 PM PDT 24
Peak memory 196860 kb
Host smart-d419e133-4172-4bd9-9829-f641086143e6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215743037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3215743037
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3264461785
Short name T947
Test name
Test status
Simulation time 208744550 ps
CPU time 0.96 seconds
Started Jul 01 04:25:19 PM PDT 24
Finished Jul 01 04:25:30 PM PDT 24
Peak memory 195936 kb
Host smart-a87dd5a8-6519-4adc-979c-f8cae860968c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3264461785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3264461785
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.677036851
Short name T881
Test name
Test status
Simulation time 416939593 ps
CPU time 1.17 seconds
Started Jul 01 04:25:23 PM PDT 24
Finished Jul 01 04:25:35 PM PDT 24
Peak memory 196232 kb
Host smart-3a5ae3e4-a1ea-43c5-afa6-5db3173146f3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677036851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.677036851
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2481785437
Short name T890
Test name
Test status
Simulation time 131569792 ps
CPU time 1.17 seconds
Started Jul 01 04:25:17 PM PDT 24
Finished Jul 01 04:25:27 PM PDT 24
Peak memory 195996 kb
Host smart-49a3513c-29a9-486d-8e5b-1fdfeab5f4a4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2481785437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.2481785437
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3017432253
Short name T906
Test name
Test status
Simulation time 49869738 ps
CPU time 1.27 seconds
Started Jul 01 04:25:29 PM PDT 24
Finished Jul 01 04:25:42 PM PDT 24
Peak memory 196828 kb
Host smart-9a14f0b7-f8be-4dce-adaf-d2b1649f572a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017432253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3017432253
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3861014986
Short name T871
Test name
Test status
Simulation time 52191616 ps
CPU time 0.92 seconds
Started Jul 01 04:25:22 PM PDT 24
Finished Jul 01 04:25:34 PM PDT 24
Peak memory 195916 kb
Host smart-93fdcae6-6c16-41d9-8a73-df61c4af0ff8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3861014986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.3861014986
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1256323922
Short name T902
Test name
Test status
Simulation time 230387101 ps
CPU time 1.59 seconds
Started Jul 01 04:25:22 PM PDT 24
Finished Jul 01 04:25:34 PM PDT 24
Peak memory 197116 kb
Host smart-69910bd1-b525-4d39-97b8-0cb985f32649
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256323922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1256323922
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.752530693
Short name T895
Test name
Test status
Simulation time 182685927 ps
CPU time 1.24 seconds
Started Jul 01 04:25:27 PM PDT 24
Finished Jul 01 04:25:41 PM PDT 24
Peak memory 198456 kb
Host smart-dda1cbfa-8d7a-4f05-9646-a6731c5a21c0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=752530693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.752530693
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1609732929
Short name T921
Test name
Test status
Simulation time 362933869 ps
CPU time 1.26 seconds
Started Jul 01 04:25:18 PM PDT 24
Finished Jul 01 04:25:30 PM PDT 24
Peak memory 197196 kb
Host smart-a30d691b-bdfe-43c6-ba00-4e7d6984eb2f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609732929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1609732929
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.4105095968
Short name T927
Test name
Test status
Simulation time 445307299 ps
CPU time 1.32 seconds
Started Jul 01 04:25:28 PM PDT 24
Finished Jul 01 04:25:41 PM PDT 24
Peak memory 195936 kb
Host smart-25e4e8f5-c365-4902-9682-5a22c8d25b93
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4105095968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.4105095968
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2675621538
Short name T862
Test name
Test status
Simulation time 85561322 ps
CPU time 1.48 seconds
Started Jul 01 04:25:23 PM PDT 24
Finished Jul 01 04:25:36 PM PDT 24
Peak memory 198280 kb
Host smart-7323b676-ce41-492e-b66b-0863995c14d1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675621538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2675621538
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.620841529
Short name T928
Test name
Test status
Simulation time 90725834 ps
CPU time 0.95 seconds
Started Jul 01 04:25:24 PM PDT 24
Finished Jul 01 04:25:38 PM PDT 24
Peak memory 196872 kb
Host smart-85be9d60-5706-4360-b047-7dd0f7adda68
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=620841529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.620841529
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2217933549
Short name T867
Test name
Test status
Simulation time 66500399 ps
CPU time 1.43 seconds
Started Jul 01 04:25:19 PM PDT 24
Finished Jul 01 04:25:30 PM PDT 24
Peak memory 196232 kb
Host smart-331d7ed0-068a-4981-9ae3-38be272bcc0f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217933549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2217933549
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3631255179
Short name T915
Test name
Test status
Simulation time 46688746 ps
CPU time 0.96 seconds
Started Jul 01 04:25:26 PM PDT 24
Finished Jul 01 04:25:39 PM PDT 24
Peak memory 196160 kb
Host smart-47c76bcf-9125-4751-a987-5474db1fd720
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3631255179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.3631255179
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3324203928
Short name T923
Test name
Test status
Simulation time 84997799 ps
CPU time 1.36 seconds
Started Jul 01 04:25:36 PM PDT 24
Finished Jul 01 04:25:48 PM PDT 24
Peak memory 197612 kb
Host smart-46c4361c-f5b1-49ba-82ed-36e699b04afd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324203928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3324203928
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2623068745
Short name T940
Test name
Test status
Simulation time 182246254 ps
CPU time 0.95 seconds
Started Jul 01 04:25:25 PM PDT 24
Finished Jul 01 04:25:38 PM PDT 24
Peak memory 196748 kb
Host smart-a3f2a0f7-b7e5-46af-9835-8ee8945e0cd3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2623068745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.2623068745
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3782312842
Short name T848
Test name
Test status
Simulation time 37275693 ps
CPU time 1.14 seconds
Started Jul 01 04:25:21 PM PDT 24
Finished Jul 01 04:25:33 PM PDT 24
Peak memory 196776 kb
Host smart-a4a48b9c-7f02-4976-bf77-7a39b22996c8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782312842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3782312842
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2978259368
Short name T864
Test name
Test status
Simulation time 363723437 ps
CPU time 1.42 seconds
Started Jul 01 04:25:25 PM PDT 24
Finished Jul 01 04:25:39 PM PDT 24
Peak memory 197432 kb
Host smart-bdbe6be2-ca6c-4196-8800-6d9d25102dcb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2978259368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2978259368
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2988073268
Short name T899
Test name
Test status
Simulation time 265175614 ps
CPU time 1.4 seconds
Started Jul 01 04:25:18 PM PDT 24
Finished Jul 01 04:25:29 PM PDT 24
Peak memory 197504 kb
Host smart-df0f0fa6-6a67-4364-9cfa-98191fffc3af
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988073268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2988073268
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2675016689
Short name T879
Test name
Test status
Simulation time 434031247 ps
CPU time 1.51 seconds
Started Jul 01 04:25:35 PM PDT 24
Finished Jul 01 04:25:47 PM PDT 24
Peak memory 196844 kb
Host smart-2d3e0a33-b4ac-431b-9f49-b89ac0811608
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2675016689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2675016689
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1218441100
Short name T904
Test name
Test status
Simulation time 202711197 ps
CPU time 1.35 seconds
Started Jul 01 04:25:17 PM PDT 24
Finished Jul 01 04:25:27 PM PDT 24
Peak memory 196904 kb
Host smart-a0fc211c-b97f-4ea0-b9b7-39f89c001ed0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218441100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1218441100
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2220252600
Short name T869
Test name
Test status
Simulation time 141502298 ps
CPU time 0.85 seconds
Started Jul 01 04:25:33 PM PDT 24
Finished Jul 01 04:25:45 PM PDT 24
Peak memory 196708 kb
Host smart-51c8ec11-8571-415b-9450-f4571c476f70
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2220252600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2220252600
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.141887838
Short name T891
Test name
Test status
Simulation time 150265838 ps
CPU time 1.52 seconds
Started Jul 01 04:25:27 PM PDT 24
Finished Jul 01 04:25:41 PM PDT 24
Peak memory 197016 kb
Host smart-ea6b8c07-ad20-4f91-b337-4247bf3b5c9b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141887838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.141887838
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.95122119
Short name T944
Test name
Test status
Simulation time 83443879 ps
CPU time 0.98 seconds
Started Jul 01 04:25:21 PM PDT 24
Finished Jul 01 04:25:32 PM PDT 24
Peak memory 191988 kb
Host smart-37d6b461-22cf-4310-af69-a54f19658392
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=95122119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.95122119
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2876508019
Short name T853
Test name
Test status
Simulation time 50014469 ps
CPU time 1.41 seconds
Started Jul 01 04:25:45 PM PDT 24
Finished Jul 01 04:25:56 PM PDT 24
Peak memory 197032 kb
Host smart-35511f52-b7bf-40fd-88df-9c958220108e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876508019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2876508019
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2459005164
Short name T924
Test name
Test status
Simulation time 75348583 ps
CPU time 0.9 seconds
Started Jul 01 04:25:25 PM PDT 24
Finished Jul 01 04:25:39 PM PDT 24
Peak memory 196632 kb
Host smart-d75094ea-2623-48bb-9a2d-a302cd1fcbb3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2459005164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2459005164
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4065441642
Short name T905
Test name
Test status
Simulation time 73025005 ps
CPU time 1.16 seconds
Started Jul 01 04:25:38 PM PDT 24
Finished Jul 01 04:25:49 PM PDT 24
Peak memory 196872 kb
Host smart-dbb83f6e-4ddb-4289-ad46-a108799b91d4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065441642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4065441642
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.4288770761
Short name T860
Test name
Test status
Simulation time 28181787 ps
CPU time 0.77 seconds
Started Jul 01 04:25:31 PM PDT 24
Finished Jul 01 04:25:43 PM PDT 24
Peak memory 195900 kb
Host smart-33a3042c-295c-467e-848a-a9e23b3360dd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4288770761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.4288770761
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.814560596
Short name T861
Test name
Test status
Simulation time 155054375 ps
CPU time 1.19 seconds
Started Jul 01 04:25:18 PM PDT 24
Finished Jul 01 04:25:28 PM PDT 24
Peak memory 197164 kb
Host smart-2a041496-beee-41cf-854c-a7d0f6ae85aa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814560596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.814560596
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.719315263
Short name T913
Test name
Test status
Simulation time 369260035 ps
CPU time 1.36 seconds
Started Jul 01 04:25:33 PM PDT 24
Finished Jul 01 04:25:45 PM PDT 24
Peak memory 196984 kb
Host smart-bd53dbc2-cc6e-4e87-afef-e89ad7dab8cb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=719315263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.719315263
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3049831483
Short name T883
Test name
Test status
Simulation time 64544321 ps
CPU time 1.08 seconds
Started Jul 01 04:25:24 PM PDT 24
Finished Jul 01 04:25:36 PM PDT 24
Peak memory 196800 kb
Host smart-597fb5f6-4660-4dfa-8921-64844bcafbd6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049831483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3049831483
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1970921791
Short name T849
Test name
Test status
Simulation time 238443378 ps
CPU time 0.78 seconds
Started Jul 01 04:25:42 PM PDT 24
Finished Jul 01 04:25:53 PM PDT 24
Peak memory 196468 kb
Host smart-5c90b51e-7985-4823-aa83-85d0ac7849de
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1970921791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.1970921791
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3189369478
Short name T857
Test name
Test status
Simulation time 99164937 ps
CPU time 0.97 seconds
Started Jul 01 04:25:36 PM PDT 24
Finished Jul 01 04:25:47 PM PDT 24
Peak memory 196852 kb
Host smart-02076944-f0fc-4bff-ba8c-830e0264ecb7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189369478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3189369478
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2119518567
Short name T916
Test name
Test status
Simulation time 148595722 ps
CPU time 1.28 seconds
Started Jul 01 04:25:31 PM PDT 24
Finished Jul 01 04:25:43 PM PDT 24
Peak memory 197240 kb
Host smart-0fb729eb-ff23-46b1-8cf0-d632aaaa3adc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2119518567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2119518567
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1702396333
Short name T939
Test name
Test status
Simulation time 79910201 ps
CPU time 0.86 seconds
Started Jul 01 04:25:38 PM PDT 24
Finished Jul 01 04:25:49 PM PDT 24
Peak memory 195656 kb
Host smart-b36ca43f-d79a-4443-8403-2215572a535e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702396333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1702396333
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.461668107
Short name T907
Test name
Test status
Simulation time 302715806 ps
CPU time 1 seconds
Started Jul 01 04:25:42 PM PDT 24
Finished Jul 01 04:25:53 PM PDT 24
Peak memory 196172 kb
Host smart-38332950-3371-4191-b25b-a7dda4a461be
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=461668107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.461668107
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.423835551
Short name T925
Test name
Test status
Simulation time 42545296 ps
CPU time 1.12 seconds
Started Jul 01 04:25:51 PM PDT 24
Finished Jul 01 04:26:03 PM PDT 24
Peak memory 196144 kb
Host smart-205015dc-a3f0-4fb1-a560-028a43246355
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423835551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.423835551
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.893097158
Short name T892
Test name
Test status
Simulation time 36618803 ps
CPU time 0.85 seconds
Started Jul 01 04:25:36 PM PDT 24
Finished Jul 01 04:25:47 PM PDT 24
Peak memory 195624 kb
Host smart-34b06713-abbb-48bc-bc51-43fa969ac36f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=893097158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.893097158
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1963152226
Short name T877
Test name
Test status
Simulation time 72552800 ps
CPU time 0.94 seconds
Started Jul 01 04:25:41 PM PDT 24
Finished Jul 01 04:25:52 PM PDT 24
Peak memory 196372 kb
Host smart-6b6b7a34-6a1b-4243-bc01-f97fe78a875d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963152226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1963152226
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.4148092978
Short name T886
Test name
Test status
Simulation time 138235104 ps
CPU time 1.17 seconds
Started Jul 01 04:25:33 PM PDT 24
Finished Jul 01 04:25:45 PM PDT 24
Peak memory 197076 kb
Host smart-c8f3aa0e-9105-480b-905c-df938bf7ec10
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4148092978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.4148092978
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2394541449
Short name T855
Test name
Test status
Simulation time 124572195 ps
CPU time 0.85 seconds
Started Jul 01 04:25:32 PM PDT 24
Finished Jul 01 04:25:44 PM PDT 24
Peak memory 195940 kb
Host smart-90a50981-409e-45f0-af2a-71d0b99beb0f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394541449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2394541449
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2094417027
Short name T931
Test name
Test status
Simulation time 74220188 ps
CPU time 1.16 seconds
Started Jul 01 04:25:37 PM PDT 24
Finished Jul 01 04:25:48 PM PDT 24
Peak memory 197136 kb
Host smart-f640f54b-aae9-490b-a1ee-86711eb31991
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2094417027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.2094417027
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3850039996
Short name T873
Test name
Test status
Simulation time 68321735 ps
CPU time 1.12 seconds
Started Jul 01 04:25:36 PM PDT 24
Finished Jul 01 04:25:47 PM PDT 24
Peak memory 196796 kb
Host smart-f008328e-08d4-40b7-a3eb-0ccde02a85ea
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850039996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3850039996
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1181057447
Short name T930
Test name
Test status
Simulation time 994530775 ps
CPU time 1.34 seconds
Started Jul 01 04:25:23 PM PDT 24
Finished Jul 01 04:25:37 PM PDT 24
Peak memory 197184 kb
Host smart-480c3ed3-8e15-459f-a7ad-a7a598b19318
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1181057447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1181057447
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2186638226
Short name T896
Test name
Test status
Simulation time 150810342 ps
CPU time 1.28 seconds
Started Jul 01 04:25:19 PM PDT 24
Finished Jul 01 04:25:30 PM PDT 24
Peak memory 197052 kb
Host smart-e1730fdb-98ab-4ed1-9c09-01969b75cf2e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186638226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2186638226
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1118888453
Short name T878
Test name
Test status
Simulation time 325176422 ps
CPU time 1.1 seconds
Started Jul 01 04:25:45 PM PDT 24
Finished Jul 01 04:25:57 PM PDT 24
Peak memory 196132 kb
Host smart-4bcdf95c-c86c-4431-9c9c-d46284922e08
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1118888453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1118888453
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.113834351
Short name T908
Test name
Test status
Simulation time 68351503 ps
CPU time 0.75 seconds
Started Jul 01 04:25:27 PM PDT 24
Finished Jul 01 04:25:40 PM PDT 24
Peak memory 196308 kb
Host smart-63946179-c171-4945-8621-e2fdb0d1c831
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113834351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.113834351
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2900036649
Short name T926
Test name
Test status
Simulation time 54929793 ps
CPU time 1.39 seconds
Started Jul 01 04:25:47 PM PDT 24
Finished Jul 01 04:25:59 PM PDT 24
Peak memory 197080 kb
Host smart-25d73bd2-c9a4-4fc3-b86d-05338c32eef3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2900036649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2900036649
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4114320665
Short name T852
Test name
Test status
Simulation time 155951658 ps
CPU time 1.5 seconds
Started Jul 01 04:25:39 PM PDT 24
Finished Jul 01 04:25:50 PM PDT 24
Peak memory 198612 kb
Host smart-640cc9c7-204c-40a7-a27a-744b930a0c09
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114320665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4114320665
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.4119098187
Short name T910
Test name
Test status
Simulation time 143472111 ps
CPU time 1 seconds
Started Jul 01 04:25:45 PM PDT 24
Finished Jul 01 04:25:57 PM PDT 24
Peak memory 196856 kb
Host smart-8b8794ca-ddbd-497a-b7c3-73634e51ade2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4119098187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.4119098187
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1747283529
Short name T911
Test name
Test status
Simulation time 35795719 ps
CPU time 1.06 seconds
Started Jul 01 04:25:36 PM PDT 24
Finished Jul 01 04:25:47 PM PDT 24
Peak memory 196036 kb
Host smart-f4a824cc-4a3c-411d-b627-94fb4dac3795
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747283529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1747283529
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3465550851
Short name T884
Test name
Test status
Simulation time 212644974 ps
CPU time 0.89 seconds
Started Jul 01 04:25:28 PM PDT 24
Finished Jul 01 04:25:41 PM PDT 24
Peak memory 196952 kb
Host smart-c90a0620-fa4e-43f8-a208-80df6cb344e0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3465550851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.3465550851
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2254674910
Short name T893
Test name
Test status
Simulation time 180479361 ps
CPU time 1.26 seconds
Started Jul 01 04:25:47 PM PDT 24
Finished Jul 01 04:25:59 PM PDT 24
Peak memory 197356 kb
Host smart-1d3b7f47-7a73-42ca-83e5-c098b6516871
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254674910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2254674910
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.191372313
Short name T934
Test name
Test status
Simulation time 78398101 ps
CPU time 1.3 seconds
Started Jul 01 04:25:28 PM PDT 24
Finished Jul 01 04:25:42 PM PDT 24
Peak memory 198468 kb
Host smart-c8c8d494-5f26-479b-9524-8edb4b786a52
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=191372313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.191372313
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3358835062
Short name T933
Test name
Test status
Simulation time 143224868 ps
CPU time 1.33 seconds
Started Jul 01 04:25:39 PM PDT 24
Finished Jul 01 04:25:50 PM PDT 24
Peak memory 198252 kb
Host smart-7f623b79-867a-4be7-9c21-e427c0b88605
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358835062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3358835062
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1265585165
Short name T888
Test name
Test status
Simulation time 39920715 ps
CPU time 1.23 seconds
Started Jul 01 04:25:35 PM PDT 24
Finished Jul 01 04:25:47 PM PDT 24
Peak memory 197160 kb
Host smart-cff396f1-4dfd-4c81-a1c1-eccc6fa97828
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1265585165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1265585165
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2705113792
Short name T885
Test name
Test status
Simulation time 213638579 ps
CPU time 1.28 seconds
Started Jul 01 04:25:46 PM PDT 24
Finished Jul 01 04:25:58 PM PDT 24
Peak memory 197064 kb
Host smart-651dd260-d41e-4582-8da3-eea60dcc8b9b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705113792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2705113792
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2370880247
Short name T897
Test name
Test status
Simulation time 182410182 ps
CPU time 1.02 seconds
Started Jul 01 04:25:33 PM PDT 24
Finished Jul 01 04:25:45 PM PDT 24
Peak memory 196972 kb
Host smart-4d524860-1a30-4beb-b8f8-47c473252925
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2370880247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.2370880247
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.327887845
Short name T875
Test name
Test status
Simulation time 311815653 ps
CPU time 1.11 seconds
Started Jul 01 04:25:24 PM PDT 24
Finished Jul 01 04:25:37 PM PDT 24
Peak memory 196980 kb
Host smart-18288245-5ab8-4e47-9eed-68f2918c8d83
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327887845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.327887845
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1096027878
Short name T880
Test name
Test status
Simulation time 241846834 ps
CPU time 0.75 seconds
Started Jul 01 04:25:19 PM PDT 24
Finished Jul 01 04:25:30 PM PDT 24
Peak memory 196356 kb
Host smart-cf87d133-787b-4686-b5e2-9f71ab0cf8e7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1096027878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.1096027878
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.828316373
Short name T922
Test name
Test status
Simulation time 79352214 ps
CPU time 1.11 seconds
Started Jul 01 04:25:24 PM PDT 24
Finished Jul 01 04:25:38 PM PDT 24
Peak memory 196184 kb
Host smart-36f3b448-6b4b-4237-835c-2b5b973bc0ab
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828316373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.828316373
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1258698708
Short name T882
Test name
Test status
Simulation time 33713173 ps
CPU time 0.92 seconds
Started Jul 01 04:25:36 PM PDT 24
Finished Jul 01 04:25:47 PM PDT 24
Peak memory 196904 kb
Host smart-5f2475f2-f776-4555-ab7f-8153c17216d5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1258698708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1258698708
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4191937560
Short name T946
Test name
Test status
Simulation time 50293750 ps
CPU time 1.08 seconds
Started Jul 01 04:25:20 PM PDT 24
Finished Jul 01 04:25:31 PM PDT 24
Peak memory 197068 kb
Host smart-0397235d-8b0a-42f9-ac27-e7541c123e83
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191937560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4191937560
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1975383365
Short name T903
Test name
Test status
Simulation time 111284765 ps
CPU time 1.04 seconds
Started Jul 01 04:25:26 PM PDT 24
Finished Jul 01 04:25:40 PM PDT 24
Peak memory 196780 kb
Host smart-48abf229-0e83-4c50-95b3-f72f67856738
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1975383365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1975383365
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2705712816
Short name T889
Test name
Test status
Simulation time 51560378 ps
CPU time 1.33 seconds
Started Jul 01 04:25:29 PM PDT 24
Finished Jul 01 04:25:42 PM PDT 24
Peak memory 197640 kb
Host smart-c2fdf0a4-aec5-4784-af04-a1fc3e733a45
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705712816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2705712816
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3625543681
Short name T858
Test name
Test status
Simulation time 67990656 ps
CPU time 1.08 seconds
Started Jul 01 04:25:46 PM PDT 24
Finished Jul 01 04:25:58 PM PDT 24
Peak memory 196784 kb
Host smart-6b973129-d637-41df-a0b1-6afade062b7a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3625543681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.3625543681
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.594372728
Short name T943
Test name
Test status
Simulation time 53112481 ps
CPU time 1.05 seconds
Started Jul 01 04:25:18 PM PDT 24
Finished Jul 01 04:25:28 PM PDT 24
Peak memory 194504 kb
Host smart-0694bc89-d7d0-4429-8e50-b3f56e706b02
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594372728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.594372728
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3747939443
Short name T941
Test name
Test status
Simulation time 237046876 ps
CPU time 1.08 seconds
Started Jul 01 04:25:21 PM PDT 24
Finished Jul 01 04:25:33 PM PDT 24
Peak memory 196020 kb
Host smart-3e5d65e6-c480-4130-8f4b-9d1e77f297a6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3747939443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3747939443
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3790429812
Short name T894
Test name
Test status
Simulation time 273278834 ps
CPU time 1.17 seconds
Started Jul 01 04:25:30 PM PDT 24
Finished Jul 01 04:25:42 PM PDT 24
Peak memory 197024 kb
Host smart-48503522-78e5-44b4-b6f7-5710d787f85a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790429812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3790429812
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.4185335154
Short name T887
Test name
Test status
Simulation time 104829018 ps
CPU time 1.01 seconds
Started Jul 01 04:25:32 PM PDT 24
Finished Jul 01 04:25:44 PM PDT 24
Peak memory 196752 kb
Host smart-5bad3bc4-a383-4e09-aa51-da4d3ca92b5c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4185335154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.4185335154
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2509384932
Short name T936
Test name
Test status
Simulation time 187941880 ps
CPU time 1.08 seconds
Started Jul 01 04:25:41 PM PDT 24
Finished Jul 01 04:25:52 PM PDT 24
Peak memory 196772 kb
Host smart-1794d2a6-9296-4b97-9641-ab7e8a69c85a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509384932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2509384932
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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