Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4004646	1			T24	1		T25	1		T26	1
all_pins[1]	4004646	1			T24	1		T25	1		T26	1
all_pins[2]	4004646	1			T24	1		T25	1		T26	1
all_pins[3]	4004646	1			T24	1		T25	1		T26	1
all_pins[4]	4004646	1			T24	1		T25	1		T26	1
all_pins[5]	4004646	1			T24	1		T25	1		T26	1
all_pins[6]	4004646	1			T24	1		T25	1		T26	1
all_pins[7]	4004646	1			T24	1		T25	1		T26	1
all_pins[8]	4004646	1			T24	1		T25	1		T26	1
all_pins[9]	4004646	1			T24	1		T25	1		T26	1
all_pins[10]	4004646	1			T24	1		T25	1		T26	1
all_pins[11]	4004646	1			T24	1		T25	1		T26	1
all_pins[12]	4004646	1			T24	1		T25	1		T26	1
all_pins[13]	4004646	1			T24	1		T25	1		T26	1
all_pins[14]	4004646	1			T24	1		T25	1		T26	1
all_pins[15]	4004646	1			T24	1		T25	1		T26	1
all_pins[16]	4004646	1			T24	1		T25	1		T26	1
all_pins[17]	4004646	1			T24	1		T25	1		T26	1
all_pins[18]	4004646	1			T24	1		T25	1		T26	1
all_pins[19]	4004646	1			T24	1		T25	1		T26	1
all_pins[20]	4004646	1			T24	1		T25	1		T26	1
all_pins[21]	4004646	1			T24	1		T25	1		T26	1
all_pins[22]	4004646	1			T24	1		T25	1		T26	1
all_pins[23]	4004646	1			T24	1		T25	1		T26	1
all_pins[24]	4004646	1			T24	1		T25	1		T26	1
all_pins[25]	4004646	1			T24	1		T25	1		T26	1
all_pins[26]	4004646	1			T24	1		T25	1		T26	1
all_pins[27]	4004646	1			T24	1		T25	1		T26	1
all_pins[28]	4004646	1			T24	1		T25	1		T26	1
all_pins[29]	4004646	1			T24	1		T25	1		T26	1
all_pins[30]	4004646	1			T24	1		T25	1		T26	1
all_pins[31]	4004646	1			T24	1		T25	1		T26	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	79616515	1			T24	32		T25	32		T26	32
values[0x1]	48532157	1			T1	300916		T2	6194		T12	5892
transitions[0x0=>0x1]	29077689	1			T1	179659		T2	3720		T12	3582
transitions[0x1=>0x0]	29077538	1			T1	179658		T2	3720		T12	3581

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2490508	1			T24	1		T25	1		T26	1
all_pins[0]	values[0x1]	1514138	1			T1	9593		T2	195		T12	182
all_pins[0]	transitions[0x0=>0x1]	939010	1			T1	5940		T2	116		T12	111
all_pins[0]	transitions[0x1=>0x0]	939623	1			T1	5896		T2	135		T12	103
all_pins[1]	values[0x0]	2493671	1			T24	1		T25	1		T26	1
all_pins[1]	values[0x1]	1510975	1			T1	9415		T2	201		T12	291
all_pins[1]	transitions[0x0=>0x1]	905292	1			T1	5627		T2	109		T12	182
all_pins[1]	transitions[0x1=>0x0]	908455	1			T1	5805		T2	103		T12	73
all_pins[2]	values[0x0]	2487704	1			T24	1		T25	1		T26	1
all_pins[2]	values[0x1]	1516942	1			T1	9054		T2	171		T12	183
all_pins[2]	transitions[0x0=>0x1]	911884	1			T1	5486		T2	105		T12	85
all_pins[2]	transitions[0x1=>0x0]	905917	1			T1	5847		T2	135		T12	193
all_pins[3]	values[0x0]	2494702	1			T24	1		T25	1		T26	1
all_pins[3]	values[0x1]	1509944	1			T1	9785		T2	206		T12	204
all_pins[3]	transitions[0x0=>0x1]	901899	1			T1	5984		T2	146		T12	132
all_pins[3]	transitions[0x1=>0x0]	908897	1			T1	5253		T2	111		T12	111
all_pins[4]	values[0x0]	2486898	1			T24	1		T25	1		T26	1
all_pins[4]	values[0x1]	1517748	1			T1	9661		T2	177		T12	139
all_pins[4]	transitions[0x0=>0x1]	910559	1			T1	5611		T2	125		T12	98
all_pins[4]	transitions[0x1=>0x0]	902755	1			T1	5735		T2	154		T12	163
all_pins[5]	values[0x0]	2487898	1			T24	1		T25	1		T26	1
all_pins[5]	values[0x1]	1516748	1			T1	9039		T2	214		T12	173
all_pins[5]	transitions[0x0=>0x1]	907288	1			T1	5398		T2	137		T12	123
all_pins[5]	transitions[0x1=>0x0]	908288	1			T1	6020		T2	100		T12	89
all_pins[6]	values[0x0]	2486732	1			T24	1		T25	1		T26	1
all_pins[6]	values[0x1]	1517914	1			T1	9709		T2	209		T12	206
all_pins[6]	transitions[0x0=>0x1]	906926	1			T1	5679		T2	134		T12	105
all_pins[6]	transitions[0x1=>0x0]	905760	1			T1	5009		T2	139		T12	72
all_pins[7]	values[0x0]	2489789	1			T24	1		T25	1		T26	1
all_pins[7]	values[0x1]	1514857	1			T1	9443		T2	247		T12	138
all_pins[7]	transitions[0x0=>0x1]	906184	1			T1	5580		T2	140		T12	71
all_pins[7]	transitions[0x1=>0x0]	909241	1			T1	5846		T2	102		T12	139
all_pins[8]	values[0x0]	2485946	1			T24	1		T25	1		T26	1
all_pins[8]	values[0x1]	1518700	1			T1	9430		T2	170		T12	224
all_pins[8]	transitions[0x0=>0x1]	909802	1			T1	5486		T2	97		T12	151
all_pins[8]	transitions[0x1=>0x0]	905959	1			T1	5499		T2	174		T12	65
all_pins[9]	values[0x0]	2487579	1			T24	1		T25	1		T26	1
all_pins[9]	values[0x1]	1517067	1			T1	9232		T2	156		T12	194
all_pins[9]	transitions[0x0=>0x1]	908982	1			T1	5570		T2	93		T12	107
all_pins[9]	transitions[0x1=>0x0]	910615	1			T1	5768		T2	107		T12	137
all_pins[10]	values[0x0]	2490107	1			T24	1		T25	1		T26	1
all_pins[10]	values[0x1]	1514539	1			T1	9306		T2	190		T12	212
all_pins[10]	transitions[0x0=>0x1]	905660	1			T1	5636		T2	132		T12	105
all_pins[10]	transitions[0x1=>0x0]	908188	1			T1	5562		T2	98		T12	87
all_pins[11]	values[0x0]	2488200	1			T24	1		T25	1		T26	1
all_pins[11]	values[0x1]	1516446	1			T1	9662		T2	215		T12	131
all_pins[11]	transitions[0x0=>0x1]	907445	1			T1	5785		T2	125		T12	82
all_pins[11]	transitions[0x1=>0x0]	905538	1			T1	5429		T2	100		T12	163
all_pins[12]	values[0x0]	2487603	1			T24	1		T25	1		T26	1
all_pins[12]	values[0x1]	1517043	1			T1	9769		T2	199		T12	218
all_pins[12]	transitions[0x0=>0x1]	908301	1			T1	5712		T2	112		T12	171
all_pins[12]	transitions[0x1=>0x0]	907704	1			T1	5605		T2	128		T12	84
all_pins[13]	values[0x0]	2488219	1			T24	1		T25	1		T26	1
all_pins[13]	values[0x1]	1516427	1			T1	9297		T2	217		T12	187
all_pins[13]	transitions[0x0=>0x1]	906622	1			T1	5379		T2	124		T12	89
all_pins[13]	transitions[0x1=>0x0]	907238	1			T1	5851		T2	106		T12	120
all_pins[14]	values[0x0]	2489208	1			T24	1		T25	1		T26	1
all_pins[14]	values[0x1]	1515438	1			T1	9584		T2	204		T12	186
all_pins[14]	transitions[0x0=>0x1]	908879	1			T1	5943		T2	114		T12	118
all_pins[14]	transitions[0x1=>0x0]	909868	1			T1	5656		T2	127		T12	119
all_pins[15]	values[0x0]	2489314	1			T24	1		T25	1		T26	1
all_pins[15]	values[0x1]	1515332	1			T1	9542		T2	162		T12	136
all_pins[15]	transitions[0x0=>0x1]	908691	1			T1	5603		T2	91		T12	101
all_pins[15]	transitions[0x1=>0x0]	908797	1			T1	5645		T2	133		T12	151
all_pins[16]	values[0x0]	2482762	1			T24	1		T25	1		T26	1
all_pins[16]	values[0x1]	1521884	1			T1	9168		T2	211		T12	238
all_pins[16]	transitions[0x0=>0x1]	911976	1			T1	5393		T2	153		T12	147
all_pins[16]	transitions[0x1=>0x0]	905424	1			T1	5767		T2	104		T12	45
all_pins[17]	values[0x0]	2490443	1			T24	1		T25	1		T26	1
all_pins[17]	values[0x1]	1514203	1			T1	9515		T2	182		T12	149
all_pins[17]	transitions[0x0=>0x1]	904375	1			T1	5736		T2	84		T12	97
all_pins[17]	transitions[0x1=>0x0]	912056	1			T1	5389		T2	113		T12	186
all_pins[18]	values[0x0]	2487993	1			T24	1		T25	1		T26	1
all_pins[18]	values[0x1]	1516653	1			T1	9368		T2	177		T12	207
all_pins[18]	transitions[0x0=>0x1]	907552	1			T1	5668		T2	91		T12	154
all_pins[18]	transitions[0x1=>0x0]	905102	1			T1	5815		T2	96		T12	96
all_pins[19]	values[0x0]	2485718	1			T24	1		T25	1		T26	1
all_pins[19]	values[0x1]	1518928	1			T1	9162		T2	172		T12	204
all_pins[19]	transitions[0x0=>0x1]	908916	1			T1	5446		T2	110		T12	142
all_pins[19]	transitions[0x1=>0x0]	906641	1			T1	5652		T2	115		T12	145
all_pins[20]	values[0x0]	2489680	1			T24	1		T25	1		T26	1
all_pins[20]	values[0x1]	1514966	1			T1	9543		T2	190		T12	220
all_pins[20]	transitions[0x0=>0x1]	906031	1			T1	5740		T2	119		T12	115
all_pins[20]	transitions[0x1=>0x0]	909993	1			T1	5359		T2	101		T12	99
all_pins[21]	values[0x0]	2489040	1			T24	1		T25	1		T26	1
all_pins[21]	values[0x1]	1515606	1			T1	9319		T2	222		T12	209
all_pins[21]	transitions[0x0=>0x1]	904881	1			T1	5513		T2	137		T12	84
all_pins[21]	transitions[0x1=>0x0]	904241	1			T1	5737		T2	105		T12	95
all_pins[22]	values[0x0]	2488406	1			T24	1		T25	1		T26	1
all_pins[22]	values[0x1]	1516240	1			T1	9426		T2	182		T12	162
all_pins[22]	transitions[0x0=>0x1]	909583	1			T1	5710		T2	118		T12	116
all_pins[22]	transitions[0x1=>0x0]	908949	1			T1	5603		T2	158		T12	163
all_pins[23]	values[0x0]	2487970	1			T24	1		T25	1		T26	1
all_pins[23]	values[0x1]	1516676	1			T1	9027		T2	187		T12	174
all_pins[23]	transitions[0x0=>0x1]	907961	1			T1	5264		T2	111		T12	102
all_pins[23]	transitions[0x1=>0x0]	907525	1			T1	5663		T2	106		T12	90
all_pins[24]	values[0x0]	2487646	1			T24	1		T25	1		T26	1
all_pins[24]	values[0x1]	1517000	1			T1	9213		T2	191		T12	125
all_pins[24]	transitions[0x0=>0x1]	908940	1			T1	5530		T2	121		T12	66
all_pins[24]	transitions[0x1=>0x0]	908616	1			T1	5344		T2	117		T12	115
all_pins[25]	values[0x0]	2488065	1			T24	1		T25	1		T26	1
all_pins[25]	values[0x1]	1516581	1			T1	9316		T2	204		T12	152
all_pins[25]	transitions[0x0=>0x1]	909423	1			T1	5733		T2	108		T12	131
all_pins[25]	transitions[0x1=>0x0]	909842	1			T1	5630		T2	95		T12	104
all_pins[26]	values[0x0]	2482870	1			T24	1		T25	1		T26	1
all_pins[26]	values[0x1]	1521776	1			T1	9360		T2	174		T12	160
all_pins[26]	transitions[0x0=>0x1]	910328	1			T1	5686		T2	100		T12	84
all_pins[26]	transitions[0x1=>0x0]	905133	1			T1	5642		T2	130		T12	76
all_pins[27]	values[0x0]	2481968	1			T24	1		T25	1		T26	1
all_pins[27]	values[0x1]	1522678	1			T1	9302		T2	187		T12	182
all_pins[27]	transitions[0x0=>0x1]	908318	1			T1	5529		T2	110		T12	102
all_pins[27]	transitions[0x1=>0x0]	907416	1			T1	5587		T2	97		T12	80
all_pins[28]	values[0x0]	2489093	1			T24	1		T25	1		T26	1
all_pins[28]	values[0x1]	1515553	1			T1	9322		T2	186		T12	200
all_pins[28]	transitions[0x0=>0x1]	902932	1			T1	5522		T2	116		T12	110
all_pins[28]	transitions[0x1=>0x0]	910057	1			T1	5502		T2	117		T12	92
all_pins[29]	values[0x0]	2488029	1			T24	1		T25	1		T26	1
all_pins[29]	values[0x1]	1516617	1			T1	9642		T2	184		T12	116
all_pins[29]	transitions[0x0=>0x1]	908261	1			T1	5714		T2	113		T12	53
all_pins[29]	transitions[0x1=>0x0]	907197	1			T1	5394		T2	115		T12	137
all_pins[30]	values[0x0]	2483010	1			T24	1		T25	1		T26	1
all_pins[30]	values[0x1]	1521636	1			T1	9162		T2	198		T12	215
all_pins[30]	transitions[0x0=>0x1]	911631	1			T1	5332		T2	113		T12	143
all_pins[30]	transitions[0x1=>0x0]	906612	1			T1	5812		T2	99		T12	44
all_pins[31]	values[0x0]	2489744	1			T24	1		T25	1		T26	1
all_pins[31]	values[0x1]	1514902	1			T1	9550		T2	214		T12	175
all_pins[31]	transitions[0x0=>0x1]	903157	1			T1	5724		T2	116		T12	105
all_pins[31]	transitions[0x1=>0x0]	909891	1			T1	5336		T2	100		T12	145