Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	13600958	1			T24	1		T25	258		T26	212
all_values[1]	13600958	1			T24	1		T25	258		T26	212
all_values[2]	13600958	1			T24	1		T25	258		T26	212
all_values[3]	13600958	1			T24	1		T25	258		T26	212
all_values[4]	13600958	1			T24	1		T25	258		T26	212
all_values[5]	13600958	1			T24	1		T25	258		T26	212
all_values[6]	13600958	1			T24	1		T25	258		T26	212
all_values[7]	13600958	1			T24	1		T25	258		T26	212
all_values[8]	13600958	1			T24	1		T25	258		T26	212
all_values[9]	13600958	1			T24	1		T25	258		T26	212
all_values[10]	13600958	1			T24	1		T25	258		T26	212
all_values[11]	13600958	1			T24	1		T25	258		T26	212
all_values[12]	13600958	1			T24	1		T25	258		T26	212
all_values[13]	13600958	1			T24	1		T25	258		T26	212
all_values[14]	13600958	1			T24	1		T25	258		T26	212
all_values[15]	13600958	1			T24	1		T25	258		T26	212
all_values[16]	13600958	1			T24	1		T25	258		T26	212
all_values[17]	13600958	1			T24	1		T25	258		T26	212
all_values[18]	13600958	1			T24	1		T25	258		T26	212
all_values[19]	13600958	1			T24	1		T25	258		T26	212
all_values[20]	13600958	1			T24	1		T25	258		T26	212
all_values[21]	13600958	1			T24	1		T25	258		T26	212
all_values[22]	13600958	1			T24	1		T25	258		T26	212
all_values[23]	13600958	1			T24	1		T25	258		T26	212
all_values[24]	13600958	1			T24	1		T25	258		T26	212
all_values[25]	13600958	1			T24	1		T25	258		T26	212
all_values[26]	13600958	1			T24	1		T25	258		T26	212
all_values[27]	13600958	1			T24	1		T25	258		T26	212
all_values[28]	13600958	1			T24	1		T25	258		T26	212
all_values[29]	13600958	1			T24	1		T25	258		T26	212
all_values[30]	13600958	1			T24	1		T25	258		T26	212
all_values[31]	13600958	1			T24	1		T25	258		T26	212

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

254586558

1

T24

32

T25

8256

T26

6784

auto[1]

180644098

1

T1

111760

T2

24161

T12

22293

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

108264071

1

T24

32

T25

8256

T26

6784

auto[1]

326966585

1

T1

202940

T2

42876

T12

40881

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

430534604

1

T24

32

T25

8256

T26

6784

auto[1]

4696052

1

T1

26564

T2

1729

T14

98

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2839075	1			T24	1		T25	258		T26	212
all_values[0]	auto[0]	auto[0]	auto[1]	5055313	1			T1	30508		T2	609		T12	707
all_values[0]	auto[0]	auto[1]	auto[0]	547269	1			T1	3581		T2	121		T12	56
all_values[0]	auto[0]	auto[1]	auto[1]	5012857	1			T1	32000		T2	658		T12	534
all_values[0]	auto[1]	auto[0]	auto[1]	73698	1			T1	387		T2	20		T14	1
all_values[0]	auto[1]	auto[1]	auto[1]	72746	1			T1	451		T2	23		T14	1
all_values[1]	auto[0]	auto[0]	auto[0]	2837801	1			T24	1		T25	258		T26	212
all_values[1]	auto[0]	auto[0]	auto[1]	5059228	1			T1	31580		T2	523		T12	276
all_values[1]	auto[0]	auto[1]	auto[0]	544945	1			T1	3555		T2	92		T12	158
all_values[1]	auto[0]	auto[1]	auto[1]	5012406	1			T1	30435		T2	768		T12	908
all_values[1]	auto[1]	auto[0]	auto[1]	73576	1			T1	415		T2	23		T14	2
all_values[1]	auto[1]	auto[1]	auto[1]	73002	1			T1	377		T2	29		T14	1
all_values[2]	auto[0]	auto[0]	auto[0]	2844043	1			T24	1		T25	258		T26	212
all_values[2]	auto[0]	auto[0]	auto[1]	5047791	1			T1	32340		T2	648		T12	681
all_values[2]	auto[0]	auto[1]	auto[0]	547238	1			T1	3493		T2	72		T12	69
all_values[2]	auto[0]	auto[1]	auto[1]	5014655	1			T1	30157		T2	561		T12	613
all_values[2]	auto[1]	auto[0]	auto[1]	73784	1			T1	415		T2	33		T14	1
all_values[2]	auto[1]	auto[1]	auto[1]	73447	1			T1	408		T2	23		T14	1
all_values[3]	auto[0]	auto[0]	auto[0]	2837215	1			T24	1		T25	258		T26	212
all_values[3]	auto[0]	auto[0]	auto[1]	5079029	1			T1	29454		T2	511		T12	705
all_values[3]	auto[0]	auto[1]	auto[0]	548052	1			T1	3241		T2	89		T12	30
all_values[3]	auto[0]	auto[1]	auto[1]	4989810	1			T1	33536		T2	756		T12	633
all_values[3]	auto[1]	auto[0]	auto[1]	73655	1			T1	419		T2	26		T14	3
all_values[3]	auto[1]	auto[1]	auto[1]	73197	1			T1	414		T2	32		T14	1
all_values[4]	auto[0]	auto[0]	auto[0]	2831759	1			T24	1		T25	258		T26	212
all_values[4]	auto[0]	auto[0]	auto[1]	5048596	1			T1	30038		T2	777		T12	766
all_values[4]	auto[0]	auto[1]	auto[0]	547758	1			T1	3436		T2	71		T12	79
all_values[4]	auto[0]	auto[1]	auto[1]	5026088	1			T1	32754		T2	517		T12	517
all_values[4]	auto[1]	auto[0]	auto[1]	73291	1			T1	400		T2	36		T14	1
all_values[4]	auto[1]	auto[1]	auto[1]	73466	1			T1	396		T2	23		T15	356
all_values[5]	auto[0]	auto[0]	auto[0]	2834178	1			T24	1		T25	258		T26	212
all_values[5]	auto[0]	auto[0]	auto[1]	5027735	1			T1	31698		T2	693		T12	757
all_values[5]	auto[0]	auto[1]	auto[0]	552494	1			T1	3259		T2	50		T12	42
all_values[5]	auto[0]	auto[1]	auto[1]	5040244	1			T1	30454		T2	630		T12	555
all_values[5]	auto[1]	auto[0]	auto[1]	73489	1			T1	399		T2	28		T14	2
all_values[5]	auto[1]	auto[1]	auto[1]	72818	1			T1	430		T2	22		T14	1
all_values[6]	auto[0]	auto[0]	auto[0]	2841822	1			T24	1		T25	258		T26	212
all_values[6]	auto[0]	auto[0]	auto[1]	5056175	1			T1	31206		T2	514		T12	586
all_values[6]	auto[0]	auto[1]	auto[0]	542987	1			T1	3231		T2	91		T12	56
all_values[6]	auto[0]	auto[1]	auto[1]	5013132	1			T1	31785		T2	744		T12	680
all_values[6]	auto[1]	auto[0]	auto[1]	72823	1			T1	406		T2	26		T14	2
all_values[6]	auto[1]	auto[1]	auto[1]	74019	1			T1	453		T2	31		T14	1
all_values[7]	auto[0]	auto[0]	auto[0]	2832275	1			T24	1		T25	258		T26	212
all_values[7]	auto[0]	auto[0]	auto[1]	5046244	1			T1	31131		T2	453		T12	813
all_values[7]	auto[0]	auto[1]	auto[0]	545670	1			T1	3718		T2	114		T12	112
all_values[7]	auto[0]	auto[1]	auto[1]	5029843	1			T1	30716		T2	831		T12	434
all_values[7]	auto[1]	auto[0]	auto[1]	73927	1			T1	411		T2	18		T14	3
all_values[7]	auto[1]	auto[1]	auto[1]	72999	1			T1	395		T2	36		T14	1
all_values[8]	auto[0]	auto[0]	auto[0]	2833081	1			T24	1		T25	258		T26	212
all_values[8]	auto[0]	auto[0]	auto[1]	5050380	1			T1	31011		T2	643		T12	618
all_values[8]	auto[0]	auto[1]	auto[0]	536863	1			T1	3406		T2	119		T12	29
all_values[8]	auto[0]	auto[1]	auto[1]	5033994	1			T1	31425		T2	584		T12	743
all_values[8]	auto[1]	auto[0]	auto[1]	73505	1			T1	421		T2	19		T14	4
all_values[8]	auto[1]	auto[1]	auto[1]	73135	1			T1	435		T2	28		T14	1
all_values[9]	auto[0]	auto[0]	auto[0]	2829791	1			T24	1		T25	258		T26	212
all_values[9]	auto[0]	auto[0]	auto[1]	5049767	1			T1	31524		T2	795		T12	677
all_values[9]	auto[0]	auto[1]	auto[0]	550450	1			T1	3425		T2	57		T12	80
all_values[9]	auto[0]	auto[1]	auto[1]	5024319	1			T1	31065		T2	507		T12	610
all_values[9]	auto[1]	auto[0]	auto[1]	73690	1			T1	408		T2	34		T14	1
all_values[9]	auto[1]	auto[1]	auto[1]	72941	1			T1	403		T2	21		T14	2
all_values[10]	auto[0]	auto[0]	auto[0]	2837656	1			T24	1		T25	258		T26	212
all_values[10]	auto[0]	auto[0]	auto[1]	5041778	1			T1	32355		T2	683		T12	547
all_values[10]	auto[0]	auto[1]	auto[0]	553039	1			T1	3220		T2	82		T12	90
all_values[10]	auto[0]	auto[1]	auto[1]	5021693	1			T1	30589		T2	600		T12	716
all_values[10]	auto[1]	auto[0]	auto[1]	73537	1			T1	404		T2	29		T14	1
all_values[10]	auto[1]	auto[1]	auto[1]	73255	1			T1	432		T2	25		T15	326
all_values[11]	auto[0]	auto[0]	auto[0]	2833204	1			T24	1		T25	258		T26	212
all_values[11]	auto[0]	auto[0]	auto[1]	5067967	1			T1	30250		T2	649		T12	749
all_values[11]	auto[0]	auto[1]	auto[0]	546287	1			T1	3394		T2	59		T12	80
all_values[11]	auto[0]	auto[1]	auto[1]	5006925	1			T1	32548		T2	678		T12	484
all_values[11]	auto[1]	auto[0]	auto[1]	73182	1			T1	417		T2	28		T14	1
all_values[11]	auto[1]	auto[1]	auto[1]	73393	1			T1	419		T2	27		T14	2
all_values[12]	auto[0]	auto[0]	auto[0]	2829211	1			T24	1		T25	258		T26	212
all_values[12]	auto[0]	auto[0]	auto[1]	5044013	1			T1	29768		T2	648		T12	433
all_values[12]	auto[0]	auto[1]	auto[0]	552175	1			T1	3574		T2	53		T12	183
all_values[12]	auto[0]	auto[1]	auto[1]	5028877	1			T1	32530		T2	644		T12	777
all_values[12]	auto[1]	auto[0]	auto[1]	73141	1			T1	371		T2	37		T14	3
all_values[12]	auto[1]	auto[1]	auto[1]	73541	1			T1	453		T2	22		T15	309
all_values[13]	auto[0]	auto[0]	auto[0]	2834077	1			T24	1		T25	258		T26	212
all_values[13]	auto[0]	auto[0]	auto[1]	5042533	1			T1	32147		T2	560		T12	677
all_values[13]	auto[0]	auto[1]	auto[0]	553966	1			T1	3328		T2	57		T12	69
all_values[13]	auto[0]	auto[1]	auto[1]	5023689	1			T1	30704		T2	765		T12	597
all_values[13]	auto[1]	auto[0]	auto[1]	73329	1			T1	422		T2	24		T14	1
all_values[13]	auto[1]	auto[1]	auto[1]	73364	1			T1	394		T2	31		T14	2
all_values[14]	auto[0]	auto[0]	auto[0]	2840842	1			T24	1		T25	258		T26	212
all_values[14]	auto[0]	auto[0]	auto[1]	5040207	1			T1	31253		T2	720		T12	569
all_values[14]	auto[0]	auto[1]	auto[0]	549328	1			T1	3065		T2	45		T12	109
all_values[14]	auto[0]	auto[1]	auto[1]	5023627	1			T1	31265		T2	598		T12	659
all_values[14]	auto[1]	auto[0]	auto[1]	74143	1			T1	405		T2	33		T14	2
all_values[14]	auto[1]	auto[1]	auto[1]	72811	1			T1	437		T2	27		T14	2
all_values[15]	auto[0]	auto[0]	auto[0]	2834670	1			T24	1		T25	258		T26	212
all_values[15]	auto[0]	auto[0]	auto[1]	5044648	1			T1	32014		T2	793		T12	772
all_values[15]	auto[0]	auto[1]	auto[0]	550086	1			T1	3217		T2	50		T12	42
all_values[15]	auto[0]	auto[1]	auto[1]	5024607	1			T1	30540		T2	535		T12	504
all_values[15]	auto[1]	auto[0]	auto[1]	73217	1			T1	400		T2	32		T14	1
all_values[15]	auto[1]	auto[1]	auto[1]	73730	1			T1	440		T2	24		T14	2
all_values[16]	auto[0]	auto[0]	auto[0]	2832427	1			T24	1		T25	258		T26	212
all_values[16]	auto[0]	auto[0]	auto[1]	5048062	1			T1	31800		T2	587		T12	545
all_values[16]	auto[0]	auto[1]	auto[0]	546927	1			T1	3625		T2	78		T12	105
all_values[16]	auto[0]	auto[1]	auto[1]	5026558	1			T1	30289		T2	698		T12	727
all_values[16]	auto[1]	auto[0]	auto[1]	73253	1			T1	398		T2	23		T14	1
all_values[16]	auto[1]	auto[1]	auto[1]	73731	1			T1	426		T2	27		T14	1
all_values[17]	auto[0]	auto[0]	auto[0]	2829691	1			T24	1		T25	258		T26	212
all_values[17]	auto[0]	auto[0]	auto[1]	5066988	1			T1	31594		T2	622		T12	857
all_values[17]	auto[0]	auto[1]	auto[0]	549223	1			T1	3246		T2	71		T12	14
all_values[17]	auto[0]	auto[1]	auto[1]	5008136	1			T1	31504		T2	668		T12	511
all_values[17]	auto[1]	auto[0]	auto[1]	73910	1			T1	394		T2	26		T14	3
all_values[17]	auto[1]	auto[1]	auto[1]	73010	1			T1	427		T2	37		T15	305
all_values[18]	auto[0]	auto[0]	auto[0]	2840069	1			T24	1		T25	258		T26	212
all_values[18]	auto[0]	auto[0]	auto[1]	5040085	1			T1	32552		T2	717		T12	560
all_values[18]	auto[0]	auto[1]	auto[0]	548630	1			T1	3327		T2	87		T12	42
all_values[18]	auto[0]	auto[1]	auto[1]	5025815	1			T1	30356		T2	541		T12	730
all_values[18]	auto[1]	auto[0]	auto[1]	72884	1			T1	441		T2	38		T14	2
all_values[18]	auto[1]	auto[1]	auto[1]	73475	1			T1	396		T2	18		T14	1
all_values[19]	auto[0]	auto[0]	auto[0]	2842239	1			T24	1		T25	258		T26	212
all_values[19]	auto[0]	auto[0]	auto[1]	5062491	1			T1	32523		T2	598		T12	621
all_values[19]	auto[0]	auto[1]	auto[0]	555045	1			T1	3332		T2	82		T12	97
all_values[19]	auto[0]	auto[1]	auto[1]	4994329	1			T1	30151		T2	641		T12	655
all_values[19]	auto[1]	auto[0]	auto[1]	73838	1			T1	404		T2	23		T15	337
all_values[19]	auto[1]	auto[1]	auto[1]	73016	1			T1	412		T2	27		T15	322
all_values[20]	auto[0]	auto[0]	auto[0]	2833311	1			T24	1		T25	258		T26	212
all_values[20]	auto[0]	auto[0]	auto[1]	5041821	1			T1	30232		T2	624		T12	606
all_values[20]	auto[0]	auto[1]	auto[0]	549805	1			T1	3733		T2	49		T12	36
all_values[20]	auto[0]	auto[1]	auto[1]	5029208	1			T1	32195		T2	655		T12	729
all_values[20]	auto[1]	auto[0]	auto[1]	73561	1			T1	389		T2	25		T14	1
all_values[20]	auto[1]	auto[1]	auto[1]	73252	1			T1	405		T2	32		T14	3
all_values[21]	auto[0]	auto[0]	auto[0]	2836428	1			T24	1		T25	258		T26	212
all_values[21]	auto[0]	auto[0]	auto[1]	5027366	1			T1	31738		T2	629		T12	514
all_values[21]	auto[0]	auto[1]	auto[0]	549452	1			T1	3243		T2	98		T12	106
all_values[21]	auto[0]	auto[1]	auto[1]	5041260	1			T1	31069		T2	676		T12	743
all_values[21]	auto[1]	auto[0]	auto[1]	73051	1			T1	452		T2	26		T14	2
all_values[21]	auto[1]	auto[1]	auto[1]	73401	1			T1	435		T2	28		T15	309
all_values[22]	auto[0]	auto[0]	auto[0]	2838412	1			T24	1		T25	258		T26	212
all_values[22]	auto[0]	auto[0]	auto[1]	5048148	1			T1	33040		T2	723		T12	854
all_values[22]	auto[0]	auto[1]	auto[0]	546662	1			T1	3359		T2	61		T12	47
all_values[22]	auto[0]	auto[1]	auto[1]	5020968	1			T1	29562		T2	588		T12	462
all_values[22]	auto[1]	auto[0]	auto[1]	73846	1			T1	441		T2	32		T14	2
all_values[22]	auto[1]	auto[1]	auto[1]	72922	1			T1	399		T2	26		T14	1
all_values[23]	auto[0]	auto[0]	auto[0]	2837572	1			T24	1		T25	258		T26	212
all_values[23]	auto[0]	auto[0]	auto[1]	5009557	1			T1	33537		T2	629		T12	511
all_values[23]	auto[0]	auto[1]	auto[0]	548321	1			T1	3412		T2	95		T12	130
all_values[23]	auto[0]	auto[1]	auto[1]	5058650	1			T1	29322		T2	634		T12	621
all_values[23]	auto[1]	auto[0]	auto[1]	73515	1			T1	438		T2	27		T14	3
all_values[23]	auto[1]	auto[1]	auto[1]	73343	1			T1	404		T2	25		T15	352
all_values[24]	auto[0]	auto[0]	auto[0]	2827874	1			T24	1		T25	258		T26	212
all_values[24]	auto[0]	auto[0]	auto[1]	5072243	1			T1	32007		T2	644		T12	814
all_values[24]	auto[0]	auto[1]	auto[0]	540393	1			T1	3697		T2	100		T12	33
all_values[24]	auto[0]	auto[1]	auto[1]	5013273	1			T1	30117		T2	639		T12	432
all_values[24]	auto[1]	auto[0]	auto[1]	73913	1			T1	412		T2	22		T14	1
all_values[24]	auto[1]	auto[1]	auto[1]	73262	1			T1	421		T2	25		T14	1
all_values[25]	auto[0]	auto[0]	auto[0]	2833971	1			T24	1		T25	258		T26	212
all_values[25]	auto[0]	auto[0]	auto[1]	5026552	1			T1	31924		T2	640		T12	773
all_values[25]	auto[0]	auto[1]	auto[0]	549943	1			T1	3005		T2	68		T12	46
all_values[25]	auto[0]	auto[1]	auto[1]	5044183	1			T1	31255		T2	693		T12	552
all_values[25]	auto[1]	auto[0]	auto[1]	72800	1			T1	391		T2	24		T14	1
all_values[25]	auto[1]	auto[1]	auto[1]	73509	1			T1	415		T2	27		T14	3
all_values[26]	auto[0]	auto[0]	auto[0]	2840547	1			T24	1		T25	258		T26	212
all_values[26]	auto[0]	auto[0]	auto[1]	5017893	1			T1	31681		T2	669		T12	573
all_values[26]	auto[0]	auto[1]	auto[0]	544470	1			T1	3597		T2	112		T12	72
all_values[26]	auto[0]	auto[1]	auto[1]	5051170	1			T1	30952		T2	618		T12	668
all_values[26]	auto[1]	auto[0]	auto[1]	73835	1			T1	391		T2	24		T14	2
all_values[26]	auto[1]	auto[1]	auto[1]	73043	1			T1	432		T2	28		T14	2
all_values[27]	auto[0]	auto[0]	auto[0]	2823042	1			T24	1		T25	258		T26	212
all_values[27]	auto[0]	auto[0]	auto[1]	5057646	1			T1	32303		T2	682		T12	539
all_values[27]	auto[0]	auto[1]	auto[0]	548044	1			T1	3389		T2	43		T12	136
all_values[27]	auto[0]	auto[1]	auto[1]	5024969	1			T1	30339		T2	626		T12	677
all_values[27]	auto[1]	auto[0]	auto[1]	74092	1			T1	426		T2	30		T14	2
all_values[27]	auto[1]	auto[1]	auto[1]	73165	1			T1	430		T2	21		T14	1
all_values[28]	auto[0]	auto[0]	auto[0]	2835560	1			T24	1		T25	258		T26	212
all_values[28]	auto[0]	auto[0]	auto[1]	5042382	1			T1	31420		T2	640		T12	637
all_values[28]	auto[0]	auto[1]	auto[0]	546374	1			T1	3552		T2	54		T12	36
all_values[28]	auto[0]	auto[1]	auto[1]	5029929	1			T1	30908		T2	678		T12	700
all_values[28]	auto[1]	auto[0]	auto[1]	73381	1			T1	456		T2	23		T14	3
all_values[28]	auto[1]	auto[1]	auto[1]	73332	1			T1	369		T2	25		T14	1
all_values[29]	auto[0]	auto[0]	auto[0]	2835765	1			T24	1		T25	258		T26	212
all_values[29]	auto[0]	auto[0]	auto[1]	5064785	1			T1	29116		T2	532		T12	789
all_values[29]	auto[0]	auto[1]	auto[0]	548054	1			T1	3326		T2	95		T12	39
all_values[29]	auto[0]	auto[1]	auto[1]	5006101	1			T1	33474		T2	691		T12	513
all_values[29]	auto[1]	auto[0]	auto[1]	73938	1			T1	419		T2	26		T14	4
all_values[29]	auto[1]	auto[1]	auto[1]	72315	1			T1	457		T2	25		T14	2
all_values[30]	auto[0]	auto[0]	auto[0]	2833253	1			T24	1		T25	258		T26	212
all_values[30]	auto[0]	auto[0]	auto[1]	5025828	1			T1	32237		T2	603		T12	564
all_values[30]	auto[0]	auto[1]	auto[0]	545806	1			T1	3398		T2	82		T12	20
all_values[30]	auto[0]	auto[1]	auto[1]	5048998	1			T1	30186		T2	695		T12	783
all_values[30]	auto[1]	auto[0]	auto[1]	74040	1			T1	437		T2	26		T14	1
all_values[30]	auto[1]	auto[1]	auto[1]	73033	1			T1	378		T2	29		T14	3
all_values[31]	auto[0]	auto[0]	auto[0]	2839012	1			T24	1		T25	258		T26	212
all_values[31]	auto[0]	auto[0]	auto[1]	5049631	1			T1	31396		T2	563		T12	768
all_values[31]	auto[0]	auto[1]	auto[0]	548442	1			T1	3414		T2	77		T12	27
all_values[31]	auto[0]	auto[1]	auto[1]	5017338	1			T1	31284		T2	709		T12	556
all_values[31]	auto[1]	auto[0]	auto[1]	73959	1			T1	438		T2	27		T14	2
all_values[31]	auto[1]	auto[1]	auto[1]	72576	1			T1	394		T2	37		T14	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal