Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[1]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[2]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[3]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[4]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[5]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[6]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[7]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[8]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[9]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[10]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[11]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[12]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[13]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[14]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[15]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[16]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[17]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[18]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[19]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[20]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[21]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[22]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[23]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[24]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[25]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[26]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[27]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[28]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[29]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[30]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[31]	13401219	1			T24	1		T25	362		T26	407

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

253668245

1

T24

32

T25

4176

T26

9885

auto[1]

175170763

1

T25

7408

T26

3139

T1

166776

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

345577389

1

T24

32

T25

8253

T26

9288

auto[1]

83261619

1

T25

3331

T26

3736

T1

545249

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

320868502

1

T24

32

T25

8400

T26

6190

auto[1]

107970506

1

T25

3184

T26

6834

T1

698899

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4985337	1			T24	1		T25	82		T26	92
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3733000	1			T25	119		T26	10		T1	31074
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1311330	1			T25	53		T26	59		T1	8608
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1631086	1			T26	137		T1	898		T2	16
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	440040	1			T25	56		T26	25		T1	12528
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1300426	1			T25	52		T26	84		T1	8565
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4990355	1			T24	1		T25	77		T26	165
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3730425	1			T25	115		T26	26		T1	31237
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1310222	1			T25	66		T26	70		T1	8518
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1636913	1			T26	106		T1	866		T2	6
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	438082	1			T25	42		T26	10		T1	12579
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1295222	1			T25	62		T26	30		T1	8357
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4975484	1			T24	1		T25	78		T26	94
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3734613	1			T25	147		T26	24		T1	31131
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1308716	1			T25	50		T26	59		T1	8096
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1639549	1			T26	151		T1	810		T2	16
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	439354	1			T25	48		T26	17		T1	12943
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1303503	1			T25	39		T26	62		T1	8633
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4964993	1			T24	1		T25	73		T26	131
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3751195	1			T25	146		T26	21		T1	30992
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1313686	1			T25	44		T26	43		T1	8365
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1637605	1			T26	126		T1	865		T2	18
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	437897	1			T25	51		T26	12		T1	12891
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1295843	1			T25	48		T26	74		T1	8424
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4968189	1			T24	1		T25	82		T26	175
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3745125	1			T25	123		T26	37		T1	31085
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1306333	1			T25	38		T26	81		T1	8255
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1642644	1			T26	68		T1	868		T2	19
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	439729	1			T25	65		T26	9		T1	12800
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1299199	1			T25	54		T26	37		T1	8655
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4974481	1			T24	1		T25	72		T26	160
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3742670	1			T25	145		T26	16		T1	31455
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1306533	1			T25	54		T26	58		T1	8374
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1641147	1			T26	89		T1	788		T2	20
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	439072	1			T25	44		T26	13		T1	12312
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1297316	1			T25	47		T26	71		T1	8386
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4976575	1			T24	1		T25	80		T26	175
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3741149	1			T25	127		T26	20		T1	30953
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1313632	1			T25	63		T26	49		T1	8179
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1632977	1			T26	99		T1	898		T2	18
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	438818	1			T25	30		T26	16		T1	12920
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1298068	1			T25	62		T26	48		T1	8557
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4983898	1			T24	1		T25	89		T26	106
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3729100	1			T25	120		T26	10		T1	31586
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1306207	1			T25	53		T26	28		T1	8872
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1639854	1			T26	128		T1	839		T2	12
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	440551	1			T25	56		T26	21		T1	11941
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1301609	1			T25	44		T26	114		T1	8236
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4976381	1			T24	1		T25	79		T26	122
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3744422	1			T25	120		T26	25		T1	30764
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1307213	1			T25	51		T26	51		T1	8826
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1637226	1			T26	150		T1	820		T2	30
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	436665	1			T25	46		T26	13		T1	12207
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1299312	1			T25	66		T26	46		T1	8815
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4974371	1			T24	1		T25	77		T26	159
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3744256	1			T25	116		T26	18		T1	30555
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1310295	1			T25	49		T26	53		T1	8609
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1632952	1			T26	109		T1	907		T2	18
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	438469	1			T25	48		T26	22		T1	12793
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1300876	1			T25	72		T26	46		T1	8562
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4967976	1			T24	1		T25	68		T26	154
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3749068	1			T25	129		T26	16		T1	31080
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1309461	1			T25	54		T26	58		T1	8134
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1640028	1			T26	119		T1	820		T2	6
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	438319	1			T25	52		T26	21		T1	12927
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1296367	1			T25	59		T26	39		T1	8481
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4979111	1			T24	1		T25	73		T26	83
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3745480	1			T25	156		T26	9		T1	30915
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1308668	1			T25	50		T26	58		T1	8694
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1639006	1			T26	177		T1	861		T2	18
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	437143	1			T25	61		T26	18		T1	12382
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1291811	1			T25	22		T26	62		T1	8626
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4983734	1			T24	1		T25	78		T26	60
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3738799	1			T25	131		T26	10		T1	31038
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1307901	1			T25	61		T26	62		T1	8234
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1637904	1			T26	171		T1	926		T2	31
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	436341	1			T25	52		T26	23		T1	12490
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1296540	1			T25	40		T26	81		T1	8828
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4977264	1			T24	1		T25	70		T26	150
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3743044	1			T25	142		T26	25		T1	31051
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1311241	1			T25	50		T26	40		T1	8776
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1637950	1			T26	101		T1	892		T2	15
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	436617	1			T25	42		T26	16		T1	12132
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1295103	1			T25	58		T26	75		T1	8578
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4984032	1			T24	1		T25	70		T26	107
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3734487	1			T25	146		T26	11		T1	30969
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1305778	1			T25	66		T26	67		T1	8624
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1638970	1			T26	134		T1	819		T2	30
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	441014	1			T25	38		T26	27		T1	12475
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1296938	1			T25	42		T26	61		T1	8485
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4986453	1			T24	1		T25	79		T26	162
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3729134	1			T25	124		T26	24		T1	30812
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1313659	1			T25	56		T26	90		T1	8598
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1636322	1			T26	86		T1	879		T2	8
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	437350	1			T25	51		T26	11		T1	12556
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1298301	1			T25	52		T26	34		T1	8595
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4979396	1			T24	1		T25	77		T26	140
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3743549	1			T25	156		T26	19		T1	30623
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1307658	1			T25	34		T26	91		T1	8490
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1640800	1			T26	89		T1	994		T2	17
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	439239	1			T25	57		T26	11		T1	12855
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1290577	1			T25	38		T26	57		T1	8647
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4993116	1			T24	1		T25	68		T26	96
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3739344	1			T25	133		T26	11		T1	31307
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1301943	1			T25	62		T26	45		T1	8636
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1635807	1			T26	166		T1	777		T2	35
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	439669	1			T25	28		T26	27		T1	12232
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1291340	1			T25	71		T26	62		T1	8472
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4990865	1			T24	1		T25	89		T26	143
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3734587	1			T25	130		T26	17		T1	31187
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1305050	1			T25	67		T26	52		T1	8997
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1640816	1			T26	141		T1	876		T2	22
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	438856	1			T25	42		T26	15		T1	12371
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1291045	1			T25	34		T26	39		T1	8279
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4985518	1			T24	1		T25	79		T26	154
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3740315	1			T25	118		T26	22		T1	31498
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1304396	1			T25	46		T26	76		T1	8902
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1644171	1			T26	103		T1	733		T2	17
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	439074	1			T25	61		T26	9		T1	11998
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1287745	1			T25	58		T26	43		T1	8544
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4973920	1			T24	1		T25	73		T26	134
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3739475	1			T25	120		T26	15		T1	31567
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1305909	1			T25	41		T26	51		T1	8335
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1646751	1			T26	119		T1	853		T2	28
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	441533	1			T25	48		T26	21		T1	12338
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1293631	1			T25	80		T26	67		T1	8336
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4985842	1			T24	1		T25	83		T26	143
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3729682	1			T25	140		T26	21		T1	31206
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1300738	1			T25	63		T26	81		T1	8563
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1649588	1			T26	93		T1	859		T2	12
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	442169	1			T25	34		T26	25		T1	12544
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1293200	1			T25	42		T26	44		T1	8376
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4997886	1			T24	1		T25	81		T26	89
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3730482	1			T25	136		T26	7		T1	31118
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1302390	1			T25	50		T26	49		T1	8433
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1642965	1			T26	166		T1	878		T2	14
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	439295	1			T25	56		T26	30		T1	12768
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1288201	1			T25	39		T26	66		T1	8322
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4967190	1			T24	1		T25	76		T26	89
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3750311	1			T25	139		T26	8		T1	30339
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1305548	1			T25	52		T26	29		T1	8845
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1644056	1			T26	184		T1	984		T2	18
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	440356	1			T25	39		T26	33		T1	12687
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1293758	1			T25	56		T26	64		T1	8707
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4985648	1			T24	1		T25	69		T26	84
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3737520	1			T25	126		T26	22		T1	31243
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1309319	1			T25	75		T26	38		T1	8631
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1636016	1			T26	148		T1	890		T2	17
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	438318	1			T25	46		T26	21		T1	12302
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1294398	1			T25	46		T26	94		T1	8430
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4994566	1			T24	1		T25	70		T26	60
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3734028	1			T25	140		T26	1		T1	31318
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1303914	1			T25	64		T26	30		T1	8547
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1642581	1			T26	201		T1	890		T2	19
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	436652	1			T25	52		T26	39		T1	12634
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1289478	1			T25	36		T26	76		T1	8264
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4982787	1			T24	1		T25	78		T26	141
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3739874	1			T25	133		T26	19		T1	31071
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1304950	1			T25	36		T26	51		T1	8504
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1639487	1			T26	114		T1	866		T2	13
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	438770	1			T25	54		T26	12		T1	12684
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1295351	1			T25	61		T26	70		T1	8211
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4978373	1			T24	1		T25	82		T26	143
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3742579	1			T25	124		T26	20		T1	31178
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1298594	1			T25	64		T26	85		T1	8455
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1644127	1			T26	76		T1	881		T2	26
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	441004	1			T25	40		T26	23		T1	12585
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1296542	1			T25	52		T26	60		T1	8551
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4976033	1			T24	1		T25	80		T26	99
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3745609	1			T25	135		T26	15		T1	31649
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1303985	1			T25	43		T26	43		T1	8429
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1641708	1			T26	176		T1	832		T2	15
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	437676	1			T25	54		T26	20		T1	12639
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1296208	1			T25	50		T26	54		T1	8229
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4977561	1			T24	1		T25	69		T26	107
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3744983	1			T25	130		T26	15		T1	31253
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1304572	1			T25	60		T26	32		T1	8626
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1639680	1			T26	175		T1	847		T2	22
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	440170	1			T25	66		T26	19		T1	12113
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1294253	1			T25	37		T26	59		T1	8543
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4972936	1			T24	1		T25	78		T26	69
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3743383	1			T25	127		T26	12		T1	31326
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1301697	1			T25	50		T26	35		T1	8574
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1648499	1			T26	172		T1	810		T2	19
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	438706	1			T25	64		T26	30		T1	12285
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1295998	1			T25	43		T26	89		T1	8588
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4983573	1			T24	1		T25	76		T26	97
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3747777	1			T25	131		T26	13		T1	31819
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1303655	1			T25	56		T26	54		T1	8770
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1640023	1			T26	160		T1	810		T2	15
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	437924	1			T25	51		T26	23		T1	11702
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1288267	1			T25	48		T26	60		T1	8468

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal