Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[1]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[2]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[3]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[4]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[5]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[6]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[7]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[8]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[9]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[10]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[11]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[12]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[13]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[14]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[15]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[16]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[17]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[18]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[19]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[20]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[21]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[22]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[23]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[24]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[25]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[26]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[27]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[28]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[29]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[30]	13401219	1			T24	1		T25	362		T26	407
bins_for_gpio_bits[31]	13401219	1			T24	1		T25	362		T26	407

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

253668245

1

T24

32

T25

4176

T26

9885

auto[1]

175170763

1

T25

7408

T26

3139

T1

166776

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

253660352

1

T24

32

T25

4187

T26

9885

auto[1]

175178656

1

T25

7397

T26

3139

T1

166757

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7695368	1			T24	1		T25	126		T26	275
bins_for_gpio_bits[0]	auto[0]	auto[1]	232162	1			T25	10		T26	13		T1	1573
bins_for_gpio_bits[0]	auto[1]	auto[0]	232385	1			T25	9		T26	13		T1	1566
bins_for_gpio_bits[0]	auto[1]	auto[1]	5241304	1			T25	217		T26	106		T1	50594
bins_for_gpio_bits[1]	auto[0]	auto[0]	7705382	1			T24	1		T25	129		T26	333
bins_for_gpio_bits[1]	auto[0]	auto[1]	231825	1			T25	14		T26	8		T1	1562
bins_for_gpio_bits[1]	auto[1]	auto[0]	232108	1			T25	14		T26	8		T1	1558
bins_for_gpio_bits[1]	auto[1]	auto[1]	5231904	1			T25	205		T26	58		T1	50611
bins_for_gpio_bits[2]	auto[0]	auto[0]	7691238	1			T24	1		T25	116		T26	295
bins_for_gpio_bits[2]	auto[0]	auto[1]	232223	1			T25	12		T26	9		T1	1556
bins_for_gpio_bits[2]	auto[1]	auto[0]	232511	1			T25	12		T26	9		T1	1550
bins_for_gpio_bits[2]	auto[1]	auto[1]	5245247	1			T25	222		T26	94		T1	51151
bins_for_gpio_bits[3]	auto[0]	auto[0]	7683981	1			T24	1		T25	107		T26	287
bins_for_gpio_bits[3]	auto[0]	auto[1]	232057	1			T25	10		T26	13		T1	1575
bins_for_gpio_bits[3]	auto[1]	auto[0]	232303	1			T25	10		T26	13		T1	1569
bins_for_gpio_bits[3]	auto[1]	auto[1]	5252878	1			T25	235		T26	94		T1	50732
bins_for_gpio_bits[4]	auto[0]	auto[0]	7684998	1			T24	1		T25	110		T26	318
bins_for_gpio_bits[4]	auto[0]	auto[1]	231920	1			T25	10		T26	6		T1	1573
bins_for_gpio_bits[4]	auto[1]	auto[0]	232168	1			T25	10		T26	6		T1	1569
bins_for_gpio_bits[4]	auto[1]	auto[1]	5252133	1			T25	232		T26	77		T1	50967
bins_for_gpio_bits[5]	auto[0]	auto[0]	7689590	1			T24	1		T25	112		T26	295
bins_for_gpio_bits[5]	auto[0]	auto[1]	232344	1			T25	14		T26	12		T1	1572
bins_for_gpio_bits[5]	auto[1]	auto[0]	232571	1			T25	14		T26	12		T1	1566
bins_for_gpio_bits[5]	auto[1]	auto[1]	5246714	1			T25	222		T26	88		T1	50581
bins_for_gpio_bits[6]	auto[0]	auto[0]	7690104	1			T24	1		T25	127		T26	315
bins_for_gpio_bits[6]	auto[0]	auto[1]	232842	1			T25	17		T26	8		T1	1577
bins_for_gpio_bits[6]	auto[1]	auto[0]	233080	1			T25	16		T26	8		T1	1570
bins_for_gpio_bits[6]	auto[1]	auto[1]	5245193	1			T25	202		T26	76		T1	50853
bins_for_gpio_bits[7]	auto[0]	auto[0]	7697809	1			T24	1		T25	126		T26	246
bins_for_gpio_bits[7]	auto[0]	auto[1]	231908	1			T25	17		T26	16		T1	1649
bins_for_gpio_bits[7]	auto[1]	auto[0]	232150	1			T25	16		T26	16		T1	1642
bins_for_gpio_bits[7]	auto[1]	auto[1]	5239352	1			T25	203		T26	129		T1	50114
bins_for_gpio_bits[8]	auto[0]	auto[0]	7687595	1			T24	1		T25	121		T26	318
bins_for_gpio_bits[8]	auto[0]	auto[1]	232967	1			T25	10		T26	5		T1	1610
bins_for_gpio_bits[8]	auto[1]	auto[0]	233225	1			T25	9		T26	5		T1	1606
bins_for_gpio_bits[8]	auto[1]	auto[1]	5247432	1			T25	222		T26	79		T1	50176
bins_for_gpio_bits[9]	auto[0]	auto[0]	7685746	1			T24	1		T25	115		T26	312
bins_for_gpio_bits[9]	auto[0]	auto[1]	231651	1			T25	12		T26	9		T1	1595
bins_for_gpio_bits[9]	auto[1]	auto[0]	231872	1			T25	11		T26	9		T1	1591
bins_for_gpio_bits[9]	auto[1]	auto[1]	5251950	1			T25	224		T26	77		T1	50315
bins_for_gpio_bits[10]	auto[0]	auto[0]	7684811	1			T24	1		T25	112		T26	323
bins_for_gpio_bits[10]	auto[0]	auto[1]	232405	1			T25	10		T26	8		T1	1540
bins_for_gpio_bits[10]	auto[1]	auto[0]	232654	1			T25	10		T26	8		T1	1536
bins_for_gpio_bits[10]	auto[1]	auto[1]	5251349	1			T25	230		T26	68		T1	50948
bins_for_gpio_bits[11]	auto[0]	auto[0]	7694816	1			T24	1		T25	111		T26	308
bins_for_gpio_bits[11]	auto[0]	auto[1]	231716	1			T25	12		T26	10		T1	1582
bins_for_gpio_bits[11]	auto[1]	auto[0]	231969	1			T25	12		T26	10		T1	1575
bins_for_gpio_bits[11]	auto[1]	auto[1]	5242718	1			T25	227		T26	79		T1	50341
bins_for_gpio_bits[12]	auto[0]	auto[0]	7697424	1			T24	1		T25	127		T26	279
bins_for_gpio_bits[12]	auto[0]	auto[1]	231851	1			T25	13		T26	14		T1	1573
bins_for_gpio_bits[12]	auto[1]	auto[0]	232115	1			T25	12		T26	14		T1	1571
bins_for_gpio_bits[12]	auto[1]	auto[1]	5239829	1			T25	210		T26	100		T1	50783
bins_for_gpio_bits[13]	auto[0]	auto[0]	7693872	1			T24	1		T25	105		T26	278
bins_for_gpio_bits[13]	auto[0]	auto[1]	232336	1			T25	15		T26	13		T1	1608
bins_for_gpio_bits[13]	auto[1]	auto[0]	232583	1			T25	15		T26	13		T1	1604
bins_for_gpio_bits[13]	auto[1]	auto[1]	5242428	1			T25	227		T26	103		T1	50153
bins_for_gpio_bits[14]	auto[0]	auto[0]	7696031	1			T24	1		T25	123		T26	299
bins_for_gpio_bits[14]	auto[0]	auto[1]	232527	1			T25	13		T26	9		T1	1598
bins_for_gpio_bits[14]	auto[1]	auto[0]	232749	1			T25	13		T26	9		T1	1591
bins_for_gpio_bits[14]	auto[1]	auto[1]	5239912	1			T25	213		T26	90		T1	50331
bins_for_gpio_bits[15]	auto[0]	auto[0]	7704253	1			T24	1		T25	123		T26	329
bins_for_gpio_bits[15]	auto[0]	auto[1]	231952	1			T25	12		T26	9		T1	1628
bins_for_gpio_bits[15]	auto[1]	auto[0]	232181	1			T25	12		T26	9		T1	1622
bins_for_gpio_bits[15]	auto[1]	auto[1]	5232833	1			T25	215		T26	60		T1	50335
bins_for_gpio_bits[16]	auto[0]	auto[0]	7695659	1			T24	1		T25	98		T26	310
bins_for_gpio_bits[16]	auto[0]	auto[1]	231987	1			T25	13		T26	10		T1	1586
bins_for_gpio_bits[16]	auto[1]	auto[0]	232195	1			T25	13		T26	10		T1	1580
bins_for_gpio_bits[16]	auto[1]	auto[1]	5241378	1			T25	238		T26	77		T1	50539
bins_for_gpio_bits[17]	auto[0]	auto[0]	7698912	1			T24	1		T25	115		T26	296
bins_for_gpio_bits[17]	auto[0]	auto[1]	231709	1			T25	15		T26	11		T1	1614
bins_for_gpio_bits[17]	auto[1]	auto[0]	231954	1			T25	15		T26	11		T1	1606
bins_for_gpio_bits[17]	auto[1]	auto[1]	5238644	1			T25	217		T26	89		T1	50397
bins_for_gpio_bits[18]	auto[0]	auto[0]	7704374	1			T24	1		T25	145		T26	328
bins_for_gpio_bits[18]	auto[0]	auto[1]	232096	1			T25	12		T26	8		T1	1640
bins_for_gpio_bits[18]	auto[1]	auto[0]	232357	1			T25	11		T26	8		T1	1634
bins_for_gpio_bits[18]	auto[1]	auto[1]	5232392	1			T25	194		T26	63		T1	50197
bins_for_gpio_bits[19]	auto[0]	auto[0]	7702410	1			T24	1		T25	111		T26	325
bins_for_gpio_bits[19]	auto[0]	auto[1]	231455	1			T25	14		T26	8		T1	1653
bins_for_gpio_bits[19]	auto[1]	auto[0]	231675	1			T25	14		T26	8		T1	1645
bins_for_gpio_bits[19]	auto[1]	auto[1]	5235679	1			T25	223		T26	66		T1	50387
bins_for_gpio_bits[20]	auto[0]	auto[0]	7694021	1			T24	1		T25	103		T26	293
bins_for_gpio_bits[20]	auto[0]	auto[1]	232303	1			T25	12		T26	11		T1	1574
bins_for_gpio_bits[20]	auto[1]	auto[0]	232559	1			T25	11		T26	11		T1	1568
bins_for_gpio_bits[20]	auto[1]	auto[1]	5242336	1			T25	236		T26	92		T1	50667
bins_for_gpio_bits[21]	auto[0]	auto[0]	7704010	1			T24	1		T25	131		T26	308
bins_for_gpio_bits[21]	auto[0]	auto[1]	231895	1			T25	16		T26	9		T1	1630
bins_for_gpio_bits[21]	auto[1]	auto[0]	232158	1			T25	15		T26	9		T1	1626
bins_for_gpio_bits[21]	auto[1]	auto[1]	5233156	1			T25	200		T26	81		T1	50496
bins_for_gpio_bits[22]	auto[0]	auto[0]	7710829	1			T24	1		T25	118		T26	291
bins_for_gpio_bits[22]	auto[0]	auto[1]	232170	1			T25	13		T26	13		T1	1594
bins_for_gpio_bits[22]	auto[1]	auto[0]	232412	1			T25	13		T26	13		T1	1591
bins_for_gpio_bits[22]	auto[1]	auto[1]	5225808	1			T25	218		T26	90		T1	50614
bins_for_gpio_bits[23]	auto[0]	auto[0]	7684916	1			T24	1		T25	115		T26	288
bins_for_gpio_bits[23]	auto[0]	auto[1]	231645	1			T25	13		T26	14		T1	1613
bins_for_gpio_bits[23]	auto[1]	auto[0]	231878	1			T25	13		T26	14		T1	1609
bins_for_gpio_bits[23]	auto[1]	auto[1]	5252780	1			T25	221		T26	91		T1	50120
bins_for_gpio_bits[24]	auto[0]	auto[0]	7698287	1			T24	1		T25	130		T26	259
bins_for_gpio_bits[24]	auto[0]	auto[1]	232433	1			T25	15		T26	11		T1	1603
bins_for_gpio_bits[24]	auto[1]	auto[0]	232696	1			T25	14		T26	11		T1	1594
bins_for_gpio_bits[24]	auto[1]	auto[1]	5237803	1			T25	203		T26	126		T1	50372
bins_for_gpio_bits[25]	auto[0]	auto[0]	7709026	1			T24	1		T25	123		T26	276
bins_for_gpio_bits[25]	auto[0]	auto[1]	231796	1			T25	11		T26	15		T1	1555
bins_for_gpio_bits[25]	auto[1]	auto[0]	232035	1			T25	11		T26	15		T1	1547
bins_for_gpio_bits[25]	auto[1]	auto[1]	5228362	1			T25	217		T26	101		T1	50661
bins_for_gpio_bits[26]	auto[0]	auto[0]	7694609	1			T24	1		T25	105		T26	293
bins_for_gpio_bits[26]	auto[0]	auto[1]	232348	1			T25	9		T26	13		T1	1597
bins_for_gpio_bits[26]	auto[1]	auto[0]	232615	1			T25	9		T26	13		T1	1592
bins_for_gpio_bits[26]	auto[1]	auto[1]	5241647	1			T25	239		T26	88		T1	50369
bins_for_gpio_bits[27]	auto[0]	auto[0]	7688505	1			T24	1		T25	129		T26	293
bins_for_gpio_bits[27]	auto[0]	auto[1]	232311	1			T25	17		T26	11		T1	1636
bins_for_gpio_bits[27]	auto[1]	auto[0]	232589	1			T25	17		T26	11		T1	1630
bins_for_gpio_bits[27]	auto[1]	auto[1]	5247814	1			T25	199		T26	92		T1	50678
bins_for_gpio_bits[28]	auto[0]	auto[0]	7688999	1			T24	1		T25	111		T26	304
bins_for_gpio_bits[28]	auto[0]	auto[1]	232464	1			T25	13		T26	14		T1	1607
bins_for_gpio_bits[28]	auto[1]	auto[0]	232727	1			T25	12		T26	14		T1	1602
bins_for_gpio_bits[28]	auto[1]	auto[1]	5247029	1			T25	226		T26	75		T1	50910
bins_for_gpio_bits[29]	auto[0]	auto[0]	7689636	1			T24	1		T25	117		T26	302
bins_for_gpio_bits[29]	auto[0]	auto[1]	231945	1			T25	12		T26	12		T1	1641
bins_for_gpio_bits[29]	auto[1]	auto[0]	232177	1			T25	12		T26	12		T1	1634
bins_for_gpio_bits[29]	auto[1]	auto[1]	5247461	1			T25	221		T26	81		T1	50268
bins_for_gpio_bits[30]	auto[0]	auto[0]	7690254	1			T24	1		T25	119		T26	261
bins_for_gpio_bits[30]	auto[0]	auto[1]	232634	1			T25	9		T26	15		T1	1645
bins_for_gpio_bits[30]	auto[1]	auto[0]	232878	1			T25	9		T26	15		T1	1638
bins_for_gpio_bits[30]	auto[1]	auto[1]	5245453	1			T25	225		T26	116		T1	50554
bins_for_gpio_bits[31]	auto[0]	auto[0]	7695610	1			T24	1		T25	117		T26	299
bins_for_gpio_bits[31]	auto[0]	auto[1]	231400	1			T25	15		T26	12		T1	1623
bins_for_gpio_bits[31]	auto[1]	auto[0]	231641	1			T25	15		T26	12		T1	1615
bins_for_gpio_bits[31]	auto[1]	auto[1]	5242568	1			T25	215		T26	84		T1	50366