Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7956966 |
1 |
|
|
T24 |
1 |
|
T25 |
258 |
|
T26 |
212 |
| auto[1] |
5643992 |
1 |
|
|
T1 |
35266 |
|
T2 |
731 |
|
T12 |
772 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12877455 |
1 |
|
|
T24 |
1 |
|
T25 |
258 |
|
T26 |
212 |
| auto[1] |
723503 |
1 |
|
|
T1 |
4458 |
|
T2 |
36 |
|
T12 |
159 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7961400 |
1 |
|
|
T24 |
1 |
|
T25 |
258 |
|
T26 |
212 |
| auto[1] |
5639558 |
1 |
|
|
T1 |
34111 |
|
T2 |
744 |
|
T12 |
815 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2461885 |
1 |
|
|
T1 |
14650 |
|
T2 |
355 |
|
T12 |
319 |
| auto[1] |
auto[0] |
auto[1] |
362376 |
1 |
|
|
T1 |
2261 |
|
T2 |
17 |
|
T12 |
75 |
| auto[1] |
auto[1] |
auto[0] |
2454170 |
1 |
|
|
T1 |
15003 |
|
T2 |
353 |
|
T12 |
337 |
| auto[1] |
auto[1] |
auto[1] |
361127 |
1 |
|
|
T1 |
2197 |
|
T2 |
19 |
|
T12 |
84 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |