Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7974353 |
1 |
|
|
T24 |
1 |
|
T25 |
258 |
|
T26 |
212 |
| auto[1] |
5626605 |
1 |
|
|
T1 |
36361 |
|
T2 |
764 |
|
T12 |
564 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11252594 |
1 |
|
|
T24 |
1 |
|
T25 |
258 |
|
T26 |
212 |
| auto[1] |
2348364 |
1 |
|
|
T1 |
21307 |
|
T2 |
533 |
|
T12 |
366 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7962870 |
1 |
|
|
T24 |
1 |
|
T25 |
258 |
|
T26 |
212 |
| auto[1] |
5638088 |
1 |
|
|
T1 |
35571 |
|
T2 |
713 |
|
T12 |
701 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1665837 |
1 |
|
|
T1 |
6942 |
|
T2 |
85 |
|
T12 |
201 |
| auto[1] |
auto[0] |
auto[1] |
1183731 |
1 |
|
|
T1 |
10116 |
|
T2 |
254 |
|
T12 |
209 |
| auto[1] |
auto[1] |
auto[0] |
1623887 |
1 |
|
|
T1 |
7322 |
|
T2 |
95 |
|
T12 |
134 |
| auto[1] |
auto[1] |
auto[1] |
1164633 |
1 |
|
|
T1 |
11191 |
|
T2 |
279 |
|
T12 |
157 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |