Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7965317 |
1 |
|
|
T24 |
1 |
|
T25 |
258 |
|
T26 |
212 |
| auto[1] |
5635641 |
1 |
|
|
T1 |
34720 |
|
T2 |
725 |
|
T12 |
631 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2438133 |
1 |
|
|
T1 |
15096 |
|
T2 |
397 |
|
T12 |
191 |
| auto[1] |
auto[0] |
auto[1] |
357004 |
1 |
|
|
T1 |
2356 |
|
T2 |
17 |
|
T12 |
42 |
| auto[1] |
auto[1] |
auto[0] |
2474683 |
1 |
|
|
T1 |
15097 |
|
T2 |
294 |
|
T12 |
328 |
| auto[1] |
auto[1] |
auto[1] |
365821 |
1 |
|
|
T1 |
2171 |
|
T2 |
17 |
|
T12 |
70 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |