Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7949939 |
1 |
|
|
T24 |
1 |
|
T25 |
258 |
|
T26 |
212 |
| auto[1] |
5651019 |
1 |
|
|
T1 |
34426 |
|
T2 |
853 |
|
T12 |
666 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11255266 |
1 |
|
|
T24 |
1 |
|
T25 |
258 |
|
T26 |
212 |
| auto[1] |
2345692 |
1 |
|
|
T1 |
20981 |
|
T2 |
560 |
|
T12 |
378 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7962078 |
1 |
|
|
T24 |
1 |
|
T25 |
258 |
|
T26 |
212 |
| auto[1] |
5638880 |
1 |
|
|
T1 |
35659 |
|
T2 |
714 |
|
T12 |
762 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1639995 |
1 |
|
|
T1 |
7716 |
|
T2 |
67 |
|
T12 |
222 |
| auto[1] |
auto[0] |
auto[1] |
1172653 |
1 |
|
|
T1 |
11221 |
|
T2 |
223 |
|
T12 |
206 |
| auto[1] |
auto[1] |
auto[0] |
1653193 |
1 |
|
|
T1 |
6962 |
|
T2 |
87 |
|
T12 |
162 |
| auto[1] |
auto[1] |
auto[1] |
1173039 |
1 |
|
|
T1 |
9760 |
|
T2 |
337 |
|
T12 |
172 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |