Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7970589 |
1 |
|
|
T24 |
1 |
|
T25 |
258 |
|
T26 |
212 |
| auto[1] |
5630369 |
1 |
|
|
T1 |
35177 |
|
T2 |
776 |
|
T12 |
525 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11252981 |
1 |
|
|
T24 |
1 |
|
T25 |
258 |
|
T26 |
212 |
| auto[1] |
2347977 |
1 |
|
|
T1 |
20239 |
|
T2 |
645 |
|
T12 |
492 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7953988 |
1 |
|
|
T24 |
1 |
|
T25 |
258 |
|
T26 |
212 |
| auto[1] |
5646970 |
1 |
|
|
T1 |
34378 |
|
T2 |
776 |
|
T12 |
923 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1652070 |
1 |
|
|
T1 |
6897 |
|
T2 |
55 |
|
T12 |
267 |
| auto[1] |
auto[0] |
auto[1] |
1176099 |
1 |
|
|
T1 |
10086 |
|
T2 |
274 |
|
T12 |
271 |
| auto[1] |
auto[1] |
auto[0] |
1646923 |
1 |
|
|
T1 |
7242 |
|
T2 |
76 |
|
T12 |
164 |
| auto[1] |
auto[1] |
auto[1] |
1171878 |
1 |
|
|
T1 |
10153 |
|
T2 |
371 |
|
T12 |
221 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |