Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7960406 |
1 |
|
|
T24 |
1 |
|
T25 |
258 |
|
T26 |
212 |
| auto[1] |
5640552 |
1 |
|
|
T1 |
33320 |
|
T2 |
675 |
|
T12 |
509 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11248182 |
1 |
|
|
T24 |
1 |
|
T25 |
258 |
|
T26 |
212 |
| auto[1] |
2352776 |
1 |
|
|
T1 |
20634 |
|
T2 |
555 |
|
T12 |
422 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7929407 |
1 |
|
|
T24 |
1 |
|
T25 |
258 |
|
T26 |
212 |
| auto[1] |
5671551 |
1 |
|
|
T1 |
34091 |
|
T2 |
727 |
|
T12 |
815 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1677285 |
1 |
|
|
T1 |
6915 |
|
T2 |
88 |
|
T12 |
266 |
| auto[1] |
auto[0] |
auto[1] |
1188374 |
1 |
|
|
T1 |
10848 |
|
T2 |
280 |
|
T12 |
283 |
| auto[1] |
auto[1] |
auto[0] |
1641490 |
1 |
|
|
T1 |
6542 |
|
T2 |
84 |
|
T12 |
127 |
| auto[1] |
auto[1] |
auto[1] |
1164402 |
1 |
|
|
T1 |
9786 |
|
T2 |
275 |
|
T12 |
139 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |