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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 941
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T760 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2563571134 Jul 02 08:08:20 AM PDT 24 Jul 02 08:08:27 AM PDT 24 31144081 ps
T82 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2591323622 Jul 02 08:08:23 AM PDT 24 Jul 02 08:08:30 AM PDT 24 160853510 ps
T761 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.4222710334 Jul 02 08:08:30 AM PDT 24 Jul 02 08:08:35 AM PDT 24 64977827 ps
T762 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3898727679 Jul 02 08:08:50 AM PDT 24 Jul 02 08:08:55 AM PDT 24 15665797 ps
T763 /workspace/coverage/cover_reg_top/5.gpio_intr_test.3175862878 Jul 02 08:08:29 AM PDT 24 Jul 02 08:08:35 AM PDT 24 18740793 ps
T764 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2492632018 Jul 02 08:08:35 AM PDT 24 Jul 02 08:08:41 AM PDT 24 50943410 ps
T765 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2357792370 Jul 02 08:08:23 AM PDT 24 Jul 02 08:08:29 AM PDT 24 13515613 ps
T766 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3595674849 Jul 02 08:08:22 AM PDT 24 Jul 02 08:08:29 AM PDT 24 143633028 ps
T767 /workspace/coverage/cover_reg_top/45.gpio_intr_test.107848893 Jul 02 08:08:48 AM PDT 24 Jul 02 08:08:52 AM PDT 24 42752077 ps
T768 /workspace/coverage/cover_reg_top/4.gpio_intr_test.1470611479 Jul 02 08:08:22 AM PDT 24 Jul 02 08:08:29 AM PDT 24 16415843 ps
T769 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2296841294 Jul 02 08:08:35 AM PDT 24 Jul 02 08:08:40 AM PDT 24 1022732310 ps
T770 /workspace/coverage/cover_reg_top/29.gpio_intr_test.753314465 Jul 02 08:08:45 AM PDT 24 Jul 02 08:08:48 AM PDT 24 23366289 ps
T771 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.4167045095 Jul 02 08:08:50 AM PDT 24 Jul 02 08:08:55 AM PDT 24 104923618 ps
T772 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2060253518 Jul 02 08:08:35 AM PDT 24 Jul 02 08:08:38 AM PDT 24 15186571 ps
T42 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3358321338 Jul 02 08:08:48 AM PDT 24 Jul 02 08:08:52 AM PDT 24 532702371 ps
T773 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2320068103 Jul 02 08:08:44 AM PDT 24 Jul 02 08:08:47 AM PDT 24 27287169 ps
T774 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3169804558 Jul 02 08:08:31 AM PDT 24 Jul 02 08:08:36 AM PDT 24 124635555 ps
T775 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3490987376 Jul 02 08:08:30 AM PDT 24 Jul 02 08:08:37 AM PDT 24 185911066 ps
T776 /workspace/coverage/cover_reg_top/19.gpio_intr_test.1580900504 Jul 02 08:08:44 AM PDT 24 Jul 02 08:08:47 AM PDT 24 44556398 ps
T777 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1313998775 Jul 02 08:08:39 AM PDT 24 Jul 02 08:08:44 AM PDT 24 32807465 ps
T99 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1361258222 Jul 02 08:08:37 AM PDT 24 Jul 02 08:08:42 AM PDT 24 127444394 ps
T778 /workspace/coverage/cover_reg_top/22.gpio_intr_test.2550812836 Jul 02 08:08:45 AM PDT 24 Jul 02 08:08:48 AM PDT 24 12174982 ps
T779 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1924975730 Jul 02 08:08:39 AM PDT 24 Jul 02 08:08:42 AM PDT 24 12836993 ps
T780 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3636911772 Jul 02 08:08:37 AM PDT 24 Jul 02 08:08:42 AM PDT 24 136282247 ps
T781 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.4262079580 Jul 02 08:08:25 AM PDT 24 Jul 02 08:08:32 AM PDT 24 61051740 ps
T782 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1281974884 Jul 02 08:08:16 AM PDT 24 Jul 02 08:08:24 AM PDT 24 305503511 ps
T783 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3074247153 Jul 02 08:08:24 AM PDT 24 Jul 02 08:08:33 AM PDT 24 156743156 ps
T784 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3826276427 Jul 02 08:08:40 AM PDT 24 Jul 02 08:08:44 AM PDT 24 398811518 ps
T83 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2747042789 Jul 02 08:08:23 AM PDT 24 Jul 02 08:08:30 AM PDT 24 43751637 ps
T785 /workspace/coverage/cover_reg_top/38.gpio_intr_test.1441808808 Jul 02 08:08:52 AM PDT 24 Jul 02 08:08:58 AM PDT 24 19371156 ps
T786 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2137608363 Jul 02 08:08:28 AM PDT 24 Jul 02 08:08:34 AM PDT 24 107734865 ps
T787 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3417199592 Jul 02 08:08:29 AM PDT 24 Jul 02 08:08:35 AM PDT 24 35572793 ps
T788 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3967108697 Jul 02 08:08:31 AM PDT 24 Jul 02 08:08:36 AM PDT 24 13150612 ps
T789 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.4086341695 Jul 02 08:08:22 AM PDT 24 Jul 02 08:08:31 AM PDT 24 129510713 ps
T790 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2579284009 Jul 02 08:08:40 AM PDT 24 Jul 02 08:08:45 AM PDT 24 109893808 ps
T791 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.138194073 Jul 02 08:08:35 AM PDT 24 Jul 02 08:08:39 AM PDT 24 27045846 ps
T792 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1054669827 Jul 02 08:08:29 AM PDT 24 Jul 02 08:08:36 AM PDT 24 63104377 ps
T793 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1986606127 Jul 02 08:08:22 AM PDT 24 Jul 02 08:08:29 AM PDT 24 11916442 ps
T84 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.470330721 Jul 02 08:08:23 AM PDT 24 Jul 02 08:08:29 AM PDT 24 39123096 ps
T794 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3824452681 Jul 02 08:08:22 AM PDT 24 Jul 02 08:08:29 AM PDT 24 18659012 ps
T795 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2933995317 Jul 02 08:08:46 AM PDT 24 Jul 02 08:08:49 AM PDT 24 11777996 ps
T796 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.4237828916 Jul 02 08:08:40 AM PDT 24 Jul 02 08:08:44 AM PDT 24 16471122 ps
T797 /workspace/coverage/cover_reg_top/25.gpio_intr_test.3854973818 Jul 02 08:08:46 AM PDT 24 Jul 02 08:08:49 AM PDT 24 21008822 ps
T798 /workspace/coverage/cover_reg_top/9.gpio_intr_test.2156544621 Jul 02 08:08:36 AM PDT 24 Jul 02 08:08:39 AM PDT 24 25853342 ps
T799 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1771561087 Jul 02 08:08:46 AM PDT 24 Jul 02 08:08:50 AM PDT 24 411663492 ps
T85 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2613152440 Jul 02 08:08:27 AM PDT 24 Jul 02 08:08:33 AM PDT 24 25797459 ps
T800 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.853637145 Jul 02 08:08:46 AM PDT 24 Jul 02 08:08:50 AM PDT 24 116380760 ps
T801 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3631987066 Jul 02 08:08:18 AM PDT 24 Jul 02 08:08:24 AM PDT 24 55659036 ps
T802 /workspace/coverage/cover_reg_top/34.gpio_intr_test.208499118 Jul 02 08:08:51 AM PDT 24 Jul 02 08:08:56 AM PDT 24 26484851 ps
T803 /workspace/coverage/cover_reg_top/17.gpio_intr_test.2191469187 Jul 02 08:08:51 AM PDT 24 Jul 02 08:08:57 AM PDT 24 40806021 ps
T804 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3451266986 Jul 02 08:08:41 AM PDT 24 Jul 02 08:08:45 AM PDT 24 118835283 ps
T805 /workspace/coverage/cover_reg_top/49.gpio_intr_test.3476742449 Jul 02 08:08:50 AM PDT 24 Jul 02 08:08:55 AM PDT 24 42989040 ps
T86 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.10540832 Jul 02 08:08:33 AM PDT 24 Jul 02 08:08:37 AM PDT 24 19914177 ps
T806 /workspace/coverage/cover_reg_top/11.gpio_intr_test.2409276863 Jul 02 08:08:34 AM PDT 24 Jul 02 08:08:38 AM PDT 24 49498052 ps
T807 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2003971111 Jul 02 08:08:45 AM PDT 24 Jul 02 08:08:49 AM PDT 24 22290595 ps
T808 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3610054551 Jul 02 08:08:28 AM PDT 24 Jul 02 08:08:34 AM PDT 24 14891916 ps
T809 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2264948491 Jul 02 08:08:41 AM PDT 24 Jul 02 08:08:46 AM PDT 24 41474335 ps
T810 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1107072771 Jul 02 08:08:26 AM PDT 24 Jul 02 08:08:33 AM PDT 24 38777259 ps
T811 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1256190260 Jul 02 08:08:36 AM PDT 24 Jul 02 08:08:40 AM PDT 24 38839421 ps
T812 /workspace/coverage/cover_reg_top/40.gpio_intr_test.34981311 Jul 02 08:08:51 AM PDT 24 Jul 02 08:08:57 AM PDT 24 17106395 ps
T813 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.207698491 Jul 02 08:08:35 AM PDT 24 Jul 02 08:08:39 AM PDT 24 63402748 ps
T814 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3606507974 Jul 02 08:08:41 AM PDT 24 Jul 02 08:08:46 AM PDT 24 130035587 ps
T815 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2050059027 Jul 02 08:08:38 AM PDT 24 Jul 02 08:08:43 AM PDT 24 65475549 ps
T816 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3782352168 Jul 02 08:08:29 AM PDT 24 Jul 02 08:08:35 AM PDT 24 111020917 ps
T817 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.526929553 Jul 02 08:08:40 AM PDT 24 Jul 02 08:08:45 AM PDT 24 38543741 ps
T87 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2584287430 Jul 02 08:08:22 AM PDT 24 Jul 02 08:08:29 AM PDT 24 13678616 ps
T818 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1517208611 Jul 02 08:08:41 AM PDT 24 Jul 02 08:08:45 AM PDT 24 29639288 ps
T819 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1394498456 Jul 02 08:08:29 AM PDT 24 Jul 02 08:08:36 AM PDT 24 279127561 ps
T820 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.293192205 Jul 02 08:08:46 AM PDT 24 Jul 02 08:08:49 AM PDT 24 56419870 ps
T821 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.269830011 Jul 02 08:08:40 AM PDT 24 Jul 02 08:08:46 AM PDT 24 1091658172 ps
T822 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1285089347 Jul 02 08:08:17 AM PDT 24 Jul 02 08:08:24 AM PDT 24 28321907 ps
T823 /workspace/coverage/cover_reg_top/3.gpio_intr_test.3811316531 Jul 02 08:08:23 AM PDT 24 Jul 02 08:08:29 AM PDT 24 15907816 ps
T824 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2316319056 Jul 02 08:08:22 AM PDT 24 Jul 02 08:08:30 AM PDT 24 940562347 ps
T825 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2927337946 Jul 02 08:08:41 AM PDT 24 Jul 02 08:08:45 AM PDT 24 117387216 ps
T826 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.4148575458 Jul 02 08:08:37 AM PDT 24 Jul 02 08:08:41 AM PDT 24 25676537 ps
T827 /workspace/coverage/cover_reg_top/42.gpio_intr_test.1385052900 Jul 02 08:08:53 AM PDT 24 Jul 02 08:08:58 AM PDT 24 15253289 ps
T828 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3707654724 Jul 02 08:08:29 AM PDT 24 Jul 02 08:08:35 AM PDT 24 54646775 ps
T829 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3312318893 Jul 02 08:08:28 AM PDT 24 Jul 02 08:08:35 AM PDT 24 407069621 ps
T830 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.775196379 Jul 02 08:08:29 AM PDT 24 Jul 02 08:08:36 AM PDT 24 115498458 ps
T88 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2279041821 Jul 02 08:08:51 AM PDT 24 Jul 02 08:08:57 AM PDT 24 13552444 ps
T831 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3877620715 Jul 02 08:08:22 AM PDT 24 Jul 02 08:08:29 AM PDT 24 37082685 ps
T832 /workspace/coverage/cover_reg_top/12.gpio_intr_test.3970399809 Jul 02 08:08:36 AM PDT 24 Jul 02 08:08:40 AM PDT 24 19837216 ps
T833 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1718805636 Jul 02 08:08:24 AM PDT 24 Jul 02 08:08:31 AM PDT 24 157334097 ps
T834 /workspace/coverage/cover_reg_top/41.gpio_intr_test.2393682401 Jul 02 08:08:51 AM PDT 24 Jul 02 08:08:56 AM PDT 24 13106999 ps
T835 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.764959209 Jul 02 08:08:15 AM PDT 24 Jul 02 08:08:21 AM PDT 24 44173217 ps
T836 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2132875193 Jul 02 08:08:51 AM PDT 24 Jul 02 08:08:57 AM PDT 24 671869282 ps
T837 /workspace/coverage/cover_reg_top/36.gpio_intr_test.1191573378 Jul 02 08:08:49 AM PDT 24 Jul 02 08:08:53 AM PDT 24 44197679 ps
T838 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2106544945 Jul 02 08:08:24 AM PDT 24 Jul 02 08:08:31 AM PDT 24 26938866 ps
T839 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3464809238 Jul 02 08:08:37 AM PDT 24 Jul 02 08:08:41 AM PDT 24 49631164 ps
T840 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3783511206 Jul 02 08:08:41 AM PDT 24 Jul 02 08:08:46 AM PDT 24 367429861 ps
T841 /workspace/coverage/cover_reg_top/14.gpio_intr_test.558977184 Jul 02 08:08:40 AM PDT 24 Jul 02 08:08:44 AM PDT 24 15767002 ps
T842 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.4089473546 Jul 02 07:33:22 AM PDT 24 Jul 02 07:33:23 AM PDT 24 81884326 ps
T843 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.171526352 Jul 02 07:36:38 AM PDT 24 Jul 02 07:36:47 AM PDT 24 200741807 ps
T844 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2515242552 Jul 02 07:33:34 AM PDT 24 Jul 02 07:33:35 AM PDT 24 165163255 ps
T845 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.885173136 Jul 02 07:36:17 AM PDT 24 Jul 02 07:36:19 AM PDT 24 43116944 ps
T846 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.531511818 Jul 02 07:36:20 AM PDT 24 Jul 02 07:36:23 AM PDT 24 50264575 ps
T847 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3235764697 Jul 02 07:37:17 AM PDT 24 Jul 02 07:37:23 AM PDT 24 140951308 ps
T848 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.341154588 Jul 02 07:32:15 AM PDT 24 Jul 02 07:32:17 AM PDT 24 147808496 ps
T849 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1651345555 Jul 02 07:37:27 AM PDT 24 Jul 02 07:37:36 AM PDT 24 88478060 ps
T850 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1263283661 Jul 02 07:34:48 AM PDT 24 Jul 02 07:34:50 AM PDT 24 285002333 ps
T851 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2284496721 Jul 02 07:36:17 AM PDT 24 Jul 02 07:36:19 AM PDT 24 268729635 ps
T852 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.775176067 Jul 02 07:37:29 AM PDT 24 Jul 02 07:37:39 AM PDT 24 21378210 ps
T853 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2674856611 Jul 02 07:36:51 AM PDT 24 Jul 02 07:36:57 AM PDT 24 360398477 ps
T854 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3477922489 Jul 02 07:35:07 AM PDT 24 Jul 02 07:35:09 AM PDT 24 121589272 ps
T855 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1227429353 Jul 02 07:33:05 AM PDT 24 Jul 02 07:33:06 AM PDT 24 46204008 ps
T856 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3868064608 Jul 02 07:38:09 AM PDT 24 Jul 02 07:38:27 AM PDT 24 54893890 ps
T857 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.137353726 Jul 02 07:32:22 AM PDT 24 Jul 02 07:32:23 AM PDT 24 59990712 ps
T858 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3923363657 Jul 02 07:37:34 AM PDT 24 Jul 02 07:37:47 AM PDT 24 125039655 ps
T859 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3380578905 Jul 02 07:35:33 AM PDT 24 Jul 02 07:35:34 AM PDT 24 39974613 ps
T860 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2703281053 Jul 02 07:37:21 AM PDT 24 Jul 02 07:37:30 AM PDT 24 153532507 ps
T861 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1006831530 Jul 02 07:33:49 AM PDT 24 Jul 02 07:33:50 AM PDT 24 129956690 ps
T862 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.720945870 Jul 02 07:37:17 AM PDT 24 Jul 02 07:37:24 AM PDT 24 160470634 ps
T863 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.716232632 Jul 02 07:33:43 AM PDT 24 Jul 02 07:33:46 AM PDT 24 150755855 ps
T864 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1363972415 Jul 02 07:33:43 AM PDT 24 Jul 02 07:33:46 AM PDT 24 81712838 ps
T865 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2669931316 Jul 02 07:35:35 AM PDT 24 Jul 02 07:35:38 AM PDT 24 68292300 ps
T866 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1609367467 Jul 02 07:36:34 AM PDT 24 Jul 02 07:36:42 AM PDT 24 96012701 ps
T867 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2228279807 Jul 02 07:34:33 AM PDT 24 Jul 02 07:34:35 AM PDT 24 83256256 ps
T868 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.4108037157 Jul 02 07:36:45 AM PDT 24 Jul 02 07:36:53 AM PDT 24 88354333 ps
T869 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2912112958 Jul 02 07:37:19 AM PDT 24 Jul 02 07:37:27 AM PDT 24 26786012 ps
T870 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1952334881 Jul 02 07:37:03 AM PDT 24 Jul 02 07:37:05 AM PDT 24 167066540 ps
T871 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1788022573 Jul 02 07:33:47 AM PDT 24 Jul 02 07:33:49 AM PDT 24 71888002 ps
T872 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1800106649 Jul 02 07:33:43 AM PDT 24 Jul 02 07:33:45 AM PDT 24 31589328 ps
T873 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.4248774166 Jul 02 07:36:51 AM PDT 24 Jul 02 07:36:57 AM PDT 24 56086866 ps
T874 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2130339202 Jul 02 07:36:48 AM PDT 24 Jul 02 07:36:55 AM PDT 24 133719841 ps
T875 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1643478026 Jul 02 07:37:16 AM PDT 24 Jul 02 07:37:22 AM PDT 24 60398138 ps
T876 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2027408052 Jul 02 07:31:47 AM PDT 24 Jul 02 07:31:49 AM PDT 24 103765432 ps
T877 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3942706051 Jul 02 07:36:27 AM PDT 24 Jul 02 07:36:29 AM PDT 24 68649329 ps
T878 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2452406467 Jul 02 07:37:17 AM PDT 24 Jul 02 07:37:24 AM PDT 24 48602330 ps
T879 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.199172 Jul 02 07:32:51 AM PDT 24 Jul 02 07:32:53 AM PDT 24 34661182 ps
T880 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2493424105 Jul 02 07:36:48 AM PDT 24 Jul 02 07:36:55 AM PDT 24 122266914 ps
T881 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1253953892 Jul 02 07:37:19 AM PDT 24 Jul 02 07:37:26 AM PDT 24 49597010 ps
T882 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.99841422 Jul 02 07:35:39 AM PDT 24 Jul 02 07:35:41 AM PDT 24 68417830 ps
T883 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.412805924 Jul 02 07:36:35 AM PDT 24 Jul 02 07:36:43 AM PDT 24 37666371 ps
T884 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1120649406 Jul 02 07:36:33 AM PDT 24 Jul 02 07:36:41 AM PDT 24 479895082 ps
T885 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3785777795 Jul 02 07:36:40 AM PDT 24 Jul 02 07:36:49 AM PDT 24 441500739 ps
T886 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3391221333 Jul 02 07:36:19 AM PDT 24 Jul 02 07:36:22 AM PDT 24 74071464 ps
T887 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2982595725 Jul 02 07:36:31 AM PDT 24 Jul 02 07:36:38 AM PDT 24 67503267 ps
T888 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3679877190 Jul 02 07:36:34 AM PDT 24 Jul 02 07:36:42 AM PDT 24 82135811 ps
T889 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1762302207 Jul 02 07:38:14 AM PDT 24 Jul 02 07:38:34 AM PDT 24 65949341 ps
T890 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2315924995 Jul 02 07:36:21 AM PDT 24 Jul 02 07:36:24 AM PDT 24 34832035 ps
T891 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.4189570609 Jul 02 07:37:16 AM PDT 24 Jul 02 07:37:23 AM PDT 24 79240024 ps
T892 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1954945571 Jul 02 07:33:50 AM PDT 24 Jul 02 07:33:52 AM PDT 24 104078400 ps
T893 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2556016006 Jul 02 07:36:19 AM PDT 24 Jul 02 07:36:22 AM PDT 24 61542957 ps
T894 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2210613487 Jul 02 07:36:56 AM PDT 24 Jul 02 07:36:59 AM PDT 24 189846644 ps
T895 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1389859454 Jul 02 07:35:34 AM PDT 24 Jul 02 07:35:36 AM PDT 24 32798351 ps
T896 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3335689123 Jul 02 07:32:50 AM PDT 24 Jul 02 07:32:51 AM PDT 24 38060706 ps
T897 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2201440515 Jul 02 07:36:46 AM PDT 24 Jul 02 07:36:54 AM PDT 24 54394288 ps
T898 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3487088157 Jul 02 07:37:41 AM PDT 24 Jul 02 07:37:54 AM PDT 24 68320480 ps
T899 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3111749532 Jul 02 07:37:25 AM PDT 24 Jul 02 07:37:35 AM PDT 24 116863464 ps
T900 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2719688570 Jul 02 07:37:05 AM PDT 24 Jul 02 07:37:08 AM PDT 24 228865960 ps
T901 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4291299826 Jul 02 07:36:27 AM PDT 24 Jul 02 07:36:30 AM PDT 24 70027344 ps
T902 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2335203895 Jul 02 07:37:26 AM PDT 24 Jul 02 07:37:35 AM PDT 24 17864580 ps
T903 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3613189516 Jul 02 07:36:49 AM PDT 24 Jul 02 07:36:55 AM PDT 24 81167113 ps
T904 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3079670987 Jul 02 07:36:28 AM PDT 24 Jul 02 07:36:32 AM PDT 24 143593410 ps
T905 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2594005201 Jul 02 07:36:31 AM PDT 24 Jul 02 07:36:38 AM PDT 24 238549709 ps
T906 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2740889897 Jul 02 07:37:35 AM PDT 24 Jul 02 07:37:47 AM PDT 24 31778256 ps
T907 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.146957620 Jul 02 07:36:57 AM PDT 24 Jul 02 07:36:59 AM PDT 24 151275435 ps
T908 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1956114635 Jul 02 07:37:16 AM PDT 24 Jul 02 07:37:22 AM PDT 24 183759197 ps
T909 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1202677614 Jul 02 07:35:20 AM PDT 24 Jul 02 07:35:22 AM PDT 24 198767947 ps
T910 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.870456165 Jul 02 07:33:46 AM PDT 24 Jul 02 07:33:48 AM PDT 24 44355936 ps
T911 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.100947645 Jul 02 07:37:13 AM PDT 24 Jul 02 07:37:17 AM PDT 24 116368652 ps
T912 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3765341793 Jul 02 07:36:17 AM PDT 24 Jul 02 07:36:19 AM PDT 24 31111348 ps
T913 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3027076211 Jul 02 07:35:29 AM PDT 24 Jul 02 07:35:31 AM PDT 24 72789569 ps
T914 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3573892270 Jul 02 07:36:31 AM PDT 24 Jul 02 07:36:38 AM PDT 24 33546524 ps
T915 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.448402603 Jul 02 07:37:26 AM PDT 24 Jul 02 07:37:35 AM PDT 24 64850243 ps
T916 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.575268912 Jul 02 07:32:06 AM PDT 24 Jul 02 07:32:08 AM PDT 24 79806468 ps
T917 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3972667624 Jul 02 07:35:53 AM PDT 24 Jul 02 07:35:55 AM PDT 24 185498390 ps
T918 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2990281294 Jul 02 07:37:25 AM PDT 24 Jul 02 07:37:34 AM PDT 24 39809449 ps
T919 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2442474158 Jul 02 07:31:48 AM PDT 24 Jul 02 07:31:49 AM PDT 24 191329865 ps
T920 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.258054141 Jul 02 07:36:38 AM PDT 24 Jul 02 07:36:47 AM PDT 24 196296244 ps
T921 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2377824177 Jul 02 07:37:20 AM PDT 24 Jul 02 07:37:28 AM PDT 24 146887521 ps
T922 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2332360894 Jul 02 07:32:19 AM PDT 24 Jul 02 07:32:21 AM PDT 24 73821571 ps
T923 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3981446351 Jul 02 07:33:50 AM PDT 24 Jul 02 07:33:51 AM PDT 24 157802065 ps
T924 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2522492728 Jul 02 07:37:17 AM PDT 24 Jul 02 07:37:24 AM PDT 24 167725754 ps
T925 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2369828015 Jul 02 07:37:17 AM PDT 24 Jul 02 07:37:24 AM PDT 24 52034864 ps
T926 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3000656991 Jul 02 07:31:54 AM PDT 24 Jul 02 07:31:56 AM PDT 24 187612128 ps
T927 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1251495688 Jul 02 07:36:37 AM PDT 24 Jul 02 07:36:47 AM PDT 24 41512046 ps
T928 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1898829598 Jul 02 07:35:49 AM PDT 24 Jul 02 07:35:51 AM PDT 24 40023142 ps
T929 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1533265284 Jul 02 07:36:27 AM PDT 24 Jul 02 07:36:29 AM PDT 24 122288379 ps
T930 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.6448447 Jul 02 07:37:19 AM PDT 24 Jul 02 07:37:27 AM PDT 24 74890374 ps
T931 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.788503265 Jul 02 07:34:34 AM PDT 24 Jul 02 07:34:36 AM PDT 24 30453002 ps
T932 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.158489051 Jul 02 07:31:38 AM PDT 24 Jul 02 07:31:41 AM PDT 24 184372764 ps
T933 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2232192632 Jul 02 07:34:31 AM PDT 24 Jul 02 07:34:33 AM PDT 24 231757496 ps
T934 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1866771531 Jul 02 07:37:26 AM PDT 24 Jul 02 07:37:35 AM PDT 24 93375279 ps
T935 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3888967798 Jul 02 07:33:06 AM PDT 24 Jul 02 07:33:08 AM PDT 24 102724908 ps
T936 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2411766538 Jul 02 07:36:12 AM PDT 24 Jul 02 07:36:14 AM PDT 24 80480887 ps
T937 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.731173846 Jul 02 07:32:51 AM PDT 24 Jul 02 07:32:53 AM PDT 24 52601113 ps
T938 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2894416131 Jul 02 07:37:17 AM PDT 24 Jul 02 07:37:24 AM PDT 24 37789070 ps
T939 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.4147346517 Jul 02 07:37:17 AM PDT 24 Jul 02 07:37:24 AM PDT 24 101520268 ps
T940 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1058233054 Jul 02 07:32:32 AM PDT 24 Jul 02 07:32:34 AM PDT 24 161707771 ps
T941 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3942763388 Jul 02 07:36:01 AM PDT 24 Jul 02 07:36:03 AM PDT 24 348869335 ps

Test location /workspace/coverage/default/43.gpio_full_random.2604112865
Short name T14
Test name
Test status
Simulation time 79716128 ps
CPU time 0.77 seconds
Started Jul 02 07:38:54 AM PDT 24
Finished Jul 02 07:39:09 AM PDT 24
Peak memory 196468 kb
Host smart-4c896389-ba66-405f-8818-9d7bdd3d8ac0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604112865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2604112865
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.1394314290
Short name T12
Test name
Test status
Simulation time 195856403 ps
CPU time 1.76 seconds
Started Jul 02 07:39:02 AM PDT 24
Finished Jul 02 07:39:14 AM PDT 24
Peak memory 197300 kb
Host smart-13ca680b-2596-48b1-9832-ca5b619edf4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394314290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.1394314290
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.981821608
Short name T100
Test name
Test status
Simulation time 61099896 ps
CPU time 1.69 seconds
Started Jul 02 07:37:31 AM PDT 24
Finished Jul 02 07:37:42 AM PDT 24
Peak memory 198512 kb
Host smart-746066d7-d546-458a-a5d0-8ccd8f143a40
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981821608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.gpio_intr_with_filter_rand_intr_event.981821608
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.167022278
Short name T27
Test name
Test status
Simulation time 59060713898 ps
CPU time 842.71 seconds
Started Jul 02 07:37:54 AM PDT 24
Finished Jul 02 07:52:07 AM PDT 24
Peak memory 198732 kb
Host smart-a0d9b722-b7e0-47c6-8c1b-b503a2c7730e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=167022278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.167022278
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2741950999
Short name T2
Test name
Test status
Simulation time 349471834 ps
CPU time 4.11 seconds
Started Jul 02 07:38:42 AM PDT 24
Finished Jul 02 07:39:01 AM PDT 24
Peak memory 198452 kb
Host smart-f841e9a0-7c99-4766-bfdd-1da565471b29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741950999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2741950999
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2301149292
Short name T70
Test name
Test status
Simulation time 58582419 ps
CPU time 0.85 seconds
Started Jul 02 08:08:17 AM PDT 24
Finished Jul 02 08:08:23 AM PDT 24
Peak memory 196716 kb
Host smart-d98abfe9-0bd3-4edd-b23f-8a13928a15a2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301149292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.2301149292
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.195838860
Short name T30
Test name
Test status
Simulation time 1032449109 ps
CPU time 1.19 seconds
Started Jul 02 08:08:29 AM PDT 24
Finished Jul 02 08:08:35 AM PDT 24
Peak memory 198752 kb
Host smart-0b93e967-7d44-49d9-9124-e50e2bb42549
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195838860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.gpio_tl_intg_err.195838860
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/12.gpio_alert_test.2795832653
Short name T134
Test name
Test status
Simulation time 18780748 ps
CPU time 0.59 seconds
Started Jul 02 07:37:50 AM PDT 24
Finished Jul 02 07:38:01 AM PDT 24
Peak memory 195356 kb
Host smart-16cd4a30-228c-4c7d-a36b-33777097978e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795832653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.2795832653
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2637403643
Short name T34
Test name
Test status
Simulation time 614147676 ps
CPU time 1.06 seconds
Started Jul 02 07:36:56 AM PDT 24
Finished Jul 02 07:36:59 AM PDT 24
Peak memory 213320 kb
Host smart-c4541c06-e915-4235-afc9-2b878d3dfb13
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637403643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2637403643
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3336921930
Short name T92
Test name
Test status
Simulation time 15228026 ps
CPU time 0.69 seconds
Started Jul 02 08:08:24 AM PDT 24
Finished Jul 02 08:08:31 AM PDT 24
Peak memory 195824 kb
Host smart-b3136232-2fc4-48d5-935a-ccfdcea77ca8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336921930 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3336921930
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1361258222
Short name T99
Test name
Test status
Simulation time 127444394 ps
CPU time 1.4 seconds
Started Jul 02 08:08:37 AM PDT 24
Finished Jul 02 08:08:42 AM PDT 24
Peak memory 198704 kb
Host smart-3a5e343c-1e07-489b-9c4e-db231505b5bf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361258222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1361258222
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.2250429594
Short name T113
Test name
Test status
Simulation time 197817953 ps
CPU time 9.47 seconds
Started Jul 02 07:37:46 AM PDT 24
Finished Jul 02 07:38:06 AM PDT 24
Peak memory 197576 kb
Host smart-78ce844b-8ce4-45f6-bc15-c98ee080ea3d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250429594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.2250429594
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1415433181
Short name T97
Test name
Test status
Simulation time 151285536 ps
CPU time 2.92 seconds
Started Jul 02 08:08:20 AM PDT 24
Finished Jul 02 08:08:29 AM PDT 24
Peak memory 197608 kb
Host smart-6b188e4c-48b9-4b39-b3dc-90029591c172
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415433181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1415433181
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1285089347
Short name T822
Test name
Test status
Simulation time 28321907 ps
CPU time 0.62 seconds
Started Jul 02 08:08:17 AM PDT 24
Finished Jul 02 08:08:24 AM PDT 24
Peak memory 195672 kb
Host smart-db47ad35-65dc-4e4d-8bd5-79543e2f4bca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285089347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1285089347
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1764280769
Short name T751
Test name
Test status
Simulation time 115651146 ps
CPU time 0.9 seconds
Started Jul 02 08:08:17 AM PDT 24
Finished Jul 02 08:08:24 AM PDT 24
Peak memory 198592 kb
Host smart-7f842629-79f9-42a9-87e7-a0e85e839774
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764280769 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1764280769
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.764959209
Short name T835
Test name
Test status
Simulation time 44173217 ps
CPU time 0.67 seconds
Started Jul 02 08:08:15 AM PDT 24
Finished Jul 02 08:08:21 AM PDT 24
Peak memory 196232 kb
Host smart-082f6590-71f3-4e64-8b33-177a239bad1b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764959209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.764959209
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.4017489638
Short name T744
Test name
Test status
Simulation time 88883120 ps
CPU time 0.6 seconds
Started Jul 02 08:08:17 AM PDT 24
Finished Jul 02 08:08:23 AM PDT 24
Peak memory 194388 kb
Host smart-0d357571-0921-48ee-a1f6-c829d9e32e95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017489638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.4017489638
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3631987066
Short name T801
Test name
Test status
Simulation time 55659036 ps
CPU time 0.75 seconds
Started Jul 02 08:08:18 AM PDT 24
Finished Jul 02 08:08:24 AM PDT 24
Peak memory 196756 kb
Host smart-6d1ffb63-7f09-490a-b9eb-1a6465b0f18f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631987066 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3631987066
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1281974884
Short name T782
Test name
Test status
Simulation time 305503511 ps
CPU time 1.9 seconds
Started Jul 02 08:08:16 AM PDT 24
Finished Jul 02 08:08:24 AM PDT 24
Peak memory 198760 kb
Host smart-f10b18d4-7dd3-4377-96e9-22e6bd34a898
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281974884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.1281974884
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.997244119
Short name T39
Test name
Test status
Simulation time 85177925 ps
CPU time 1.12 seconds
Started Jul 02 08:08:17 AM PDT 24
Finished Jul 02 08:08:23 AM PDT 24
Peak memory 198724 kb
Host smart-c0afd517-c397-4ca2-af96-f784a8cc86f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997244119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.gpio_tl_intg_err.997244119
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3877620715
Short name T831
Test name
Test status
Simulation time 37082685 ps
CPU time 0.72 seconds
Started Jul 02 08:08:22 AM PDT 24
Finished Jul 02 08:08:29 AM PDT 24
Peak memory 195164 kb
Host smart-bc9b8046-b3e5-4aef-8166-003c61ed9c37
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877620715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.3877620715
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.113499673
Short name T96
Test name
Test status
Simulation time 226188218 ps
CPU time 2.11 seconds
Started Jul 02 08:08:22 AM PDT 24
Finished Jul 02 08:08:30 AM PDT 24
Peak memory 197440 kb
Host smart-cd51b48f-7853-4343-aabb-2ce11e7a955c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113499673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.113499673
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2780129265
Short name T74
Test name
Test status
Simulation time 67996382 ps
CPU time 0.6 seconds
Started Jul 02 08:08:24 AM PDT 24
Finished Jul 02 08:08:30 AM PDT 24
Peak memory 195316 kb
Host smart-e81a1fd6-ea28-4e5e-b50e-83c466f0467e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780129265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2780129265
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3595674849
Short name T766
Test name
Test status
Simulation time 143633028 ps
CPU time 1.08 seconds
Started Jul 02 08:08:22 AM PDT 24
Finished Jul 02 08:08:29 AM PDT 24
Peak memory 198596 kb
Host smart-b618723c-8de1-48ee-89d0-55885d8f4ed8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595674849 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3595674849
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2563571134
Short name T760
Test name
Test status
Simulation time 31144081 ps
CPU time 0.59 seconds
Started Jul 02 08:08:20 AM PDT 24
Finished Jul 02 08:08:27 AM PDT 24
Peak memory 195492 kb
Host smart-7799716f-1642-4a45-b649-a6acb92370b0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563571134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.2563571134
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1010719567
Short name T747
Test name
Test status
Simulation time 196605419 ps
CPU time 0.61 seconds
Started Jul 02 08:08:21 AM PDT 24
Finished Jul 02 08:08:28 AM PDT 24
Peak memory 194996 kb
Host smart-51908604-1d45-46a8-978a-45e6e288595d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010719567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1010719567
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.4086341695
Short name T789
Test name
Test status
Simulation time 129510713 ps
CPU time 2.33 seconds
Started Jul 02 08:08:22 AM PDT 24
Finished Jul 02 08:08:31 AM PDT 24
Peak memory 198800 kb
Host smart-a46e221a-49ff-4feb-a065-04754d49a8ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086341695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.4086341695
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1306762664
Short name T40
Test name
Test status
Simulation time 131360485 ps
CPU time 0.84 seconds
Started Jul 02 08:08:24 AM PDT 24
Finished Jul 02 08:08:31 AM PDT 24
Peak memory 197616 kb
Host smart-f9be9a02-28a6-4fd9-ad7d-8d4b3982ba2a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306762664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.1306762664
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2050059027
Short name T815
Test name
Test status
Simulation time 65475549 ps
CPU time 1.02 seconds
Started Jul 02 08:08:38 AM PDT 24
Finished Jul 02 08:08:43 AM PDT 24
Peak memory 198540 kb
Host smart-13f05b3e-178f-4bc9-83a1-cab7582e8355
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050059027 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2050059027
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.10540832
Short name T86
Test name
Test status
Simulation time 19914177 ps
CPU time 0.57 seconds
Started Jul 02 08:08:33 AM PDT 24
Finished Jul 02 08:08:37 AM PDT 24
Peak memory 193996 kb
Host smart-93dec9c4-1853-4eb6-959a-0edb965b009b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10540832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_
csr_rw.10540832
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.2955359496
Short name T722
Test name
Test status
Simulation time 67913640 ps
CPU time 0.6 seconds
Started Jul 02 08:08:40 AM PDT 24
Finished Jul 02 08:08:44 AM PDT 24
Peak memory 194344 kb
Host smart-4ec93262-6875-4b81-807e-f414bf4565a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955359496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.2955359496
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2927337946
Short name T825
Test name
Test status
Simulation time 117387216 ps
CPU time 0.87 seconds
Started Jul 02 08:08:41 AM PDT 24
Finished Jul 02 08:08:45 AM PDT 24
Peak memory 197488 kb
Host smart-fa240de1-d157-4d57-921b-418e4c5eb4fb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927337946 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.2927337946
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2492632018
Short name T764
Test name
Test status
Simulation time 50943410 ps
CPU time 2.53 seconds
Started Jul 02 08:08:35 AM PDT 24
Finished Jul 02 08:08:41 AM PDT 24
Peak memory 198748 kb
Host smart-0cecd584-7973-4dae-a869-8dd6b4514246
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492632018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2492632018
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.4148575458
Short name T826
Test name
Test status
Simulation time 25676537 ps
CPU time 0.71 seconds
Started Jul 02 08:08:37 AM PDT 24
Finished Jul 02 08:08:41 AM PDT 24
Peak memory 198620 kb
Host smart-c5b9d24d-5608-4065-9f78-573e1d367c39
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148575458 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.4148575458
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2060253518
Short name T772
Test name
Test status
Simulation time 15186571 ps
CPU time 0.59 seconds
Started Jul 02 08:08:35 AM PDT 24
Finished Jul 02 08:08:38 AM PDT 24
Peak memory 194632 kb
Host smart-99fb7866-17fe-433f-b14e-c67d30cbb573
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060253518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.2060253518
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2409276863
Short name T806
Test name
Test status
Simulation time 49498052 ps
CPU time 0.64 seconds
Started Jul 02 08:08:34 AM PDT 24
Finished Jul 02 08:08:38 AM PDT 24
Peak memory 194440 kb
Host smart-c42f94bf-fabf-4222-be4a-3df7f3a95cb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409276863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2409276863
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3305554908
Short name T89
Test name
Test status
Simulation time 50199523 ps
CPU time 0.69 seconds
Started Jul 02 08:08:41 AM PDT 24
Finished Jul 02 08:08:45 AM PDT 24
Peak memory 195180 kb
Host smart-26b8e343-aaab-4e18-bad5-0c5d33f9f877
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305554908 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3305554908
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.207698491
Short name T813
Test name
Test status
Simulation time 63402748 ps
CPU time 1.07 seconds
Started Jul 02 08:08:35 AM PDT 24
Finished Jul 02 08:08:39 AM PDT 24
Peak memory 198752 kb
Host smart-33c69e26-3d02-44b6-b4ed-72714a93424b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207698491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.207698491
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2526560057
Short name T41
Test name
Test status
Simulation time 164525505 ps
CPU time 1.25 seconds
Started Jul 02 08:08:37 AM PDT 24
Finished Jul 02 08:08:42 AM PDT 24
Peak memory 198712 kb
Host smart-bf6e91c3-7eb3-4ebd-a387-8ec153fa9f45
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526560057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.2526560057
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1313998775
Short name T777
Test name
Test status
Simulation time 32807465 ps
CPU time 0.96 seconds
Started Jul 02 08:08:39 AM PDT 24
Finished Jul 02 08:08:44 AM PDT 24
Peak memory 198652 kb
Host smart-1793dec8-09d7-4b7d-b21e-5c8c34538360
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313998775 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1313998775
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1924975730
Short name T779
Test name
Test status
Simulation time 12836993 ps
CPU time 0.62 seconds
Started Jul 02 08:08:39 AM PDT 24
Finished Jul 02 08:08:42 AM PDT 24
Peak memory 195776 kb
Host smart-02ba6aa5-05a2-49e8-a55e-15281974a849
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924975730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1924975730
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.3970399809
Short name T832
Test name
Test status
Simulation time 19837216 ps
CPU time 0.58 seconds
Started Jul 02 08:08:36 AM PDT 24
Finished Jul 02 08:08:40 AM PDT 24
Peak memory 194256 kb
Host smart-425c82bd-417a-49b1-8273-7f68ae2c1dc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970399809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.3970399809
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3169433871
Short name T93
Test name
Test status
Simulation time 36042260 ps
CPU time 0.83 seconds
Started Jul 02 08:08:39 AM PDT 24
Finished Jul 02 08:08:43 AM PDT 24
Peak memory 197188 kb
Host smart-881433d5-86ce-4a48-9c66-67581b483ecc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169433871 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.3169433871
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3464809238
Short name T839
Test name
Test status
Simulation time 49631164 ps
CPU time 1.37 seconds
Started Jul 02 08:08:37 AM PDT 24
Finished Jul 02 08:08:41 AM PDT 24
Peak memory 198680 kb
Host smart-d993686b-b0ca-408f-9abe-5975df7379d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464809238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3464809238
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1053080944
Short name T749
Test name
Test status
Simulation time 427795152 ps
CPU time 1.11 seconds
Started Jul 02 08:08:39 AM PDT 24
Finished Jul 02 08:08:44 AM PDT 24
Peak memory 198356 kb
Host smart-a0d3837b-ef5c-41df-9083-e5a910550215
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053080944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1053080944
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1256190260
Short name T811
Test name
Test status
Simulation time 38839421 ps
CPU time 1.07 seconds
Started Jul 02 08:08:36 AM PDT 24
Finished Jul 02 08:08:40 AM PDT 24
Peak memory 198596 kb
Host smart-511980d4-e7fb-4fb3-be69-ee09ff145df8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256190260 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1256190260
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3148608771
Short name T746
Test name
Test status
Simulation time 13512407 ps
CPU time 0.63 seconds
Started Jul 02 08:08:34 AM PDT 24
Finished Jul 02 08:08:37 AM PDT 24
Peak memory 195404 kb
Host smart-d72d8186-9fc5-4b29-9cfa-e1136ca8f930
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148608771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3148608771
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2333407634
Short name T736
Test name
Test status
Simulation time 35616415 ps
CPU time 0.56 seconds
Started Jul 02 08:08:41 AM PDT 24
Finished Jul 02 08:08:45 AM PDT 24
Peak memory 195008 kb
Host smart-8f76b07e-4a07-4b1e-beef-aca3a1cac899
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333407634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2333407634
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1582445241
Short name T73
Test name
Test status
Simulation time 27793792 ps
CPU time 0.75 seconds
Started Jul 02 08:08:35 AM PDT 24
Finished Jul 02 08:08:39 AM PDT 24
Peak memory 196444 kb
Host smart-68c048ae-6f91-4baa-ae9f-942bfacab201
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582445241 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1582445241
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.526929553
Short name T817
Test name
Test status
Simulation time 38543741 ps
CPU time 1.59 seconds
Started Jul 02 08:08:40 AM PDT 24
Finished Jul 02 08:08:45 AM PDT 24
Peak memory 198720 kb
Host smart-48560da0-9a00-40fe-833e-9c1942841789
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526929553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.526929553
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1691077627
Short name T37
Test name
Test status
Simulation time 77079527 ps
CPU time 1.14 seconds
Started Jul 02 08:08:36 AM PDT 24
Finished Jul 02 08:08:40 AM PDT 24
Peak memory 198804 kb
Host smart-b9675819-a42e-448b-80d3-4ae9a9d969ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691077627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.1691077627
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.293192205
Short name T820
Test name
Test status
Simulation time 56419870 ps
CPU time 0.67 seconds
Started Jul 02 08:08:46 AM PDT 24
Finished Jul 02 08:08:49 AM PDT 24
Peak memory 197140 kb
Host smart-42b6043e-5252-456e-b67e-6a7364e00d36
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293192205 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.293192205
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.4237828916
Short name T796
Test name
Test status
Simulation time 16471122 ps
CPU time 0.65 seconds
Started Jul 02 08:08:40 AM PDT 24
Finished Jul 02 08:08:44 AM PDT 24
Peak memory 196156 kb
Host smart-486d5504-4ec3-4d73-af43-3b9b54fd3b47
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237828916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.4237828916
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.558977184
Short name T841
Test name
Test status
Simulation time 15767002 ps
CPU time 0.62 seconds
Started Jul 02 08:08:40 AM PDT 24
Finished Jul 02 08:08:44 AM PDT 24
Peak memory 195060 kb
Host smart-78cb25b2-8898-424d-8808-10f2f01f63a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558977184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.558977184
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.4031348633
Short name T75
Test name
Test status
Simulation time 29549659 ps
CPU time 0.67 seconds
Started Jul 02 08:08:44 AM PDT 24
Finished Jul 02 08:08:47 AM PDT 24
Peak memory 195504 kb
Host smart-fa378bb7-6d4e-4ab9-ba85-9bc086d0e9ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031348633 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.4031348633
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.269830011
Short name T821
Test name
Test status
Simulation time 1091658172 ps
CPU time 2.95 seconds
Started Jul 02 08:08:40 AM PDT 24
Finished Jul 02 08:08:46 AM PDT 24
Peak memory 198704 kb
Host smart-282098fe-83ca-494b-9f40-520e8328bf7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269830011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.269830011
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.853637145
Short name T800
Test name
Test status
Simulation time 116380760 ps
CPU time 1.48 seconds
Started Jul 02 08:08:46 AM PDT 24
Finished Jul 02 08:08:50 AM PDT 24
Peak memory 198660 kb
Host smart-7f2e07a8-3181-4108-8d20-2597515ea191
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853637145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.gpio_tl_intg_err.853637145
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2579284009
Short name T790
Test name
Test status
Simulation time 109893808 ps
CPU time 1.3 seconds
Started Jul 02 08:08:40 AM PDT 24
Finished Jul 02 08:08:45 AM PDT 24
Peak memory 198756 kb
Host smart-7ea9e1a9-67fe-41e4-a9e1-a42a34e48375
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579284009 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2579284009
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3451266986
Short name T804
Test name
Test status
Simulation time 118835283 ps
CPU time 0.62 seconds
Started Jul 02 08:08:41 AM PDT 24
Finished Jul 02 08:08:45 AM PDT 24
Peak memory 195636 kb
Host smart-bc5c61a3-42d6-496f-aa9f-5f2ec1313262
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451266986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.3451266986
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.566264008
Short name T733
Test name
Test status
Simulation time 21246272 ps
CPU time 0.57 seconds
Started Jul 02 08:08:39 AM PDT 24
Finished Jul 02 08:08:42 AM PDT 24
Peak memory 194388 kb
Host smart-e4fda3a8-fb33-45d3-a718-5f1b1e068bc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566264008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.566264008
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1213153515
Short name T91
Test name
Test status
Simulation time 61127157 ps
CPU time 0.84 seconds
Started Jul 02 08:08:40 AM PDT 24
Finished Jul 02 08:08:44 AM PDT 24
Peak memory 197664 kb
Host smart-c40d5bc4-ca5e-4f2b-ae2a-d01aa1c0c339
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213153515 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1213153515
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3606507974
Short name T814
Test name
Test status
Simulation time 130035587 ps
CPU time 1.73 seconds
Started Jul 02 08:08:41 AM PDT 24
Finished Jul 02 08:08:46 AM PDT 24
Peak memory 198716 kb
Host smart-ebcb320f-7d09-44f4-9d50-2bbccc584fe5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606507974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.3606507974
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3826276427
Short name T784
Test name
Test status
Simulation time 398811518 ps
CPU time 0.92 seconds
Started Jul 02 08:08:40 AM PDT 24
Finished Jul 02 08:08:44 AM PDT 24
Peak memory 197864 kb
Host smart-d2f55a81-dd4a-456e-9cae-b82e3c69da43
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826276427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3826276427
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2264948491
Short name T809
Test name
Test status
Simulation time 41474335 ps
CPU time 0.74 seconds
Started Jul 02 08:08:41 AM PDT 24
Finished Jul 02 08:08:46 AM PDT 24
Peak memory 198624 kb
Host smart-37a98fe5-b70d-4558-9e66-70805ce53704
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264948491 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2264948491
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2933995317
Short name T795
Test name
Test status
Simulation time 11777996 ps
CPU time 0.63 seconds
Started Jul 02 08:08:46 AM PDT 24
Finished Jul 02 08:08:49 AM PDT 24
Peak memory 195772 kb
Host smart-30b11969-e16d-4ca4-875d-469834911b6a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933995317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.2933995317
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.504357095
Short name T755
Test name
Test status
Simulation time 15406135 ps
CPU time 0.62 seconds
Started Jul 02 08:08:41 AM PDT 24
Finished Jul 02 08:08:45 AM PDT 24
Peak memory 195048 kb
Host smart-c215076d-af57-4a96-a27f-ff849891322a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504357095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.504357095
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3783511206
Short name T840
Test name
Test status
Simulation time 367429861 ps
CPU time 0.82 seconds
Started Jul 02 08:08:41 AM PDT 24
Finished Jul 02 08:08:46 AM PDT 24
Peak memory 197016 kb
Host smart-4d661c68-9992-4029-adc6-1fb23813ae82
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783511206 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.3783511206
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1517208611
Short name T818
Test name
Test status
Simulation time 29639288 ps
CPU time 0.97 seconds
Started Jul 02 08:08:41 AM PDT 24
Finished Jul 02 08:08:45 AM PDT 24
Peak memory 198596 kb
Host smart-1fea2070-48f1-4dbc-a780-b9aeb53b5c0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517208611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1517208611
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2132875193
Short name T836
Test name
Test status
Simulation time 671869282 ps
CPU time 1.43 seconds
Started Jul 02 08:08:51 AM PDT 24
Finished Jul 02 08:08:57 AM PDT 24
Peak memory 198748 kb
Host smart-2c4af8c6-2317-42ff-8575-543c93d10a6f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132875193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2132875193
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1156941114
Short name T737
Test name
Test status
Simulation time 74188820 ps
CPU time 0.76 seconds
Started Jul 02 08:08:39 AM PDT 24
Finished Jul 02 08:08:43 AM PDT 24
Peak memory 198616 kb
Host smart-8494d99a-51f0-4f20-9652-6f4f39ff25fb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156941114 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.1156941114
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2674769831
Short name T77
Test name
Test status
Simulation time 70078954 ps
CPU time 0.62 seconds
Started Jul 02 08:08:51 AM PDT 24
Finished Jul 02 08:08:57 AM PDT 24
Peak memory 195636 kb
Host smart-b538b788-6a91-46dc-8309-4e5bccbb03f9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674769831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.2674769831
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.2191469187
Short name T803
Test name
Test status
Simulation time 40806021 ps
CPU time 0.6 seconds
Started Jul 02 08:08:51 AM PDT 24
Finished Jul 02 08:08:57 AM PDT 24
Peak memory 194404 kb
Host smart-9dfe1ea1-d269-4c5b-9f9d-26ea35b07eca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191469187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.2191469187
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2320068103
Short name T773
Test name
Test status
Simulation time 27287169 ps
CPU time 0.74 seconds
Started Jul 02 08:08:44 AM PDT 24
Finished Jul 02 08:08:47 AM PDT 24
Peak memory 196904 kb
Host smart-791a4061-5cc2-4d90-a3cc-39137714b4c0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320068103 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.2320068103
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.877852212
Short name T727
Test name
Test status
Simulation time 106167116 ps
CPU time 3.6 seconds
Started Jul 02 08:08:41 AM PDT 24
Finished Jul 02 08:08:48 AM PDT 24
Peak memory 198724 kb
Host smart-b84d4ea0-a15a-437e-af42-b86a12abf013
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877852212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.877852212
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2344425309
Short name T98
Test name
Test status
Simulation time 1874501562 ps
CPU time 1.4 seconds
Started Jul 02 08:08:51 AM PDT 24
Finished Jul 02 08:08:57 AM PDT 24
Peak memory 198788 kb
Host smart-0d5e9dd5-1fd9-4659-ad8b-f073429421d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344425309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.2344425309
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.4167045095
Short name T771
Test name
Test status
Simulation time 104923618 ps
CPU time 0.81 seconds
Started Jul 02 08:08:50 AM PDT 24
Finished Jul 02 08:08:55 AM PDT 24
Peak memory 198640 kb
Host smart-f12075c5-6d0c-4428-9e1a-0a4fcdd76388
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167045095 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.4167045095
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2279041821
Short name T88
Test name
Test status
Simulation time 13552444 ps
CPU time 0.6 seconds
Started Jul 02 08:08:51 AM PDT 24
Finished Jul 02 08:08:57 AM PDT 24
Peak memory 195368 kb
Host smart-ac21bdd7-8a05-412b-9a42-082bc657f5f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279041821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2279041821
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.4082738436
Short name T725
Test name
Test status
Simulation time 48289343 ps
CPU time 0.61 seconds
Started Jul 02 08:08:48 AM PDT 24
Finished Jul 02 08:08:52 AM PDT 24
Peak memory 194356 kb
Host smart-95907b13-c8b7-4861-9eb0-a5d8efa7234b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082738436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.4082738436
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1240547818
Short name T90
Test name
Test status
Simulation time 31611945 ps
CPU time 0.81 seconds
Started Jul 02 08:08:43 AM PDT 24
Finished Jul 02 08:08:47 AM PDT 24
Peak memory 197032 kb
Host smart-51bc0d53-c80e-4899-a082-4eedeea6653a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240547818 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1240547818
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1322832505
Short name T748
Test name
Test status
Simulation time 45271384 ps
CPU time 2.21 seconds
Started Jul 02 08:08:40 AM PDT 24
Finished Jul 02 08:08:45 AM PDT 24
Peak memory 198744 kb
Host smart-e498454d-c582-41f6-851b-052d4bf2ca8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322832505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.1322832505
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2497389522
Short name T38
Test name
Test status
Simulation time 114053815 ps
CPU time 1.39 seconds
Started Jul 02 08:08:43 AM PDT 24
Finished Jul 02 08:08:47 AM PDT 24
Peak memory 198996 kb
Host smart-2098c257-df4b-4a71-a1c7-39ee3faf1fa2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497389522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2497389522
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2003971111
Short name T807
Test name
Test status
Simulation time 22290595 ps
CPU time 1.06 seconds
Started Jul 02 08:08:45 AM PDT 24
Finished Jul 02 08:08:49 AM PDT 24
Peak memory 198616 kb
Host smart-dd5b77cd-1b6d-4429-8f9a-cf2370cb2b2b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003971111 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2003971111
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1441217010
Short name T80
Test name
Test status
Simulation time 36688368 ps
CPU time 0.63 seconds
Started Jul 02 08:08:45 AM PDT 24
Finished Jul 02 08:08:48 AM PDT 24
Peak memory 195812 kb
Host smart-21f2c460-f41d-4140-a367-597b21c6cbef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441217010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1441217010
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1580900504
Short name T776
Test name
Test status
Simulation time 44556398 ps
CPU time 0.62 seconds
Started Jul 02 08:08:44 AM PDT 24
Finished Jul 02 08:08:47 AM PDT 24
Peak memory 194408 kb
Host smart-bea849c4-e4ce-4066-9f9c-7407c4596313
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580900504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1580900504
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3898727679
Short name T762
Test name
Test status
Simulation time 15665797 ps
CPU time 0.64 seconds
Started Jul 02 08:08:50 AM PDT 24
Finished Jul 02 08:08:55 AM PDT 24
Peak memory 195336 kb
Host smart-0007149c-8908-45d2-80b1-92488877fc80
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898727679 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3898727679
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1771561087
Short name T799
Test name
Test status
Simulation time 411663492 ps
CPU time 2.33 seconds
Started Jul 02 08:08:46 AM PDT 24
Finished Jul 02 08:08:50 AM PDT 24
Peak memory 198736 kb
Host smart-65b795a8-3515-406e-9e05-6dc47b822803
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771561087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1771561087
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3358321338
Short name T42
Test name
Test status
Simulation time 532702371 ps
CPU time 1.52 seconds
Started Jul 02 08:08:48 AM PDT 24
Finished Jul 02 08:08:52 AM PDT 24
Peak memory 198728 kb
Host smart-e2f15deb-1d72-42b9-bebb-793ed158b0eb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358321338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3358321338
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2591323622
Short name T82
Test name
Test status
Simulation time 160853510 ps
CPU time 0.83 seconds
Started Jul 02 08:08:23 AM PDT 24
Finished Jul 02 08:08:30 AM PDT 24
Peak memory 196628 kb
Host smart-afb265ed-a043-4497-a9c8-f706ab8e274b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591323622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.2591323622
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.369655637
Short name T79
Test name
Test status
Simulation time 514902070 ps
CPU time 3.11 seconds
Started Jul 02 08:08:22 AM PDT 24
Finished Jul 02 08:08:31 AM PDT 24
Peak memory 198728 kb
Host smart-660604c8-945c-4e66-a2e3-cfb1fa372b1c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369655637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.369655637
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2340639690
Short name T754
Test name
Test status
Simulation time 15545693 ps
CPU time 0.6 seconds
Started Jul 02 08:08:23 AM PDT 24
Finished Jul 02 08:08:30 AM PDT 24
Peak memory 194960 kb
Host smart-862ae6f8-235c-4330-9d32-2a86a7fe9b34
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340639690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.2340639690
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.4262079580
Short name T781
Test name
Test status
Simulation time 61051740 ps
CPU time 0.96 seconds
Started Jul 02 08:08:25 AM PDT 24
Finished Jul 02 08:08:32 AM PDT 24
Peak memory 198536 kb
Host smart-f6ad9c34-b6ec-4b47-8936-273469ad3d9d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262079580 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.4262079580
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1959037740
Short name T743
Test name
Test status
Simulation time 37883333 ps
CPU time 0.57 seconds
Started Jul 02 08:08:27 AM PDT 24
Finished Jul 02 08:08:34 AM PDT 24
Peak memory 195960 kb
Host smart-ce32f284-12a5-4085-ad3f-0d0511ac43bb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959037740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1959037740
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.3354461637
Short name T724
Test name
Test status
Simulation time 57750640 ps
CPU time 0.6 seconds
Started Jul 02 08:08:24 AM PDT 24
Finished Jul 02 08:08:30 AM PDT 24
Peak memory 194320 kb
Host smart-c4335276-33e4-4803-b91a-fe8a36b67ec1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354461637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.3354461637
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2357792370
Short name T765
Test name
Test status
Simulation time 13515613 ps
CPU time 0.65 seconds
Started Jul 02 08:08:23 AM PDT 24
Finished Jul 02 08:08:29 AM PDT 24
Peak memory 195292 kb
Host smart-ab884a41-0ddb-4735-b8ec-926645969ba0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357792370 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2357792370
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1107072771
Short name T810
Test name
Test status
Simulation time 38777259 ps
CPU time 1.91 seconds
Started Jul 02 08:08:26 AM PDT 24
Finished Jul 02 08:08:33 AM PDT 24
Peak memory 198728 kb
Host smart-ed9ec270-f276-4339-96ad-96924d892b3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107072771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1107072771
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1718805636
Short name T833
Test name
Test status
Simulation time 157334097 ps
CPU time 1.15 seconds
Started Jul 02 08:08:24 AM PDT 24
Finished Jul 02 08:08:31 AM PDT 24
Peak memory 198752 kb
Host smart-8105404d-90aa-458f-b758-00e2a3310fa2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718805636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.1718805636
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.151205336
Short name T757
Test name
Test status
Simulation time 44376639 ps
CPU time 0.61 seconds
Started Jul 02 08:08:46 AM PDT 24
Finished Jul 02 08:08:49 AM PDT 24
Peak memory 194392 kb
Host smart-19967a8d-c853-4229-8970-029bc03fd2f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151205336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.151205336
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.4168778446
Short name T719
Test name
Test status
Simulation time 23414212 ps
CPU time 0.58 seconds
Started Jul 02 08:08:46 AM PDT 24
Finished Jul 02 08:08:49 AM PDT 24
Peak memory 194328 kb
Host smart-9cdb825f-7710-4a0e-8a71-8bb0958fc329
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168778446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.4168778446
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.2550812836
Short name T778
Test name
Test status
Simulation time 12174982 ps
CPU time 0.59 seconds
Started Jul 02 08:08:45 AM PDT 24
Finished Jul 02 08:08:48 AM PDT 24
Peak memory 194344 kb
Host smart-e7e9a1a9-0e73-4cc3-8e50-e8958bc10e5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550812836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.2550812836
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1183723016
Short name T750
Test name
Test status
Simulation time 31833124 ps
CPU time 0.66 seconds
Started Jul 02 08:08:48 AM PDT 24
Finished Jul 02 08:08:51 AM PDT 24
Peak memory 195096 kb
Host smart-58316b26-d372-4890-b874-6e229e76dc72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183723016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1183723016
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.3517598672
Short name T721
Test name
Test status
Simulation time 16601856 ps
CPU time 0.59 seconds
Started Jul 02 08:08:44 AM PDT 24
Finished Jul 02 08:08:47 AM PDT 24
Peak memory 194424 kb
Host smart-70f04166-39ae-4aa9-af59-f8b955f3a297
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517598672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.3517598672
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.3854973818
Short name T797
Test name
Test status
Simulation time 21008822 ps
CPU time 0.63 seconds
Started Jul 02 08:08:46 AM PDT 24
Finished Jul 02 08:08:49 AM PDT 24
Peak memory 195008 kb
Host smart-509ae07b-bc51-4f0a-8120-8d20f088e174
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854973818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.3854973818
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.1979840670
Short name T726
Test name
Test status
Simulation time 148320458 ps
CPU time 0.59 seconds
Started Jul 02 08:08:45 AM PDT 24
Finished Jul 02 08:08:48 AM PDT 24
Peak memory 194420 kb
Host smart-d1bc87eb-a9ef-4e12-857d-fb253cb6360d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979840670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.1979840670
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.3504089342
Short name T720
Test name
Test status
Simulation time 11997840 ps
CPU time 0.62 seconds
Started Jul 02 08:08:45 AM PDT 24
Finished Jul 02 08:08:48 AM PDT 24
Peak memory 194328 kb
Host smart-c4cf52b1-d09c-4da7-bfae-0595b3e6a82b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504089342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.3504089342
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.2523423762
Short name T728
Test name
Test status
Simulation time 41730580 ps
CPU time 0.6 seconds
Started Jul 02 08:08:47 AM PDT 24
Finished Jul 02 08:08:51 AM PDT 24
Peak memory 194416 kb
Host smart-8cd1d67b-e4f6-4244-927a-86514a110595
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523423762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2523423762
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.753314465
Short name T770
Test name
Test status
Simulation time 23366289 ps
CPU time 0.59 seconds
Started Jul 02 08:08:45 AM PDT 24
Finished Jul 02 08:08:48 AM PDT 24
Peak memory 194360 kb
Host smart-7a63a597-669c-4cd2-9907-17a796e721e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753314465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.753314465
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.470330721
Short name T84
Test name
Test status
Simulation time 39123096 ps
CPU time 0.88 seconds
Started Jul 02 08:08:23 AM PDT 24
Finished Jul 02 08:08:29 AM PDT 24
Peak memory 196592 kb
Host smart-e8cf65f7-5483-4941-b621-6388ce6ef870
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470330721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.gpio_csr_aliasing.470330721
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1901665397
Short name T729
Test name
Test status
Simulation time 1118770655 ps
CPU time 3.28 seconds
Started Jul 02 08:08:24 AM PDT 24
Finished Jul 02 08:08:33 AM PDT 24
Peak memory 197836 kb
Host smart-b8e8607a-4489-4d2c-b5c3-86e61bdb914d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901665397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1901665397
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1986606127
Short name T793
Test name
Test status
Simulation time 11916442 ps
CPU time 0.64 seconds
Started Jul 02 08:08:22 AM PDT 24
Finished Jul 02 08:08:29 AM PDT 24
Peak memory 195528 kb
Host smart-fc12ddfa-1540-4131-896f-2af540fe2109
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986606127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1986606127
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.932460924
Short name T732
Test name
Test status
Simulation time 15774758 ps
CPU time 0.69 seconds
Started Jul 02 08:08:22 AM PDT 24
Finished Jul 02 08:08:29 AM PDT 24
Peak memory 197732 kb
Host smart-eefd448b-92ae-447a-9914-783b912dbc17
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932460924 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.932460924
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2584287430
Short name T87
Test name
Test status
Simulation time 13678616 ps
CPU time 0.65 seconds
Started Jul 02 08:08:22 AM PDT 24
Finished Jul 02 08:08:29 AM PDT 24
Peak memory 195616 kb
Host smart-235d5d10-c2e5-4bf3-963f-bf5fa1538e2f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584287430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2584287430
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3811316531
Short name T823
Test name
Test status
Simulation time 15907816 ps
CPU time 0.63 seconds
Started Jul 02 08:08:23 AM PDT 24
Finished Jul 02 08:08:29 AM PDT 24
Peak memory 194320 kb
Host smart-a879f31d-15aa-48cb-8c0b-d3dcd4716325
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811316531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3811316531
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3824452681
Short name T794
Test name
Test status
Simulation time 18659012 ps
CPU time 0.82 seconds
Started Jul 02 08:08:22 AM PDT 24
Finished Jul 02 08:08:29 AM PDT 24
Peak memory 197116 kb
Host smart-25d609a6-fcb0-4d04-8f45-207d7bdf21b0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824452681 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3824452681
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3074247153
Short name T783
Test name
Test status
Simulation time 156743156 ps
CPU time 2.73 seconds
Started Jul 02 08:08:24 AM PDT 24
Finished Jul 02 08:08:33 AM PDT 24
Peak memory 198748 kb
Host smart-2140a1b1-5542-4ebc-b22e-c0ebdb4bb6a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074247153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3074247153
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2316319056
Short name T824
Test name
Test status
Simulation time 940562347 ps
CPU time 1.36 seconds
Started Jul 02 08:08:22 AM PDT 24
Finished Jul 02 08:08:30 AM PDT 24
Peak memory 198624 kb
Host smart-2fbd0fb3-fefa-4ec0-9a94-e3944fa0b1e5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316319056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.2316319056
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.3618632819
Short name T730
Test name
Test status
Simulation time 16498142 ps
CPU time 0.63 seconds
Started Jul 02 08:08:47 AM PDT 24
Finished Jul 02 08:08:51 AM PDT 24
Peak memory 194372 kb
Host smart-dd627ba3-a389-457c-b2da-575a9cb70a7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618632819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.3618632819
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.3820107139
Short name T756
Test name
Test status
Simulation time 22874982 ps
CPU time 0.61 seconds
Started Jul 02 08:08:45 AM PDT 24
Finished Jul 02 08:08:49 AM PDT 24
Peak memory 195008 kb
Host smart-4e8aef97-ed83-4711-be18-0071f3bf6896
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820107139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.3820107139
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.2216158539
Short name T723
Test name
Test status
Simulation time 23552781 ps
CPU time 0.61 seconds
Started Jul 02 08:08:51 AM PDT 24
Finished Jul 02 08:08:56 AM PDT 24
Peak memory 194424 kb
Host smart-f98ef4ae-ca92-4191-899d-ca8d6b190934
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216158539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.2216158539
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.4157327788
Short name T731
Test name
Test status
Simulation time 15172212 ps
CPU time 0.64 seconds
Started Jul 02 08:08:52 AM PDT 24
Finished Jul 02 08:08:58 AM PDT 24
Peak memory 194352 kb
Host smart-730927a9-16aa-4a35-a1c0-b7f96cd043b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157327788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.4157327788
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.208499118
Short name T802
Test name
Test status
Simulation time 26484851 ps
CPU time 0.62 seconds
Started Jul 02 08:08:51 AM PDT 24
Finished Jul 02 08:08:56 AM PDT 24
Peak memory 194344 kb
Host smart-1fe374ad-9627-4884-ad77-2dbf16943b81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208499118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.208499118
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.459409620
Short name T716
Test name
Test status
Simulation time 24584660 ps
CPU time 0.68 seconds
Started Jul 02 08:08:53 AM PDT 24
Finished Jul 02 08:08:58 AM PDT 24
Peak memory 194432 kb
Host smart-1e6b926a-7f08-4cce-b068-e74da0aff0a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459409620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.459409620
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.1191573378
Short name T837
Test name
Test status
Simulation time 44197679 ps
CPU time 0.56 seconds
Started Jul 02 08:08:49 AM PDT 24
Finished Jul 02 08:08:53 AM PDT 24
Peak memory 195024 kb
Host smart-4baec0fe-001c-4f8d-a7ed-86b94ca319c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191573378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.1191573378
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3922810652
Short name T718
Test name
Test status
Simulation time 15253682 ps
CPU time 0.62 seconds
Started Jul 02 08:08:52 AM PDT 24
Finished Jul 02 08:08:58 AM PDT 24
Peak memory 194404 kb
Host smart-1af85654-bce3-48ba-a287-38f882c84301
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922810652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3922810652
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1441808808
Short name T785
Test name
Test status
Simulation time 19371156 ps
CPU time 0.66 seconds
Started Jul 02 08:08:52 AM PDT 24
Finished Jul 02 08:08:58 AM PDT 24
Peak memory 195088 kb
Host smart-10ab9b67-618f-4d6d-988e-2ee5d6c7c1f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441808808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1441808808
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.3220609131
Short name T741
Test name
Test status
Simulation time 34532067 ps
CPU time 0.64 seconds
Started Jul 02 08:08:52 AM PDT 24
Finished Jul 02 08:08:58 AM PDT 24
Peak memory 194412 kb
Host smart-63b415c6-ab6e-4d0c-9ad6-0caaed826efd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220609131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3220609131
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2613152440
Short name T85
Test name
Test status
Simulation time 25797459 ps
CPU time 0.77 seconds
Started Jul 02 08:08:27 AM PDT 24
Finished Jul 02 08:08:33 AM PDT 24
Peak memory 196512 kb
Host smart-7e900e27-efad-4297-b31d-8c0c37cdc530
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613152440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2613152440
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1429286247
Short name T740
Test name
Test status
Simulation time 1004919266 ps
CPU time 2.38 seconds
Started Jul 02 08:08:29 AM PDT 24
Finished Jul 02 08:08:36 AM PDT 24
Peak memory 197856 kb
Host smart-5d87dd7b-dd74-403f-8c97-e6caec5dd585
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429286247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1429286247
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.296566199
Short name T758
Test name
Test status
Simulation time 25962208 ps
CPU time 0.6 seconds
Started Jul 02 08:08:24 AM PDT 24
Finished Jul 02 08:08:31 AM PDT 24
Peak memory 195252 kb
Host smart-ad0ef102-eb0a-4a9a-b5ff-e15d7e246993
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296566199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.296566199
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2106544945
Short name T838
Test name
Test status
Simulation time 26938866 ps
CPU time 1.26 seconds
Started Jul 02 08:08:24 AM PDT 24
Finished Jul 02 08:08:31 AM PDT 24
Peak memory 198692 kb
Host smart-2d5aebff-91bb-4bf3-a1fc-2ff28e0fe5b9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106544945 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2106544945
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2747042789
Short name T83
Test name
Test status
Simulation time 43751637 ps
CPU time 0.56 seconds
Started Jul 02 08:08:23 AM PDT 24
Finished Jul 02 08:08:30 AM PDT 24
Peak memory 194636 kb
Host smart-5d92d12c-a74e-4d89-b4a1-f6cff518bd09
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747042789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2747042789
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.1470611479
Short name T768
Test name
Test status
Simulation time 16415843 ps
CPU time 0.66 seconds
Started Jul 02 08:08:22 AM PDT 24
Finished Jul 02 08:08:29 AM PDT 24
Peak memory 195032 kb
Host smart-7ed0253a-b46a-43c6-9d6b-f26c433120f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470611479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.1470611479
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2713444857
Short name T94
Test name
Test status
Simulation time 149463077 ps
CPU time 0.85 seconds
Started Jul 02 08:08:23 AM PDT 24
Finished Jul 02 08:08:30 AM PDT 24
Peak memory 196884 kb
Host smart-654bd7e4-9282-4524-bb23-4b9940ae738d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713444857 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2713444857
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1420962395
Short name T738
Test name
Test status
Simulation time 86269213 ps
CPU time 1.84 seconds
Started Jul 02 08:08:27 AM PDT 24
Finished Jul 02 08:08:35 AM PDT 24
Peak memory 198744 kb
Host smart-bf183619-a9cd-4f8a-804f-e69139e01d2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420962395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1420962395
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3312318893
Short name T829
Test name
Test status
Simulation time 407069621 ps
CPU time 1.42 seconds
Started Jul 02 08:08:28 AM PDT 24
Finished Jul 02 08:08:35 AM PDT 24
Peak memory 198780 kb
Host smart-c04ef509-7862-4bb9-b8e5-26ec6840bd12
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312318893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3312318893
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.34981311
Short name T812
Test name
Test status
Simulation time 17106395 ps
CPU time 0.63 seconds
Started Jul 02 08:08:51 AM PDT 24
Finished Jul 02 08:08:57 AM PDT 24
Peak memory 195040 kb
Host smart-8937fc61-6e17-4ccd-8f81-d557f0acf848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34981311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.34981311
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2393682401
Short name T834
Test name
Test status
Simulation time 13106999 ps
CPU time 0.6 seconds
Started Jul 02 08:08:51 AM PDT 24
Finished Jul 02 08:08:56 AM PDT 24
Peak memory 195168 kb
Host smart-c4ac2cf6-fd72-4241-b8bf-53d4d6b9a1a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393682401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2393682401
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.1385052900
Short name T827
Test name
Test status
Simulation time 15253289 ps
CPU time 0.59 seconds
Started Jul 02 08:08:53 AM PDT 24
Finished Jul 02 08:08:58 AM PDT 24
Peak memory 195036 kb
Host smart-2db13431-43ca-439b-8634-d97de848061b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385052900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1385052900
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3756665224
Short name T752
Test name
Test status
Simulation time 15382063 ps
CPU time 0.6 seconds
Started Jul 02 08:08:49 AM PDT 24
Finished Jul 02 08:08:53 AM PDT 24
Peak memory 195072 kb
Host smart-f04f11ec-7f18-4737-95d2-d900a3d3bdda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756665224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3756665224
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.2198236697
Short name T745
Test name
Test status
Simulation time 73491320 ps
CPU time 0.55 seconds
Started Jul 02 08:08:52 AM PDT 24
Finished Jul 02 08:08:57 AM PDT 24
Peak memory 194368 kb
Host smart-9ef19e4b-e476-45f7-a30d-97c4e8260cbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198236697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.2198236697
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.107848893
Short name T767
Test name
Test status
Simulation time 42752077 ps
CPU time 0.57 seconds
Started Jul 02 08:08:48 AM PDT 24
Finished Jul 02 08:08:52 AM PDT 24
Peak memory 194336 kb
Host smart-1e0552e2-17fa-48b3-8a63-ea5db605abe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107848893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.107848893
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2600686258
Short name T753
Test name
Test status
Simulation time 80231503 ps
CPU time 0.59 seconds
Started Jul 02 08:08:53 AM PDT 24
Finished Jul 02 08:08:59 AM PDT 24
Peak memory 194328 kb
Host smart-896b9c25-1186-4431-b042-f4c079b6b412
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600686258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2600686258
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.954612194
Short name T734
Test name
Test status
Simulation time 14281098 ps
CPU time 0.58 seconds
Started Jul 02 08:08:51 AM PDT 24
Finished Jul 02 08:08:55 AM PDT 24
Peak memory 194400 kb
Host smart-a3fe676b-6596-4064-b60e-3c81edf944aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954612194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.954612194
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.615363467
Short name T735
Test name
Test status
Simulation time 55912028 ps
CPU time 0.68 seconds
Started Jul 02 08:08:50 AM PDT 24
Finished Jul 02 08:08:55 AM PDT 24
Peak memory 194444 kb
Host smart-94243544-eaa4-4fe3-91e2-34e6542f054a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615363467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.615363467
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.3476742449
Short name T805
Test name
Test status
Simulation time 42989040 ps
CPU time 0.62 seconds
Started Jul 02 08:08:50 AM PDT 24
Finished Jul 02 08:08:55 AM PDT 24
Peak memory 194472 kb
Host smart-90a99290-6c02-401b-b344-e04b03b515dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476742449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.3476742449
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3169804558
Short name T774
Test name
Test status
Simulation time 124635555 ps
CPU time 0.96 seconds
Started Jul 02 08:08:31 AM PDT 24
Finished Jul 02 08:08:36 AM PDT 24
Peak memory 198540 kb
Host smart-9608ac6f-cde8-41c4-b8b4-3fef6c795b99
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169804558 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3169804558
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.4137170537
Short name T76
Test name
Test status
Simulation time 44123571 ps
CPU time 0.62 seconds
Started Jul 02 08:08:29 AM PDT 24
Finished Jul 02 08:08:35 AM PDT 24
Peak memory 195556 kb
Host smart-060ab1cc-6efc-4014-8d38-f459ae7e0d43
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137170537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.4137170537
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3175862878
Short name T763
Test name
Test status
Simulation time 18740793 ps
CPU time 0.64 seconds
Started Jul 02 08:08:29 AM PDT 24
Finished Jul 02 08:08:35 AM PDT 24
Peak memory 194372 kb
Host smart-677aa89f-6784-4fef-b19f-fd0761a3c8ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175862878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3175862878
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1924335713
Short name T72
Test name
Test status
Simulation time 58470707 ps
CPU time 0.7 seconds
Started Jul 02 08:08:29 AM PDT 24
Finished Jul 02 08:08:35 AM PDT 24
Peak memory 195420 kb
Host smart-1e1487aa-4818-4659-9e8a-5a017bbc89c9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924335713 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.1924335713
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1054669827
Short name T792
Test name
Test status
Simulation time 63104377 ps
CPU time 1.35 seconds
Started Jul 02 08:08:29 AM PDT 24
Finished Jul 02 08:08:36 AM PDT 24
Peak memory 198756 kb
Host smart-21cbe66e-db78-463c-90b2-783fa5779a4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054669827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.1054669827
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2137608363
Short name T786
Test name
Test status
Simulation time 107734865 ps
CPU time 0.85 seconds
Started Jul 02 08:08:28 AM PDT 24
Finished Jul 02 08:08:34 AM PDT 24
Peak memory 198452 kb
Host smart-d4f6ea42-7e24-41c6-86a6-7e9539de599b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137608363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.2137608363
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1218639523
Short name T739
Test name
Test status
Simulation time 160754689 ps
CPU time 0.83 seconds
Started Jul 02 08:08:30 AM PDT 24
Finished Jul 02 08:08:35 AM PDT 24
Peak memory 198568 kb
Host smart-4e1f45a9-52e5-4a58-a79c-4a29b4b3d725
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218639523 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1218639523
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3967108697
Short name T788
Test name
Test status
Simulation time 13150612 ps
CPU time 0.63 seconds
Started Jul 02 08:08:31 AM PDT 24
Finished Jul 02 08:08:36 AM PDT 24
Peak memory 195260 kb
Host smart-182dcbc7-1323-4b20-a7b4-4f29483c7383
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967108697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3967108697
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2542309772
Short name T742
Test name
Test status
Simulation time 16237718 ps
CPU time 0.58 seconds
Started Jul 02 08:08:29 AM PDT 24
Finished Jul 02 08:08:34 AM PDT 24
Peak memory 194344 kb
Host smart-35a36f8e-62c9-4774-8d1c-537eb32a56ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542309772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2542309772
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3610054551
Short name T808
Test name
Test status
Simulation time 14891916 ps
CPU time 0.65 seconds
Started Jul 02 08:08:28 AM PDT 24
Finished Jul 02 08:08:34 AM PDT 24
Peak memory 195332 kb
Host smart-e7984f07-fea3-413b-b19d-e0d343ccf869
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610054551 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.3610054551
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.775196379
Short name T830
Test name
Test status
Simulation time 115498458 ps
CPU time 2.14 seconds
Started Jul 02 08:08:29 AM PDT 24
Finished Jul 02 08:08:36 AM PDT 24
Peak memory 198792 kb
Host smart-ca2e97fc-8674-4367-ae95-b97f79d7f00a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775196379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.775196379
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.844157578
Short name T31
Test name
Test status
Simulation time 121282892 ps
CPU time 1.38 seconds
Started Jul 02 08:08:30 AM PDT 24
Finished Jul 02 08:08:36 AM PDT 24
Peak memory 198756 kb
Host smart-d42720cf-005d-4ff5-a8a2-3df3274c4f6e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844157578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.844157578
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3707654724
Short name T828
Test name
Test status
Simulation time 54646775 ps
CPU time 0.88 seconds
Started Jul 02 08:08:29 AM PDT 24
Finished Jul 02 08:08:35 AM PDT 24
Peak memory 198632 kb
Host smart-a60eba10-52a4-4639-a60c-8fb5139a59dd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707654724 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.3707654724
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.146916361
Short name T81
Test name
Test status
Simulation time 39323427 ps
CPU time 0.6 seconds
Started Jul 02 08:08:30 AM PDT 24
Finished Jul 02 08:08:35 AM PDT 24
Peak memory 196120 kb
Host smart-356bca54-5ff2-4b51-8009-d3ee3e76d756
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146916361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_
csr_rw.146916361
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.1668261220
Short name T759
Test name
Test status
Simulation time 43122240 ps
CPU time 0.61 seconds
Started Jul 02 08:08:28 AM PDT 24
Finished Jul 02 08:08:34 AM PDT 24
Peak memory 194376 kb
Host smart-fceae16f-9f50-4f19-bef4-753acddc4fab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668261220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1668261220
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3417199592
Short name T787
Test name
Test status
Simulation time 35572793 ps
CPU time 0.6 seconds
Started Jul 02 08:08:29 AM PDT 24
Finished Jul 02 08:08:35 AM PDT 24
Peak memory 195092 kb
Host smart-3499eb50-c106-49ac-b9f6-9650fe7a7e25
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417199592 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.3417199592
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3490987376
Short name T775
Test name
Test status
Simulation time 185911066 ps
CPU time 2.19 seconds
Started Jul 02 08:08:30 AM PDT 24
Finished Jul 02 08:08:37 AM PDT 24
Peak memory 198636 kb
Host smart-bf891518-af93-4308-8397-11b49f96b757
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490987376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3490987376
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1394498456
Short name T819
Test name
Test status
Simulation time 279127561 ps
CPU time 1.54 seconds
Started Jul 02 08:08:29 AM PDT 24
Finished Jul 02 08:08:36 AM PDT 24
Peak memory 198756 kb
Host smart-59faf12b-5fcc-42b1-9c84-07188aafe5e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394498456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1394498456
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3782352168
Short name T816
Test name
Test status
Simulation time 111020917 ps
CPU time 0.95 seconds
Started Jul 02 08:08:29 AM PDT 24
Finished Jul 02 08:08:35 AM PDT 24
Peak memory 198580 kb
Host smart-84a60ade-320d-4698-af0c-02721b6be04e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782352168 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3782352168
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2304193402
Short name T71
Test name
Test status
Simulation time 21715938 ps
CPU time 0.63 seconds
Started Jul 02 08:08:29 AM PDT 24
Finished Jul 02 08:08:35 AM PDT 24
Peak memory 195960 kb
Host smart-f7357f5c-e8a1-41ae-884c-40a1c09bc9e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304193402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2304193402
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.2092554688
Short name T717
Test name
Test status
Simulation time 32934558 ps
CPU time 0.64 seconds
Started Jul 02 08:08:41 AM PDT 24
Finished Jul 02 08:08:45 AM PDT 24
Peak memory 194132 kb
Host smart-3fbc10af-7f0b-45c3-811e-a18efce49171
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092554688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.2092554688
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.4222710334
Short name T761
Test name
Test status
Simulation time 64977827 ps
CPU time 0.65 seconds
Started Jul 02 08:08:30 AM PDT 24
Finished Jul 02 08:08:35 AM PDT 24
Peak memory 196388 kb
Host smart-4ac94cdd-5a9d-42ce-aed0-b45a2e3395e9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222710334 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.4222710334
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2296841294
Short name T769
Test name
Test status
Simulation time 1022732310 ps
CPU time 1.72 seconds
Started Jul 02 08:08:35 AM PDT 24
Finished Jul 02 08:08:40 AM PDT 24
Peak memory 198776 kb
Host smart-910dacc5-dc3d-4a96-ac64-87e5032650fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296841294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2296841294
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.138194073
Short name T791
Test name
Test status
Simulation time 27045846 ps
CPU time 0.83 seconds
Started Jul 02 08:08:35 AM PDT 24
Finished Jul 02 08:08:39 AM PDT 24
Peak memory 198604 kb
Host smart-540a1ece-2246-4211-893b-1437808bef97
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138194073 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.138194073
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3144421370
Short name T95
Test name
Test status
Simulation time 65363576 ps
CPU time 0.64 seconds
Started Jul 02 08:08:35 AM PDT 24
Finished Jul 02 08:08:38 AM PDT 24
Peak memory 195668 kb
Host smart-79fb3965-6017-4ae6-bd98-11de4ecb332c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144421370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3144421370
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2156544621
Short name T798
Test name
Test status
Simulation time 25853342 ps
CPU time 0.58 seconds
Started Jul 02 08:08:36 AM PDT 24
Finished Jul 02 08:08:39 AM PDT 24
Peak memory 194332 kb
Host smart-3de7297f-5644-45da-878a-81e4197add9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156544621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2156544621
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.1208836214
Short name T78
Test name
Test status
Simulation time 15403905 ps
CPU time 0.73 seconds
Started Jul 02 08:08:36 AM PDT 24
Finished Jul 02 08:08:40 AM PDT 24
Peak memory 196532 kb
Host smart-620e0f75-d070-469c-98c3-32db81b90aa2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208836214 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.1208836214
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3636911772
Short name T780
Test name
Test status
Simulation time 136282247 ps
CPU time 1.89 seconds
Started Jul 02 08:08:37 AM PDT 24
Finished Jul 02 08:08:42 AM PDT 24
Peak memory 198668 kb
Host smart-79445cb7-a9d5-43c3-b127-117ded8b5890
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636911772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.3636911772
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.322121234
Short name T32
Test name
Test status
Simulation time 286197390 ps
CPU time 0.83 seconds
Started Jul 02 08:08:38 AM PDT 24
Finished Jul 02 08:08:42 AM PDT 24
Peak memory 197744 kb
Host smart-a95c2791-b048-4711-a02b-728677735933
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322121234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.gpio_tl_intg_err.322121234
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1908227303
Short name T626
Test name
Test status
Simulation time 36895991 ps
CPU time 0.56 seconds
Started Jul 02 07:33:55 AM PDT 24
Finished Jul 02 07:33:56 AM PDT 24
Peak memory 194896 kb
Host smart-4a2bf2f3-52e7-4c63-85de-53f5168c0a4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908227303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1908227303
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.1665214054
Short name T124
Test name
Test status
Simulation time 99337988 ps
CPU time 0.64 seconds
Started Jul 02 07:36:57 AM PDT 24
Finished Jul 02 07:36:59 AM PDT 24
Peak memory 193816 kb
Host smart-77743c25-91c1-4a79-a2c6-01bccbf85a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665214054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.1665214054
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2012998366
Short name T394
Test name
Test status
Simulation time 2680998934 ps
CPU time 20.89 seconds
Started Jul 02 07:36:56 AM PDT 24
Finished Jul 02 07:37:19 AM PDT 24
Peak memory 196304 kb
Host smart-2333a02a-dd48-425f-b875-cdf9b73b5ae3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012998366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2012998366
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.3016096502
Short name T598
Test name
Test status
Simulation time 45153715 ps
CPU time 0.83 seconds
Started Jul 02 07:34:53 AM PDT 24
Finished Jul 02 07:34:54 AM PDT 24
Peak memory 195628 kb
Host smart-23d1e752-4ebe-4480-8bc9-bba41086efbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016096502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3016096502
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.3411284698
Short name T252
Test name
Test status
Simulation time 37926333 ps
CPU time 0.88 seconds
Started Jul 02 07:37:34 AM PDT 24
Finished Jul 02 07:37:47 AM PDT 24
Peak memory 196208 kb
Host smart-5fb20f84-5c51-4d87-a8cd-f267e9b1513f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411284698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.3411284698
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1261581027
Short name T323
Test name
Test status
Simulation time 94117573 ps
CPU time 3.64 seconds
Started Jul 02 07:35:18 AM PDT 24
Finished Jul 02 07:35:22 AM PDT 24
Peak memory 198896 kb
Host smart-4f2d1414-bda6-4ea0-af29-a8fac65c99f3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261581027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1261581027
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.3843162648
Short name T279
Test name
Test status
Simulation time 97378598 ps
CPU time 2.8 seconds
Started Jul 02 07:37:19 AM PDT 24
Finished Jul 02 07:37:29 AM PDT 24
Peak memory 195940 kb
Host smart-e650d3e8-9bf4-44ed-9ae4-9925e3bd296b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843162648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
3843162648
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.1990013996
Short name T577
Test name
Test status
Simulation time 27052398 ps
CPU time 1.07 seconds
Started Jul 02 07:33:21 AM PDT 24
Finished Jul 02 07:33:23 AM PDT 24
Peak memory 197568 kb
Host smart-0e1787d7-4a89-4a93-b102-f4bafa903e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990013996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.1990013996
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.4277601449
Short name T404
Test name
Test status
Simulation time 28463110 ps
CPU time 0.61 seconds
Started Jul 02 07:37:35 AM PDT 24
Finished Jul 02 07:37:47 AM PDT 24
Peak memory 195392 kb
Host smart-751481ac-d194-46c4-bfa3-720001d1ade4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277601449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.4277601449
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.483480203
Short name T434
Test name
Test status
Simulation time 64125171 ps
CPU time 1.2 seconds
Started Jul 02 07:37:19 AM PDT 24
Finished Jul 02 07:37:27 AM PDT 24
Peak memory 197900 kb
Host smart-59df3395-0e4c-4b89-9187-6e3d7f3ba6d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483480203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand
om_long_reg_writes_reg_reads.483480203
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.1917124364
Short name T507
Test name
Test status
Simulation time 25921092 ps
CPU time 0.89 seconds
Started Jul 02 07:34:31 AM PDT 24
Finished Jul 02 07:34:33 AM PDT 24
Peak memory 194160 kb
Host smart-1efb7978-83fc-461c-9aa6-063ee8eb7c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917124364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1917124364
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.313340531
Short name T688
Test name
Test status
Simulation time 27314495 ps
CPU time 0.79 seconds
Started Jul 02 07:34:48 AM PDT 24
Finished Jul 02 07:34:50 AM PDT 24
Peak memory 195680 kb
Host smart-3993eeb3-8bb4-43b5-b2b0-3f5f28f764b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313340531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.313340531
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.730782963
Short name T349
Test name
Test status
Simulation time 4509131976 ps
CPU time 103.37 seconds
Started Jul 02 07:36:15 AM PDT 24
Finished Jul 02 07:37:59 AM PDT 24
Peak memory 197624 kb
Host smart-be7fb4f9-48a8-4b73-847b-4ab2d043245b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730782963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.730782963
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2312257594
Short name T621
Test name
Test status
Simulation time 44471633 ps
CPU time 0.57 seconds
Started Jul 02 07:37:11 AM PDT 24
Finished Jul 02 07:37:15 AM PDT 24
Peak memory 194748 kb
Host smart-cb181dec-1005-4fd9-86ad-431224510e6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312257594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2312257594
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3864082248
Short name T231
Test name
Test status
Simulation time 81725325 ps
CPU time 0.84 seconds
Started Jul 02 07:36:25 AM PDT 24
Finished Jul 02 07:36:27 AM PDT 24
Peak memory 197420 kb
Host smart-7e16b3fe-9c27-4910-ab9e-4210fa2b8042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864082248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3864082248
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3735683733
Short name T171
Test name
Test status
Simulation time 1316146437 ps
CPU time 19.8 seconds
Started Jul 02 07:37:17 AM PDT 24
Finished Jul 02 07:37:43 AM PDT 24
Peak memory 198320 kb
Host smart-6fad4253-52f4-4746-919d-055149e7ed9d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735683733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3735683733
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.3069417041
Short name T23
Test name
Test status
Simulation time 52770541 ps
CPU time 0.75 seconds
Started Jul 02 07:36:21 AM PDT 24
Finished Jul 02 07:36:23 AM PDT 24
Peak memory 196608 kb
Host smart-a96ad151-0629-4daf-a7b1-fe14f12576cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069417041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.3069417041
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.4172978598
Short name T125
Test name
Test status
Simulation time 53293872 ps
CPU time 1.02 seconds
Started Jul 02 07:36:28 AM PDT 24
Finished Jul 02 07:36:32 AM PDT 24
Peak memory 196240 kb
Host smart-131febd1-83a2-48d2-b5eb-4208f66d6a2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172978598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.4172978598
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.3659186273
Short name T374
Test name
Test status
Simulation time 55196104 ps
CPU time 1.21 seconds
Started Jul 02 07:37:18 AM PDT 24
Finished Jul 02 07:37:24 AM PDT 24
Peak memory 197024 kb
Host smart-1984737b-8e89-4b86-9bc6-aba7157afe27
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659186273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.3659186273
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.3414458001
Short name T445
Test name
Test status
Simulation time 154192824 ps
CPU time 2.72 seconds
Started Jul 02 07:32:21 AM PDT 24
Finished Jul 02 07:32:25 AM PDT 24
Peak memory 196312 kb
Host smart-e17f9467-250b-4665-b0dc-a33f4d84609b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414458001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
3414458001
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.1743229120
Short name T136
Test name
Test status
Simulation time 38715459 ps
CPU time 0.9 seconds
Started Jul 02 07:32:19 AM PDT 24
Finished Jul 02 07:32:20 AM PDT 24
Peak memory 197292 kb
Host smart-7b219d18-bfc7-435f-9396-8c546c5e1e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743229120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.1743229120
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2336280311
Short name T613
Test name
Test status
Simulation time 147465876 ps
CPU time 0.86 seconds
Started Jul 02 07:36:23 AM PDT 24
Finished Jul 02 07:36:26 AM PDT 24
Peak memory 196732 kb
Host smart-506b2ae5-38d0-4643-a971-379e8abe9c6d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336280311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2336280311
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2831798332
Short name T4
Test name
Test status
Simulation time 333657398 ps
CPU time 4.31 seconds
Started Jul 02 07:37:18 AM PDT 24
Finished Jul 02 07:37:27 AM PDT 24
Peak memory 198308 kb
Host smart-d4a7e8bb-fb39-4416-b3d1-9329d83780ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831798332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2831798332
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.4111001907
Short name T45
Test name
Test status
Simulation time 69209026 ps
CPU time 0.85 seconds
Started Jul 02 07:36:20 AM PDT 24
Finished Jul 02 07:36:23 AM PDT 24
Peak memory 213912 kb
Host smart-2232cff7-940d-42a5-9619-9bc06eaa1e22
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111001907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.4111001907
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.3591335870
Short name T498
Test name
Test status
Simulation time 1301235754 ps
CPU time 1.34 seconds
Started Jul 02 07:36:48 AM PDT 24
Finished Jul 02 07:36:55 AM PDT 24
Peak memory 194936 kb
Host smart-72308ae6-2cb1-4087-b0dd-6bed9ff574b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591335870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3591335870
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1071778868
Short name T145
Test name
Test status
Simulation time 271001326 ps
CPU time 1.19 seconds
Started Jul 02 07:32:21 AM PDT 24
Finished Jul 02 07:32:23 AM PDT 24
Peak memory 197660 kb
Host smart-ed41a62e-da92-4f42-a3d6-d7c8d4e26348
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071778868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1071778868
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.881938184
Short name T421
Test name
Test status
Simulation time 49636057584 ps
CPU time 95.11 seconds
Started Jul 02 07:34:57 AM PDT 24
Finished Jul 02 07:36:33 AM PDT 24
Peak memory 198588 kb
Host smart-b209af14-41a7-4ebe-a597-879ae3ec5c2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881938184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.881938184
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.978468031
Short name T408
Test name
Test status
Simulation time 31062637 ps
CPU time 0.61 seconds
Started Jul 02 07:38:42 AM PDT 24
Finished Jul 02 07:38:58 AM PDT 24
Peak memory 192876 kb
Host smart-88e7c8b2-6892-4808-8f74-962d9790080f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978468031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.978468031
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2054526736
Short name T652
Test name
Test status
Simulation time 22223690 ps
CPU time 0.74 seconds
Started Jul 02 07:37:30 AM PDT 24
Finished Jul 02 07:37:41 AM PDT 24
Peak memory 196192 kb
Host smart-fbc876ed-e537-4981-a822-b5824fd84a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054526736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2054526736
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.797757974
Short name T458
Test name
Test status
Simulation time 1545177126 ps
CPU time 14.73 seconds
Started Jul 02 07:37:29 AM PDT 24
Finished Jul 02 07:37:53 AM PDT 24
Peak memory 198544 kb
Host smart-d40a3366-f4ef-4da9-9ff0-3caf34b53b9d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797757974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stres
s.797757974
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.3308539394
Short name T307
Test name
Test status
Simulation time 119201946 ps
CPU time 0.68 seconds
Started Jul 02 07:37:48 AM PDT 24
Finished Jul 02 07:37:59 AM PDT 24
Peak memory 195232 kb
Host smart-7b0777da-6c3c-444b-867c-d7faa679897e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308539394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3308539394
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2661145289
Short name T451
Test name
Test status
Simulation time 88321750 ps
CPU time 1.08 seconds
Started Jul 02 07:37:33 AM PDT 24
Finished Jul 02 07:37:44 AM PDT 24
Peak memory 196380 kb
Host smart-59c2b65d-50f6-4644-82c7-dc4554afe8eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661145289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2661145289
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2175416311
Short name T315
Test name
Test status
Simulation time 138070162 ps
CPU time 2.53 seconds
Started Jul 02 07:37:30 AM PDT 24
Finished Jul 02 07:37:43 AM PDT 24
Peak memory 198516 kb
Host smart-4495463e-a6e8-4961-8356-742168f3861e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175416311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2175416311
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2394736237
Short name T585
Test name
Test status
Simulation time 16708364 ps
CPU time 0.69 seconds
Started Jul 02 07:37:46 AM PDT 24
Finished Jul 02 07:37:57 AM PDT 24
Peak memory 195760 kb
Host smart-04346407-e873-4124-bb8f-ba16716a6d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394736237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2394736237
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.4003483225
Short name T382
Test name
Test status
Simulation time 56529880 ps
CPU time 0.76 seconds
Started Jul 02 07:37:32 AM PDT 24
Finished Jul 02 07:37:44 AM PDT 24
Peak memory 196648 kb
Host smart-0567274b-e584-4c1a-9124-f8f7fe79c167
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003483225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.4003483225
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.4067585460
Short name T662
Test name
Test status
Simulation time 567040908 ps
CPU time 4.76 seconds
Started Jul 02 07:37:33 AM PDT 24
Finished Jul 02 07:37:48 AM PDT 24
Peak memory 198560 kb
Host smart-a4424147-80f2-4b39-b48f-d89429bfe9f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067585460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.4067585460
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.2400894910
Short name T588
Test name
Test status
Simulation time 48389653 ps
CPU time 1.31 seconds
Started Jul 02 07:37:44 AM PDT 24
Finished Jul 02 07:37:56 AM PDT 24
Peak memory 196208 kb
Host smart-c94c1c8d-dd96-4c09-8c45-99c6cbcda2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400894910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.2400894910
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1289816598
Short name T210
Test name
Test status
Simulation time 44163538 ps
CPU time 1.15 seconds
Started Jul 02 07:37:50 AM PDT 24
Finished Jul 02 07:38:01 AM PDT 24
Peak memory 196716 kb
Host smart-a6271821-f609-4b3c-bab3-13664d12c7a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289816598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1289816598
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1390626576
Short name T1
Test name
Test status
Simulation time 51360135153 ps
CPU time 128.78 seconds
Started Jul 02 07:37:24 AM PDT 24
Finished Jul 02 07:39:41 AM PDT 24
Peak memory 198592 kb
Host smart-91ddc152-c3a2-494a-b35b-2017246e724e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390626576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1390626576
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.2740326331
Short name T277
Test name
Test status
Simulation time 16230110 ps
CPU time 0.55 seconds
Started Jul 02 07:37:33 AM PDT 24
Finished Jul 02 07:37:50 AM PDT 24
Peak memory 195348 kb
Host smart-ef682f03-05a3-4ea3-844c-69249d18a7bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740326331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.2740326331
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.535193278
Short name T705
Test name
Test status
Simulation time 21168164 ps
CPU time 0.66 seconds
Started Jul 02 07:37:32 AM PDT 24
Finished Jul 02 07:37:44 AM PDT 24
Peak memory 194656 kb
Host smart-342c5b7c-eb59-4501-aaf9-cf90e22df187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535193278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.535193278
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.3445662621
Short name T218
Test name
Test status
Simulation time 3791529542 ps
CPU time 25.51 seconds
Started Jul 02 07:37:34 AM PDT 24
Finished Jul 02 07:38:11 AM PDT 24
Peak memory 197008 kb
Host smart-4591bd5e-344b-4fee-beac-66c4da2069f0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445662621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.3445662621
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.1120527787
Short name T192
Test name
Test status
Simulation time 62071558 ps
CPU time 0.83 seconds
Started Jul 02 07:38:42 AM PDT 24
Finished Jul 02 07:38:58 AM PDT 24
Peak memory 195852 kb
Host smart-c58fe7b3-0d9a-4dbe-b666-b7ff0152f24e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120527787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1120527787
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.1675243800
Short name T163
Test name
Test status
Simulation time 317438636 ps
CPU time 1.02 seconds
Started Jul 02 07:38:42 AM PDT 24
Finished Jul 02 07:38:58 AM PDT 24
Peak memory 195560 kb
Host smart-f08d7413-b31f-48af-8211-60b7e27d5893
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675243800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.1675243800
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3865736809
Short name T234
Test name
Test status
Simulation time 169161125 ps
CPU time 3.12 seconds
Started Jul 02 07:37:53 AM PDT 24
Finished Jul 02 07:38:06 AM PDT 24
Peak memory 198576 kb
Host smart-12c61975-533a-4358-aa71-2c74350dfece
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865736809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3865736809
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.271140173
Short name T560
Test name
Test status
Simulation time 32275194 ps
CPU time 0.95 seconds
Started Jul 02 07:37:48 AM PDT 24
Finished Jul 02 07:38:00 AM PDT 24
Peak memory 196068 kb
Host smart-5514ac17-42ce-4967-a926-26afcebb1dfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271140173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger.
271140173
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.1699183039
Short name T347
Test name
Test status
Simulation time 32725474 ps
CPU time 0.88 seconds
Started Jul 02 07:37:43 AM PDT 24
Finished Jul 02 07:37:55 AM PDT 24
Peak memory 197000 kb
Host smart-77537a4d-8414-4bca-8ec5-a99f1f5d7507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699183039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1699183039
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.1382509401
Short name T185
Test name
Test status
Simulation time 65295308 ps
CPU time 0.89 seconds
Started Jul 02 07:37:41 AM PDT 24
Finished Jul 02 07:37:54 AM PDT 24
Peak memory 197152 kb
Host smart-f1bd9a79-788f-4e10-b0c4-01edcf7d8498
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382509401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.1382509401
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2919332759
Short name T603
Test name
Test status
Simulation time 527845868 ps
CPU time 4.3 seconds
Started Jul 02 07:37:40 AM PDT 24
Finished Jul 02 07:37:56 AM PDT 24
Peak memory 198404 kb
Host smart-53b82758-b538-48ca-8853-3b4516b6236e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919332759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.2919332759
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.3652172289
Short name T559
Test name
Test status
Simulation time 36031759 ps
CPU time 0.99 seconds
Started Jul 02 07:39:11 AM PDT 24
Finished Jul 02 07:39:17 AM PDT 24
Peak memory 196968 kb
Host smart-a28bd673-bce8-4366-a393-4609f85d3087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652172289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3652172289
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2562054438
Short name T568
Test name
Test status
Simulation time 37952332 ps
CPU time 0.92 seconds
Started Jul 02 07:38:42 AM PDT 24
Finished Jul 02 07:38:58 AM PDT 24
Peak memory 196268 kb
Host smart-51d81c0b-37c4-461b-873a-ad273582bd5d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562054438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2562054438
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1622047963
Short name T108
Test name
Test status
Simulation time 4653849851 ps
CPU time 51.92 seconds
Started Jul 02 07:37:48 AM PDT 24
Finished Jul 02 07:38:51 AM PDT 24
Peak memory 198596 kb
Host smart-a6086a94-881e-4be8-a64b-79d5b77b00c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622047963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1622047963
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.3749804347
Short name T660
Test name
Test status
Simulation time 90416858 ps
CPU time 0.66 seconds
Started Jul 02 07:37:35 AM PDT 24
Finished Jul 02 07:37:48 AM PDT 24
Peak memory 195380 kb
Host smart-1721ba19-378b-404d-bd44-50f6155ac214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749804347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.3749804347
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.465501495
Short name T506
Test name
Test status
Simulation time 14173241132 ps
CPU time 23.11 seconds
Started Jul 02 07:37:54 AM PDT 24
Finished Jul 02 07:38:27 AM PDT 24
Peak memory 197768 kb
Host smart-fab55c46-ce6a-44e4-820b-45dffb84528f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465501495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.465501495
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.4192963431
Short name T479
Test name
Test status
Simulation time 399345741 ps
CPU time 1.1 seconds
Started Jul 02 07:37:59 AM PDT 24
Finished Jul 02 07:38:11 AM PDT 24
Peak memory 198320 kb
Host smart-9d7b30ae-4754-4a99-b100-0bac75700fd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192963431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.4192963431
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2904456913
Short name T707
Test name
Test status
Simulation time 38822681 ps
CPU time 0.82 seconds
Started Jul 02 07:37:28 AM PDT 24
Finished Jul 02 07:37:38 AM PDT 24
Peak memory 196284 kb
Host smart-9cfda48b-0b5c-443d-9324-5df82f1d42fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904456913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2904456913
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.4000158364
Short name T103
Test name
Test status
Simulation time 95645685 ps
CPU time 3.58 seconds
Started Jul 02 07:37:40 AM PDT 24
Finished Jul 02 07:37:56 AM PDT 24
Peak memory 198636 kb
Host smart-2cfa9c0f-cf28-464f-9ab5-e9eeebd40fd1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000158364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.4000158364
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.465611739
Short name T131
Test name
Test status
Simulation time 348616761 ps
CPU time 2.79 seconds
Started Jul 02 07:37:48 AM PDT 24
Finished Jul 02 07:38:01 AM PDT 24
Peak memory 197780 kb
Host smart-f4b381e1-fcff-49e4-9a68-ce6c5272d9f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465611739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
465611739
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.2043455077
Short name T166
Test name
Test status
Simulation time 25202149 ps
CPU time 0.71 seconds
Started Jul 02 07:37:33 AM PDT 24
Finished Jul 02 07:37:44 AM PDT 24
Peak memory 195804 kb
Host smart-23f902a4-6b71-4b0f-bb8b-7ce486e6b337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043455077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.2043455077
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.1953880554
Short name T215
Test name
Test status
Simulation time 32476145 ps
CPU time 0.83 seconds
Started Jul 02 07:37:34 AM PDT 24
Finished Jul 02 07:37:47 AM PDT 24
Peak memory 196312 kb
Host smart-3864544b-820c-4e18-9f79-44996d6d6b7d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953880554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.1953880554
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.1310498891
Short name T126
Test name
Test status
Simulation time 807250382 ps
CPU time 5.41 seconds
Started Jul 02 07:37:52 AM PDT 24
Finished Jul 02 07:38:08 AM PDT 24
Peak memory 198816 kb
Host smart-168721ea-52cb-4a85-83f0-1ddf1550acbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310498891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.1310498891
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.2294916523
Short name T446
Test name
Test status
Simulation time 207302122 ps
CPU time 1.07 seconds
Started Jul 02 07:39:07 AM PDT 24
Finished Jul 02 07:39:16 AM PDT 24
Peak memory 196908 kb
Host smart-15094488-4cf4-46f4-b1ea-b03a275d5ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294916523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.2294916523
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3217340597
Short name T179
Test name
Test status
Simulation time 61611416 ps
CPU time 1.04 seconds
Started Jul 02 07:37:58 AM PDT 24
Finished Jul 02 07:38:09 AM PDT 24
Peak memory 196964 kb
Host smart-69fd64f8-eef3-4561-a1fb-2d9ec6ee962d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217340597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3217340597
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2440175665
Short name T3
Test name
Test status
Simulation time 208616370725 ps
CPU time 102.84 seconds
Started Jul 02 07:37:40 AM PDT 24
Finished Jul 02 07:39:35 AM PDT 24
Peak memory 198524 kb
Host smart-e110625b-8094-452b-980b-7f1dc1509388
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440175665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2440175665
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.1976302710
Short name T562
Test name
Test status
Simulation time 116380107865 ps
CPU time 951.84 seconds
Started Jul 02 07:37:40 AM PDT 24
Finished Jul 02 07:53:43 AM PDT 24
Peak memory 198680 kb
Host smart-4d1e8091-b070-4ab9-b925-b489ca3059aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1976302710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.1976302710
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1028923996
Short name T440
Test name
Test status
Simulation time 14293883 ps
CPU time 0.57 seconds
Started Jul 02 07:37:41 AM PDT 24
Finished Jul 02 07:37:54 AM PDT 24
Peak memory 195088 kb
Host smart-33a24049-521c-48ab-bf0f-c890f67e82f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028923996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1028923996
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.1650612860
Short name T242
Test name
Test status
Simulation time 104339725 ps
CPU time 0.73 seconds
Started Jul 02 07:37:41 AM PDT 24
Finished Jul 02 07:37:53 AM PDT 24
Peak memory 195624 kb
Host smart-faaa3f45-d27f-4409-acf8-c4167adc3ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650612860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.1650612860
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.1818421158
Short name T699
Test name
Test status
Simulation time 865255097 ps
CPU time 22.99 seconds
Started Jul 02 07:39:08 AM PDT 24
Finished Jul 02 07:39:38 AM PDT 24
Peak memory 197296 kb
Host smart-1fd3e65b-f17b-47c1-b48d-cc7bce393ca9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818421158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.1818421158
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1405117414
Short name T443
Test name
Test status
Simulation time 65482968 ps
CPU time 0.73 seconds
Started Jul 02 07:37:52 AM PDT 24
Finished Jul 02 07:38:04 AM PDT 24
Peak memory 196912 kb
Host smart-62347c6f-0126-42ed-8c49-619d4af0901c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405117414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1405117414
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3903510247
Short name T472
Test name
Test status
Simulation time 43308069 ps
CPU time 1.13 seconds
Started Jul 02 07:37:43 AM PDT 24
Finished Jul 02 07:37:55 AM PDT 24
Peak memory 197344 kb
Host smart-30622375-7c9a-4077-bd92-e6818db255ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903510247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3903510247
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3449801406
Short name T542
Test name
Test status
Simulation time 286632488 ps
CPU time 1.52 seconds
Started Jul 02 07:39:08 AM PDT 24
Finished Jul 02 07:39:17 AM PDT 24
Peak memory 197160 kb
Host smart-35ecf9c8-1d6d-4780-83ba-bd57d4361224
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449801406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3449801406
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.1179690162
Short name T236
Test name
Test status
Simulation time 158132641 ps
CPU time 3.32 seconds
Started Jul 02 07:37:30 AM PDT 24
Finished Jul 02 07:37:42 AM PDT 24
Peak memory 196936 kb
Host smart-bcf4b3e9-e55e-4c84-8a40-4b01cbaa93d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179690162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.1179690162
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.559177116
Short name T300
Test name
Test status
Simulation time 46652027 ps
CPU time 0.93 seconds
Started Jul 02 07:37:55 AM PDT 24
Finished Jul 02 07:38:07 AM PDT 24
Peak memory 196996 kb
Host smart-fbc6b0a9-e096-48e8-91cd-b8fdc614fb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559177116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.559177116
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.1469843503
Short name T326
Test name
Test status
Simulation time 19124741 ps
CPU time 0.75 seconds
Started Jul 02 07:37:45 AM PDT 24
Finished Jul 02 07:37:56 AM PDT 24
Peak memory 195992 kb
Host smart-7cd58582-b97b-491d-9e28-654c2f401c0c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469843503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.1469843503
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1097765792
Short name T20
Test name
Test status
Simulation time 408342482 ps
CPU time 2.04 seconds
Started Jul 02 07:37:51 AM PDT 24
Finished Jul 02 07:38:04 AM PDT 24
Peak memory 198452 kb
Host smart-c903e28e-e3a8-4556-b971-b3d74c6a8819
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097765792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1097765792
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2297801493
Short name T398
Test name
Test status
Simulation time 379349015 ps
CPU time 1.34 seconds
Started Jul 02 07:38:03 AM PDT 24
Finished Jul 02 07:38:16 AM PDT 24
Peak memory 196032 kb
Host smart-88d1d89b-bc20-4696-ab47-b6e8a542b6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297801493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2297801493
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2525623184
Short name T637
Test name
Test status
Simulation time 29980453 ps
CPU time 0.87 seconds
Started Jul 02 07:37:46 AM PDT 24
Finished Jul 02 07:37:56 AM PDT 24
Peak memory 195996 kb
Host smart-ec460a42-8840-4319-9fbd-81f74141e5fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525623184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2525623184
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2714828969
Short name T470
Test name
Test status
Simulation time 8378038022 ps
CPU time 54.85 seconds
Started Jul 02 07:37:51 AM PDT 24
Finished Jul 02 07:38:57 AM PDT 24
Peak memory 198628 kb
Host smart-c468b6cb-8e7e-4265-ade4-4d028381f2b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714828969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2714828969
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.3661507241
Short name T680
Test name
Test status
Simulation time 55198795071 ps
CPU time 992.49 seconds
Started Jul 02 07:37:49 AM PDT 24
Finished Jul 02 07:54:32 AM PDT 24
Peak memory 198692 kb
Host smart-d6ce4b4d-b6fd-4e77-9538-36ea9053ad4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3661507241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.3661507241
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2651852851
Short name T525
Test name
Test status
Simulation time 35432887 ps
CPU time 0.55 seconds
Started Jul 02 07:37:43 AM PDT 24
Finished Jul 02 07:37:55 AM PDT 24
Peak memory 194420 kb
Host smart-8aaa394b-0147-4d0c-917d-afb18e9e566c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651852851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2651852851
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.3556165705
Short name T329
Test name
Test status
Simulation time 148343546 ps
CPU time 0.77 seconds
Started Jul 02 07:37:58 AM PDT 24
Finished Jul 02 07:38:09 AM PDT 24
Peak memory 195872 kb
Host smart-d79b9832-27d9-45ab-b7df-f16b89b8442a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556165705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.3556165705
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.523364637
Short name T258
Test name
Test status
Simulation time 332762175 ps
CPU time 8.03 seconds
Started Jul 02 07:38:02 AM PDT 24
Finished Jul 02 07:38:21 AM PDT 24
Peak memory 197456 kb
Host smart-6b8742ca-a363-478b-a326-eec4caccacf2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523364637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stres
s.523364637
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.2287647543
Short name T271
Test name
Test status
Simulation time 113555671 ps
CPU time 0.95 seconds
Started Jul 02 07:37:45 AM PDT 24
Finished Jul 02 07:37:56 AM PDT 24
Peak memory 198316 kb
Host smart-98e390fd-551d-40e9-a3f4-4ab1eee3b656
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287647543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.2287647543
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.4133304735
Short name T213
Test name
Test status
Simulation time 305119686 ps
CPU time 1.03 seconds
Started Jul 02 07:37:43 AM PDT 24
Finished Jul 02 07:37:55 AM PDT 24
Peak memory 196380 kb
Host smart-b438a0ef-557c-47d1-a9f7-bc49b8904c9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133304735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.4133304735
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3751149662
Short name T431
Test name
Test status
Simulation time 79379845 ps
CPU time 1.58 seconds
Started Jul 02 07:37:53 AM PDT 24
Finished Jul 02 07:38:05 AM PDT 24
Peak memory 196736 kb
Host smart-0345da56-1f9e-4496-92a6-3aa00b23a62c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751149662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3751149662
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.4288587334
Short name T567
Test name
Test status
Simulation time 184466223 ps
CPU time 1.74 seconds
Started Jul 02 07:37:44 AM PDT 24
Finished Jul 02 07:37:56 AM PDT 24
Peak memory 196516 kb
Host smart-04dcf34a-727a-4de0-b2f6-1ffb9e3e25e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288587334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.4288587334
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3733068024
Short name T657
Test name
Test status
Simulation time 238946546 ps
CPU time 1.2 seconds
Started Jul 02 07:37:55 AM PDT 24
Finished Jul 02 07:38:06 AM PDT 24
Peak memory 198504 kb
Host smart-bde9f2d6-c11c-4973-96c3-07722b100e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733068024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3733068024
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.616163440
Short name T335
Test name
Test status
Simulation time 79641125 ps
CPU time 0.93 seconds
Started Jul 02 07:37:47 AM PDT 24
Finished Jul 02 07:37:58 AM PDT 24
Peak memory 196392 kb
Host smart-9359d3b8-6868-467d-9b4e-39cfd3a51c38
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616163440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup
_pulldown.616163440
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.296725749
Short name T409
Test name
Test status
Simulation time 354849776 ps
CPU time 4.93 seconds
Started Jul 02 07:37:52 AM PDT 24
Finished Jul 02 07:38:08 AM PDT 24
Peak memory 198868 kb
Host smart-dd034aae-f7be-44bf-8852-05ae9f432b8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296725749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ran
dom_long_reg_writes_reg_reads.296725749
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.2501747843
Short name T305
Test name
Test status
Simulation time 40828780 ps
CPU time 1.07 seconds
Started Jul 02 07:37:58 AM PDT 24
Finished Jul 02 07:38:09 AM PDT 24
Peak memory 196128 kb
Host smart-a498f9d6-f9aa-4cfd-a67a-0653290a7e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501747843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.2501747843
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.2271518944
Short name T46
Test name
Test status
Simulation time 140598878 ps
CPU time 1.1 seconds
Started Jul 02 07:37:57 AM PDT 24
Finished Jul 02 07:38:09 AM PDT 24
Peak memory 196624 kb
Host smart-0afe859e-1344-4596-9a48-b70c301f2e3a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271518944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.2271518944
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.594994990
Short name T377
Test name
Test status
Simulation time 64733358767 ps
CPU time 185.62 seconds
Started Jul 02 07:37:45 AM PDT 24
Finished Jul 02 07:41:01 AM PDT 24
Peak memory 198660 kb
Host smart-e28fef19-a1b1-4bac-9e1c-0a9926a73cae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594994990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.g
pio_stress_all.594994990
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.3741946576
Short name T543
Test name
Test status
Simulation time 79502278235 ps
CPU time 1857.84 seconds
Started Jul 02 07:37:37 AM PDT 24
Finished Jul 02 08:08:47 AM PDT 24
Peak memory 198648 kb
Host smart-4eef7985-df7b-43a0-9c4b-9e4d35897d5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3741946576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.3741946576
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2259785304
Short name T296
Test name
Test status
Simulation time 11626131 ps
CPU time 0.54 seconds
Started Jul 02 07:37:44 AM PDT 24
Finished Jul 02 07:37:55 AM PDT 24
Peak memory 195116 kb
Host smart-21cb0f0c-75ed-49a2-8e80-0ca41211974b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259785304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2259785304
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.302574694
Short name T373
Test name
Test status
Simulation time 18406193 ps
CPU time 0.66 seconds
Started Jul 02 07:37:39 AM PDT 24
Finished Jul 02 07:37:51 AM PDT 24
Peak memory 194792 kb
Host smart-6cdda884-7859-447b-8402-295d4f6a464b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302574694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.302574694
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.3338973064
Short name T275
Test name
Test status
Simulation time 339779524 ps
CPU time 8.76 seconds
Started Jul 02 07:37:48 AM PDT 24
Finished Jul 02 07:38:07 AM PDT 24
Peak memory 197476 kb
Host smart-8926bca7-79e3-47e8-af81-6c94bcf0b996
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338973064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.3338973064
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.3286248940
Short name T268
Test name
Test status
Simulation time 84824557 ps
CPU time 0.93 seconds
Started Jul 02 07:37:56 AM PDT 24
Finished Jul 02 07:38:08 AM PDT 24
Peak memory 198204 kb
Host smart-b9ac89f6-1652-43cc-81dc-dfd71eb1f98c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286248940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3286248940
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.3503337503
Short name T331
Test name
Test status
Simulation time 314497629 ps
CPU time 1.25 seconds
Started Jul 02 07:37:40 AM PDT 24
Finished Jul 02 07:37:52 AM PDT 24
Peak memory 196292 kb
Host smart-83ffa164-293e-43dd-8d3e-77d3f12029d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503337503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.3503337503
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2377242711
Short name T360
Test name
Test status
Simulation time 207572569 ps
CPU time 2.18 seconds
Started Jul 02 07:37:43 AM PDT 24
Finished Jul 02 07:37:57 AM PDT 24
Peak memory 198468 kb
Host smart-ec1d9dff-054d-4f3f-ac7b-3a1bc2d3c267
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377242711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2377242711
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.3870490372
Short name T549
Test name
Test status
Simulation time 380910155 ps
CPU time 2.64 seconds
Started Jul 02 07:37:57 AM PDT 24
Finished Jul 02 07:38:10 AM PDT 24
Peak memory 197532 kb
Host smart-3770d223-cf62-4d29-a79c-97b7a5c43663
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870490372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.3870490372
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3993394993
Short name T263
Test name
Test status
Simulation time 35198659 ps
CPU time 1.16 seconds
Started Jul 02 07:37:37 AM PDT 24
Finished Jul 02 07:37:49 AM PDT 24
Peak memory 197540 kb
Host smart-0a089ff6-8410-479c-be7a-46d618db1b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993394993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3993394993
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.6797166
Short name T616
Test name
Test status
Simulation time 59967321 ps
CPU time 1.37 seconds
Started Jul 02 07:37:50 AM PDT 24
Finished Jul 02 07:38:02 AM PDT 24
Peak memory 197364 kb
Host smart-781182b1-1650-4932-a465-dd4d4e0705a6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6797166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullup_p
ulldown.6797166
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.2276110548
Short name T212
Test name
Test status
Simulation time 475790742 ps
CPU time 1.96 seconds
Started Jul 02 07:37:43 AM PDT 24
Finished Jul 02 07:37:56 AM PDT 24
Peak memory 198420 kb
Host smart-725ad85f-01ba-4583-bf07-5cd0768deccb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276110548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.2276110548
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3782156306
Short name T240
Test name
Test status
Simulation time 185914131 ps
CPU time 0.91 seconds
Started Jul 02 07:37:50 AM PDT 24
Finished Jul 02 07:38:02 AM PDT 24
Peak memory 196796 kb
Host smart-05d1a838-7dc2-4140-a186-7f7138af34b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782156306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3782156306
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.4209892747
Short name T540
Test name
Test status
Simulation time 660129865 ps
CPU time 1.13 seconds
Started Jul 02 07:37:35 AM PDT 24
Finished Jul 02 07:37:48 AM PDT 24
Peak memory 196232 kb
Host smart-c55e7110-8e64-47af-be93-4dcc90768042
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209892747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.4209892747
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.632081608
Short name T538
Test name
Test status
Simulation time 21299308472 ps
CPU time 61.02 seconds
Started Jul 02 07:37:56 AM PDT 24
Finished Jul 02 07:39:08 AM PDT 24
Peak memory 198604 kb
Host smart-e4e8d362-6f6d-4365-a5c1-17fc833227c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632081608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.g
pio_stress_all.632081608
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.3277881070
Short name T235
Test name
Test status
Simulation time 36845417 ps
CPU time 0.53 seconds
Started Jul 02 07:37:47 AM PDT 24
Finished Jul 02 07:37:58 AM PDT 24
Peak memory 194436 kb
Host smart-8c9ca4aa-b8a8-44ea-9b8c-8b58ef567277
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277881070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.3277881070
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3076433223
Short name T529
Test name
Test status
Simulation time 39575045 ps
CPU time 0.93 seconds
Started Jul 02 07:37:46 AM PDT 24
Finished Jul 02 07:37:57 AM PDT 24
Peak memory 196948 kb
Host smart-d1c085ae-53c2-437d-995c-91df2be4ece7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076433223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3076433223
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_full_random.1597542778
Short name T469
Test name
Test status
Simulation time 29977934 ps
CPU time 0.76 seconds
Started Jul 02 07:37:55 AM PDT 24
Finished Jul 02 07:38:06 AM PDT 24
Peak memory 196744 kb
Host smart-b1b14027-49b4-475c-a529-b0e0e1d0e25b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597542778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.1597542778
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.2225655769
Short name T232
Test name
Test status
Simulation time 50444609 ps
CPU time 0.91 seconds
Started Jul 02 07:37:50 AM PDT 24
Finished Jul 02 07:38:01 AM PDT 24
Peak memory 196956 kb
Host smart-0f2b347c-5a5a-4ef7-af44-ac20863d5cf0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225655769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.2225655769
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2062470815
Short name T514
Test name
Test status
Simulation time 78494171 ps
CPU time 1.64 seconds
Started Jul 02 07:37:45 AM PDT 24
Finished Jul 02 07:37:57 AM PDT 24
Peak memory 197052 kb
Host smart-89d194aa-3921-437b-bfaf-ea94f533849e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062470815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2062470815
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.3434769474
Short name T575
Test name
Test status
Simulation time 706544834 ps
CPU time 1.22 seconds
Started Jul 02 07:37:37 AM PDT 24
Finished Jul 02 07:37:50 AM PDT 24
Peak memory 196340 kb
Host smart-6c82ec2f-1f0d-47ec-90c5-5261a8678995
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434769474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.3434769474
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.1472856185
Short name T442
Test name
Test status
Simulation time 29814123 ps
CPU time 1.06 seconds
Started Jul 02 07:38:06 AM PDT 24
Finished Jul 02 07:38:22 AM PDT 24
Peak memory 196576 kb
Host smart-136e8ee1-1bc7-4d26-8c45-13669f449ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472856185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.1472856185
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3247094199
Short name T270
Test name
Test status
Simulation time 38613772 ps
CPU time 0.88 seconds
Started Jul 02 07:37:34 AM PDT 24
Finished Jul 02 07:37:47 AM PDT 24
Peak memory 196492 kb
Host smart-e7b5f99b-1066-430b-a1c5-67b254a6aacc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247094199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3247094199
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3186162882
Short name T336
Test name
Test status
Simulation time 495692709 ps
CPU time 5.61 seconds
Started Jul 02 07:37:34 AM PDT 24
Finished Jul 02 07:37:52 AM PDT 24
Peak memory 198620 kb
Host smart-abcde38b-ad80-4582-a8a8-92c2c4bfa6c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186162882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3186162882
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.4004181974
Short name T651
Test name
Test status
Simulation time 289931737 ps
CPU time 1.27 seconds
Started Jul 02 07:37:41 AM PDT 24
Finished Jul 02 07:37:54 AM PDT 24
Peak memory 195940 kb
Host smart-9bb18007-62fa-49f2-94e7-3d2b258983d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004181974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.4004181974
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.187631114
Short name T153
Test name
Test status
Simulation time 77939155 ps
CPU time 1.03 seconds
Started Jul 02 07:37:52 AM PDT 24
Finished Jul 02 07:38:04 AM PDT 24
Peak memory 196748 kb
Host smart-7e3fbbbf-8444-46b4-ab57-43d3524eb389
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187631114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.187631114
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.2076772480
Short name T180
Test name
Test status
Simulation time 954994236 ps
CPU time 23.34 seconds
Started Jul 02 07:37:59 AM PDT 24
Finished Jul 02 07:38:33 AM PDT 24
Peak memory 198440 kb
Host smart-145cef47-a9f2-46b6-9fa3-b892a829dbad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076772480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.2076772480
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.2132769348
Short name T639
Test name
Test status
Simulation time 51833940745 ps
CPU time 1421.7 seconds
Started Jul 02 07:37:50 AM PDT 24
Finished Jul 02 08:01:42 AM PDT 24
Peak memory 198704 kb
Host smart-e990d95a-aa54-4774-b182-f106cbeca96e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2132769348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.2132769348
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.2069200744
Short name T418
Test name
Test status
Simulation time 15383700 ps
CPU time 0.56 seconds
Started Jul 02 07:37:46 AM PDT 24
Finished Jul 02 07:37:57 AM PDT 24
Peak memory 194660 kb
Host smart-55d73b32-eee3-495e-a317-a9886b4170dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069200744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.2069200744
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1554878951
Short name T161
Test name
Test status
Simulation time 160703691 ps
CPU time 0.87 seconds
Started Jul 02 07:37:51 AM PDT 24
Finished Jul 02 07:38:03 AM PDT 24
Peak memory 196948 kb
Host smart-af813ae3-ba03-4516-adc7-e29ff10cfe0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554878951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1554878951
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2740726159
Short name T676
Test name
Test status
Simulation time 906652679 ps
CPU time 9.98 seconds
Started Jul 02 07:38:00 AM PDT 24
Finished Jul 02 07:38:20 AM PDT 24
Peak memory 197548 kb
Host smart-a4d63fb5-0405-40db-8097-1bb9c3eda760
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740726159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2740726159
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.2530370318
Short name T63
Test name
Test status
Simulation time 62262537 ps
CPU time 0.71 seconds
Started Jul 02 07:37:58 AM PDT 24
Finished Jul 02 07:38:10 AM PDT 24
Peak memory 195944 kb
Host smart-e9720770-825d-4c61-abdf-928aff451dd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530370318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.2530370318
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3128723042
Short name T471
Test name
Test status
Simulation time 286304954 ps
CPU time 1.21 seconds
Started Jul 02 07:38:08 AM PDT 24
Finished Jul 02 07:38:25 AM PDT 24
Peak memory 196508 kb
Host smart-50a5553e-6660-4fc6-9621-00e5011eb5ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128723042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3128723042
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3211425102
Short name T308
Test name
Test status
Simulation time 190694340 ps
CPU time 3.18 seconds
Started Jul 02 07:37:47 AM PDT 24
Finished Jul 02 07:38:01 AM PDT 24
Peak memory 198592 kb
Host smart-274bcf80-3899-4fb1-8397-b6d63291bffc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211425102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.3211425102
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.2924096903
Short name T112
Test name
Test status
Simulation time 571643284 ps
CPU time 2.89 seconds
Started Jul 02 07:37:43 AM PDT 24
Finished Jul 02 07:37:57 AM PDT 24
Peak memory 196308 kb
Host smart-92fb4473-23df-4373-a71c-69240fb5198b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924096903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.2924096903
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.1712985017
Short name T26
Test name
Test status
Simulation time 76321063 ps
CPU time 0.89 seconds
Started Jul 02 07:37:50 AM PDT 24
Finished Jul 02 07:38:01 AM PDT 24
Peak memory 196256 kb
Host smart-d1001a1e-6c1a-4868-8d39-a0d85737fd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712985017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.1712985017
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.2144118320
Short name T486
Test name
Test status
Simulation time 210581225 ps
CPU time 0.98 seconds
Started Jul 02 07:37:46 AM PDT 24
Finished Jul 02 07:37:58 AM PDT 24
Peak memory 196536 kb
Host smart-fb12fc7d-278b-44f2-8162-f3986e2a55fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144118320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.2144118320
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.1389255900
Short name T399
Test name
Test status
Simulation time 353183640 ps
CPU time 5.15 seconds
Started Jul 02 07:37:52 AM PDT 24
Finished Jul 02 07:38:08 AM PDT 24
Peak memory 198428 kb
Host smart-8372e38d-4c89-40af-9ab5-7d2adec55dfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389255900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.1389255900
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.71477557
Short name T574
Test name
Test status
Simulation time 163643464 ps
CPU time 0.94 seconds
Started Jul 02 07:37:58 AM PDT 24
Finished Jul 02 07:38:16 AM PDT 24
Peak memory 197428 kb
Host smart-b3908191-e0fe-43b0-bf27-f6af9f3012aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71477557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.71477557
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1776224918
Short name T16
Test name
Test status
Simulation time 23696252 ps
CPU time 0.84 seconds
Started Jul 02 07:37:54 AM PDT 24
Finished Jul 02 07:38:05 AM PDT 24
Peak memory 197580 kb
Host smart-6cba4823-abbd-4687-b258-78c83817a81a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776224918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1776224918
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.3563362890
Short name T683
Test name
Test status
Simulation time 28306739150 ps
CPU time 50.03 seconds
Started Jul 02 07:38:09 AM PDT 24
Finished Jul 02 07:39:16 AM PDT 24
Peak memory 198560 kb
Host smart-678b412d-a513-41c9-849e-b4d2f4ded6dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563362890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.3563362890
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3947443619
Short name T159
Test name
Test status
Simulation time 105714393 ps
CPU time 0.59 seconds
Started Jul 02 07:37:57 AM PDT 24
Finished Jul 02 07:38:08 AM PDT 24
Peak memory 195728 kb
Host smart-28f7aa78-5392-4613-be11-481164fc7fdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947443619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3947443619
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3298100109
Short name T219
Test name
Test status
Simulation time 239019165 ps
CPU time 0.79 seconds
Started Jul 02 07:38:04 AM PDT 24
Finished Jul 02 07:38:17 AM PDT 24
Peak memory 195684 kb
Host smart-e050c44b-3b23-4fd3-ac9b-daa171119641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298100109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3298100109
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1016025079
Short name T155
Test name
Test status
Simulation time 753943434 ps
CPU time 25.12 seconds
Started Jul 02 07:38:08 AM PDT 24
Finished Jul 02 07:38:50 AM PDT 24
Peak memory 197436 kb
Host smart-d05ae469-a23d-41b6-85f0-5f6a912fbe53
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016025079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1016025079
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.3007114002
Short name T245
Test name
Test status
Simulation time 67567558 ps
CPU time 0.95 seconds
Started Jul 02 07:38:19 AM PDT 24
Finished Jul 02 07:38:39 AM PDT 24
Peak memory 197420 kb
Host smart-250f1870-a4dc-4bbb-9030-f9ef2d14c82a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007114002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.3007114002
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.4038888327
Short name T537
Test name
Test status
Simulation time 70019260 ps
CPU time 1.08 seconds
Started Jul 02 07:37:53 AM PDT 24
Finished Jul 02 07:38:04 AM PDT 24
Peak memory 196516 kb
Host smart-698e3276-dfb3-433c-873d-b01353692fe4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038888327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.4038888327
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3780101050
Short name T372
Test name
Test status
Simulation time 42640426 ps
CPU time 1.01 seconds
Started Jul 02 07:37:58 AM PDT 24
Finished Jul 02 07:38:09 AM PDT 24
Peak memory 196748 kb
Host smart-8867b7b6-2576-4c5e-ac39-9676d62713cf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780101050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3780101050
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.2175368110
Short name T301
Test name
Test status
Simulation time 191645422 ps
CPU time 2.14 seconds
Started Jul 02 07:38:10 AM PDT 24
Finished Jul 02 07:38:30 AM PDT 24
Peak memory 197636 kb
Host smart-9f84e0ba-11c3-443e-8b92-5c9cb8317290
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175368110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.2175368110
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.286269680
Short name T52
Test name
Test status
Simulation time 376976217 ps
CPU time 1.02 seconds
Started Jul 02 07:37:50 AM PDT 24
Finished Jul 02 07:38:02 AM PDT 24
Peak memory 197156 kb
Host smart-7d3814b4-868c-43f0-8624-1c38ffa3a060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286269680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.286269680
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2378727266
Short name T521
Test name
Test status
Simulation time 102559138 ps
CPU time 0.85 seconds
Started Jul 02 07:37:57 AM PDT 24
Finished Jul 02 07:38:09 AM PDT 24
Peak memory 197044 kb
Host smart-18f187de-a69b-45d1-bf38-5954b7346901
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378727266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2378727266
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.2684521737
Short name T325
Test name
Test status
Simulation time 962883039 ps
CPU time 2.33 seconds
Started Jul 02 07:37:53 AM PDT 24
Finished Jul 02 07:38:06 AM PDT 24
Peak memory 198132 kb
Host smart-c836e39b-4feb-487b-8cc6-15774c30038d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684521737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.2684521737
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.22715536
Short name T599
Test name
Test status
Simulation time 165079520 ps
CPU time 1.25 seconds
Started Jul 02 07:38:09 AM PDT 24
Finished Jul 02 07:38:27 AM PDT 24
Peak memory 196000 kb
Host smart-0859b0aa-de49-4507-86ee-b9cd630dd21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22715536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.22715536
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.633258235
Short name T186
Test name
Test status
Simulation time 138643741 ps
CPU time 1.14 seconds
Started Jul 02 07:37:56 AM PDT 24
Finished Jul 02 07:38:08 AM PDT 24
Peak memory 197176 kb
Host smart-23346361-bf7c-488d-9976-ccaf95d9b092
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633258235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.633258235
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.2082588149
Short name T453
Test name
Test status
Simulation time 21410338589 ps
CPU time 175.54 seconds
Started Jul 02 07:38:06 AM PDT 24
Finished Jul 02 07:41:15 AM PDT 24
Peak memory 198964 kb
Host smart-d10b7692-ed85-45dc-ba5f-36da5fd932c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082588149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.2082588149
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.1532555303
Short name T638
Test name
Test status
Simulation time 91872422071 ps
CPU time 582.38 seconds
Started Jul 02 07:38:03 AM PDT 24
Finished Jul 02 07:47:59 AM PDT 24
Peak memory 206956 kb
Host smart-6b7cf334-142d-4e7e-acdd-9b83b80707a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1532555303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.1532555303
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.2187294735
Short name T391
Test name
Test status
Simulation time 12775887 ps
CPU time 0.56 seconds
Started Jul 02 07:37:49 AM PDT 24
Finished Jul 02 07:37:59 AM PDT 24
Peak memory 194524 kb
Host smart-7b1c7715-40e0-4e1b-9e15-33d0a63ac53f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187294735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.2187294735
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3618415155
Short name T591
Test name
Test status
Simulation time 23393898 ps
CPU time 0.59 seconds
Started Jul 02 07:38:07 AM PDT 24
Finished Jul 02 07:38:23 AM PDT 24
Peak memory 195096 kb
Host smart-0291c99e-22df-40c1-9fc3-8ac173cb8d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618415155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3618415155
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.2446158599
Short name T162
Test name
Test status
Simulation time 470070127 ps
CPU time 23.73 seconds
Started Jul 02 07:37:48 AM PDT 24
Finished Jul 02 07:38:23 AM PDT 24
Peak memory 196692 kb
Host smart-a194bcf9-4cdf-4ade-8215-7f09c963435d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446158599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.2446158599
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.3604287481
Short name T703
Test name
Test status
Simulation time 84910321 ps
CPU time 1.02 seconds
Started Jul 02 07:37:48 AM PDT 24
Finished Jul 02 07:38:00 AM PDT 24
Peak memory 197288 kb
Host smart-1785db9d-e076-450f-bc65-3bef34476ef2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604287481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3604287481
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2680123764
Short name T229
Test name
Test status
Simulation time 292094591 ps
CPU time 1.2 seconds
Started Jul 02 07:37:55 AM PDT 24
Finished Jul 02 07:38:08 AM PDT 24
Peak memory 197240 kb
Host smart-e4c24f20-1891-4ef9-9cfa-2225ff530d81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680123764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2680123764
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1461000839
Short name T320
Test name
Test status
Simulation time 735668194 ps
CPU time 3.66 seconds
Started Jul 02 07:38:03 AM PDT 24
Finished Jul 02 07:38:19 AM PDT 24
Peak memory 198544 kb
Host smart-317e0e2f-a0e5-40d6-8550-7e0ae39593dc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461000839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1461000839
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.388884595
Short name T689
Test name
Test status
Simulation time 125289702 ps
CPU time 1.65 seconds
Started Jul 02 07:38:07 AM PDT 24
Finished Jul 02 07:38:25 AM PDT 24
Peak memory 196468 kb
Host smart-198be1ab-5257-4321-bdd9-79e0021ea582
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388884595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger.
388884595
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3457954974
Short name T313
Test name
Test status
Simulation time 52899593 ps
CPU time 0.76 seconds
Started Jul 02 07:38:09 AM PDT 24
Finished Jul 02 07:38:27 AM PDT 24
Peak memory 195816 kb
Host smart-cd72c249-80e7-4a94-9365-265116d9b463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457954974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3457954974
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.975286267
Short name T66
Test name
Test status
Simulation time 27815096 ps
CPU time 0.97 seconds
Started Jul 02 07:37:59 AM PDT 24
Finished Jul 02 07:38:10 AM PDT 24
Peak memory 196436 kb
Host smart-68dc48da-9f39-471e-83e0-f062b9156ffa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975286267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup
_pulldown.975286267
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.3360246533
Short name T321
Test name
Test status
Simulation time 328145798 ps
CPU time 3.77 seconds
Started Jul 02 07:37:57 AM PDT 24
Finished Jul 02 07:38:16 AM PDT 24
Peak memory 198480 kb
Host smart-2e790106-1819-4c4b-bbb4-fb5c1e1fee06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360246533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.3360246533
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2430875427
Short name T322
Test name
Test status
Simulation time 119639018 ps
CPU time 0.97 seconds
Started Jul 02 07:38:00 AM PDT 24
Finished Jul 02 07:38:11 AM PDT 24
Peak memory 196924 kb
Host smart-8803d4ba-cd32-4ed1-a925-53089fd384fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430875427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2430875427
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.235673609
Short name T205
Test name
Test status
Simulation time 67304539 ps
CPU time 0.84 seconds
Started Jul 02 07:38:09 AM PDT 24
Finished Jul 02 07:38:27 AM PDT 24
Peak memory 195836 kb
Host smart-ab796374-e743-44b3-a0c2-52a19b5937cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235673609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.235673609
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.4070225004
Short name T597
Test name
Test status
Simulation time 2257536820 ps
CPU time 54.37 seconds
Started Jul 02 07:37:58 AM PDT 24
Finished Jul 02 07:39:03 AM PDT 24
Peak memory 198588 kb
Host smart-4a205574-a1a5-411f-9acc-8dc7c8874a47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070225004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.4070225004
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.771620029
Short name T58
Test name
Test status
Simulation time 24707230230 ps
CPU time 742.22 seconds
Started Jul 02 07:38:08 AM PDT 24
Finished Jul 02 07:50:46 AM PDT 24
Peak memory 198796 kb
Host smart-85f68f95-9e74-46f1-9a34-61d1d9b58c65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=771620029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.771620029
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.2014597816
Short name T664
Test name
Test status
Simulation time 19987164 ps
CPU time 0.63 seconds
Started Jul 02 07:36:34 AM PDT 24
Finished Jul 02 07:36:41 AM PDT 24
Peak memory 193256 kb
Host smart-36f3aff4-ff27-47fb-b3e3-75f4c322f5d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014597816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2014597816
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.2859639108
Short name T558
Test name
Test status
Simulation time 76194929 ps
CPU time 0.89 seconds
Started Jul 02 07:35:14 AM PDT 24
Finished Jul 02 07:35:16 AM PDT 24
Peak memory 195800 kb
Host smart-b231cd36-5911-482e-8ebc-7c4926f1fb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859639108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.2859639108
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1228058691
Short name T119
Test name
Test status
Simulation time 3996170873 ps
CPU time 23.51 seconds
Started Jul 02 07:36:27 AM PDT 24
Finished Jul 02 07:36:53 AM PDT 24
Peak memory 197000 kb
Host smart-0be9d599-fc0a-4817-b1c6-bf141acba512
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228058691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1228058691
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.4110013652
Short name T604
Test name
Test status
Simulation time 78427409 ps
CPU time 0.87 seconds
Started Jul 02 07:36:38 AM PDT 24
Finished Jul 02 07:36:47 AM PDT 24
Peak memory 195776 kb
Host smart-b98613e4-0d9d-4828-85b1-9eb2a2ff5904
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110013652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.4110013652
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.3485166756
Short name T554
Test name
Test status
Simulation time 85115440 ps
CPU time 0.82 seconds
Started Jul 02 07:36:34 AM PDT 24
Finished Jul 02 07:36:42 AM PDT 24
Peak memory 196740 kb
Host smart-0b06ec12-4ab0-4f3a-ba3c-fa1d17c104f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485166756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.3485166756
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3126235637
Short name T419
Test name
Test status
Simulation time 237195236 ps
CPU time 2.59 seconds
Started Jul 02 07:35:20 AM PDT 24
Finished Jul 02 07:35:23 AM PDT 24
Peak memory 198424 kb
Host smart-6d75e0be-79d4-4027-ba34-8b5539665430
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126235637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3126235637
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3103072515
Short name T267
Test name
Test status
Simulation time 49377566 ps
CPU time 1.34 seconds
Started Jul 02 07:36:34 AM PDT 24
Finished Jul 02 07:36:43 AM PDT 24
Peak memory 197672 kb
Host smart-b9ae119f-6a8c-4f05-9829-af0c1c0999cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103072515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3103072515
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.2486985493
Short name T532
Test name
Test status
Simulation time 81157339 ps
CPU time 0.93 seconds
Started Jul 02 07:37:35 AM PDT 24
Finished Jul 02 07:37:47 AM PDT 24
Peak memory 196200 kb
Host smart-438d0867-ad6b-4711-8a09-f6d8cdabaaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486985493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.2486985493
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.3511166459
Short name T132
Test name
Test status
Simulation time 119329460 ps
CPU time 0.84 seconds
Started Jul 02 07:33:04 AM PDT 24
Finished Jul 02 07:33:05 AM PDT 24
Peak memory 196520 kb
Host smart-07c8cce1-2fad-467b-88c8-db511bcbe0e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511166459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.3511166459
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.2867925067
Short name T111
Test name
Test status
Simulation time 2200234573 ps
CPU time 3.79 seconds
Started Jul 02 07:36:11 AM PDT 24
Finished Jul 02 07:36:16 AM PDT 24
Peak memory 197380 kb
Host smart-1b4ea234-193c-4023-b145-d38b5d18cc85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867925067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.2867925067
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.2625135492
Short name T33
Test name
Test status
Simulation time 308876370 ps
CPU time 0.93 seconds
Started Jul 02 07:36:26 AM PDT 24
Finished Jul 02 07:36:29 AM PDT 24
Peak memory 215080 kb
Host smart-772c4487-f2b6-403c-9b31-e5837e354f59
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625135492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.2625135492
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.1428302417
Short name T48
Test name
Test status
Simulation time 47989375 ps
CPU time 0.83 seconds
Started Jul 02 07:36:35 AM PDT 24
Finished Jul 02 07:36:43 AM PDT 24
Peak memory 195860 kb
Host smart-b04858a0-fa32-475e-8d5a-c6960c898aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428302417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1428302417
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.531662411
Short name T50
Test name
Test status
Simulation time 801813326 ps
CPU time 0.92 seconds
Started Jul 02 07:37:12 AM PDT 24
Finished Jul 02 07:37:16 AM PDT 24
Peak memory 196036 kb
Host smart-80aaa793-7439-4c9f-b611-a4cd6491044a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531662411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.531662411
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3873700611
Short name T217
Test name
Test status
Simulation time 4218017309 ps
CPU time 52.84 seconds
Started Jul 02 07:36:21 AM PDT 24
Finished Jul 02 07:37:16 AM PDT 24
Peak memory 198448 kb
Host smart-1e6ea40e-7597-48a9-ae5e-0dc3975f8c78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873700611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3873700611
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.1897294586
Short name T59
Test name
Test status
Simulation time 42299794761 ps
CPU time 1093.08 seconds
Started Jul 02 07:33:18 AM PDT 24
Finished Jul 02 07:51:31 AM PDT 24
Peak memory 199140 kb
Host smart-0511aa6e-ed65-49f5-b3aa-17acd125f17d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1897294586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.1897294586
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2541652850
Short name T195
Test name
Test status
Simulation time 13961007 ps
CPU time 0.56 seconds
Started Jul 02 07:38:13 AM PDT 24
Finished Jul 02 07:38:36 AM PDT 24
Peak memory 194572 kb
Host smart-68ed2699-67e7-49a2-a7e7-dea053e5ff0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541652850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2541652850
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.581804676
Short name T123
Test name
Test status
Simulation time 16007447 ps
CPU time 0.62 seconds
Started Jul 02 07:38:08 AM PDT 24
Finished Jul 02 07:38:25 AM PDT 24
Peak memory 195236 kb
Host smart-3d3d80d5-1b0e-4524-9d6a-a489068628e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581804676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.581804676
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1668117399
Short name T620
Test name
Test status
Simulation time 124051181 ps
CPU time 6.14 seconds
Started Jul 02 07:37:49 AM PDT 24
Finished Jul 02 07:38:06 AM PDT 24
Peak memory 198504 kb
Host smart-58760856-33c4-4654-97cb-b0954d78ffce
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668117399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1668117399
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2571971778
Short name T21
Test name
Test status
Simulation time 177321561 ps
CPU time 0.75 seconds
Started Jul 02 07:38:00 AM PDT 24
Finished Jul 02 07:38:11 AM PDT 24
Peak memory 196984 kb
Host smart-089b2e9e-d8d7-418d-ad39-e68ea9e97a13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571971778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2571971778
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1200032853
Short name T376
Test name
Test status
Simulation time 21923158 ps
CPU time 0.72 seconds
Started Jul 02 07:38:14 AM PDT 24
Finished Jul 02 07:38:33 AM PDT 24
Peak memory 196648 kb
Host smart-1c7c4cb9-137d-4396-bdbe-ec0de816b0ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200032853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1200032853
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.2277152117
Short name T448
Test name
Test status
Simulation time 194710648 ps
CPU time 3.37 seconds
Started Jul 02 07:38:08 AM PDT 24
Finished Jul 02 07:38:27 AM PDT 24
Peak memory 198472 kb
Host smart-797d40bd-e8b1-4b23-ab14-bd2bca57ff6d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277152117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.2277152117
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.4221142471
Short name T208
Test name
Test status
Simulation time 175244653 ps
CPU time 2.91 seconds
Started Jul 02 07:38:03 AM PDT 24
Finished Jul 02 07:38:18 AM PDT 24
Peak memory 198476 kb
Host smart-19aad0b1-93ce-4dbe-953e-42eb3f7841e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221142471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.4221142471
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.3270680471
Short name T435
Test name
Test status
Simulation time 35497663 ps
CPU time 1.23 seconds
Started Jul 02 07:37:48 AM PDT 24
Finished Jul 02 07:37:59 AM PDT 24
Peak memory 197556 kb
Host smart-0f6c8188-0f46-4a52-a5fd-a2cbd7e096b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270680471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.3270680471
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.1887975162
Short name T341
Test name
Test status
Simulation time 79780418 ps
CPU time 1.01 seconds
Started Jul 02 07:38:01 AM PDT 24
Finished Jul 02 07:38:13 AM PDT 24
Peak memory 196304 kb
Host smart-1ffc8835-5c7c-41bf-805a-a2fc43691126
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887975162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.1887975162
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2290585931
Short name T10
Test name
Test status
Simulation time 536134647 ps
CPU time 3.53 seconds
Started Jul 02 07:38:04 AM PDT 24
Finished Jul 02 07:38:20 AM PDT 24
Peak memory 198440 kb
Host smart-fa8263d1-01b5-4511-ae0e-9bd7b404fe96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290585931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2290585931
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2696666366
Short name T681
Test name
Test status
Simulation time 73573709 ps
CPU time 1.31 seconds
Started Jul 02 07:38:04 AM PDT 24
Finished Jul 02 07:38:19 AM PDT 24
Peak memory 197324 kb
Host smart-dd79d28e-1e02-4d32-89ca-871f26efe2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696666366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2696666366
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.89395798
Short name T602
Test name
Test status
Simulation time 39542435 ps
CPU time 1.15 seconds
Started Jul 02 07:38:04 AM PDT 24
Finished Jul 02 07:38:18 AM PDT 24
Peak memory 197332 kb
Host smart-6edd10fd-e31a-471f-8f94-1ae82c01278a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89395798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.89395798
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2724511985
Short name T535
Test name
Test status
Simulation time 4193413545 ps
CPU time 90.22 seconds
Started Jul 02 07:38:10 AM PDT 24
Finished Jul 02 07:39:58 AM PDT 24
Peak memory 198524 kb
Host smart-4acb9b24-ca75-46c0-b55f-522108f63736
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724511985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2724511985
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.2701753907
Short name T28
Test name
Test status
Simulation time 153803292208 ps
CPU time 945.93 seconds
Started Jul 02 07:38:11 AM PDT 24
Finished Jul 02 07:54:15 AM PDT 24
Peak memory 198688 kb
Host smart-542cb38c-3e2a-4759-8b0a-a4dc5b39b899
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2701753907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.2701753907
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.2995165945
Short name T461
Test name
Test status
Simulation time 61596717 ps
CPU time 0.55 seconds
Started Jul 02 07:38:12 AM PDT 24
Finished Jul 02 07:38:30 AM PDT 24
Peak memory 194488 kb
Host smart-6d8fde67-ae4b-4dc8-ba44-99ed5c2ad240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995165945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.2995165945
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.134728232
Short name T550
Test name
Test status
Simulation time 39956222 ps
CPU time 0.93 seconds
Started Jul 02 07:38:02 AM PDT 24
Finished Jul 02 07:38:14 AM PDT 24
Peak memory 197800 kb
Host smart-4421f5e2-2185-43b8-95d2-e223ea3ed966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134728232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.134728232
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3265487965
Short name T206
Test name
Test status
Simulation time 7284776827 ps
CPU time 25.02 seconds
Started Jul 02 07:38:09 AM PDT 24
Finished Jul 02 07:38:51 AM PDT 24
Peak memory 197500 kb
Host smart-b1e03323-9d43-4c49-94d7-4d99c84100b3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265487965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3265487965
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2908657941
Short name T713
Test name
Test status
Simulation time 52232455 ps
CPU time 0.79 seconds
Started Jul 02 07:38:05 AM PDT 24
Finished Jul 02 07:38:19 AM PDT 24
Peak memory 196344 kb
Host smart-a33e03de-70bb-4cf6-952c-97ab21f460be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908657941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2908657941
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.437604385
Short name T633
Test name
Test status
Simulation time 76516486 ps
CPU time 0.76 seconds
Started Jul 02 07:37:54 AM PDT 24
Finished Jul 02 07:38:06 AM PDT 24
Peak memory 196304 kb
Host smart-761a62ff-279b-4663-a258-4c7d4c2c7b7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437604385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.437604385
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1027252954
Short name T690
Test name
Test status
Simulation time 66671424 ps
CPU time 2.29 seconds
Started Jul 02 07:38:08 AM PDT 24
Finished Jul 02 07:38:26 AM PDT 24
Peak memory 198460 kb
Host smart-0a70c278-f5b1-4e6d-af88-ae75d40af42b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027252954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1027252954
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1152387052
Short name T106
Test name
Test status
Simulation time 117737793 ps
CPU time 1.59 seconds
Started Jul 02 07:38:03 AM PDT 24
Finished Jul 02 07:38:16 AM PDT 24
Peak memory 196628 kb
Host smart-5f5e09bf-b9f6-4176-86ea-344367018adc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152387052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1152387052
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.3893223175
Short name T628
Test name
Test status
Simulation time 22677793 ps
CPU time 0.77 seconds
Started Jul 02 07:38:10 AM PDT 24
Finished Jul 02 07:38:28 AM PDT 24
Peak memory 196980 kb
Host smart-024ecbb6-8e75-4474-b0c9-262f8a9a99be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893223175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.3893223175
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1465218381
Short name T425
Test name
Test status
Simulation time 41748809 ps
CPU time 1.22 seconds
Started Jul 02 07:38:03 AM PDT 24
Finished Jul 02 07:38:16 AM PDT 24
Peak memory 197596 kb
Host smart-40413595-e2cf-4dbc-9814-b3fb29c2220e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465218381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.1465218381
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.4231478781
Short name T561
Test name
Test status
Simulation time 44057956 ps
CPU time 1.81 seconds
Started Jul 02 07:38:18 AM PDT 24
Finished Jul 02 07:38:40 AM PDT 24
Peak memory 198304 kb
Host smart-975482ac-bbfd-473f-83d4-2068416f4763
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231478781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.4231478781
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.173067977
Short name T278
Test name
Test status
Simulation time 33872446 ps
CPU time 0.95 seconds
Started Jul 02 07:38:11 AM PDT 24
Finished Jul 02 07:38:29 AM PDT 24
Peak memory 196208 kb
Host smart-02080e33-392a-4c66-b9eb-2d5d2dd4e8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173067977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.173067977
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2175827431
Short name T432
Test name
Test status
Simulation time 103658544 ps
CPU time 1.47 seconds
Started Jul 02 07:38:01 AM PDT 24
Finished Jul 02 07:38:14 AM PDT 24
Peak memory 197332 kb
Host smart-fbd90da2-f36c-4ae3-aa00-13d441856e6c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175827431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2175827431
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.2418302959
Short name T62
Test name
Test status
Simulation time 11753004599 ps
CPU time 145.94 seconds
Started Jul 02 07:38:03 AM PDT 24
Finished Jul 02 07:40:40 AM PDT 24
Peak memory 198576 kb
Host smart-68147472-0e81-4c79-9e3e-9fb48cd3d9cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418302959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.2418302959
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.3984634299
Short name T650
Test name
Test status
Simulation time 50416538 ps
CPU time 0.6 seconds
Started Jul 02 07:38:03 AM PDT 24
Finished Jul 02 07:38:15 AM PDT 24
Peak memory 194536 kb
Host smart-2b8d5aff-cc0e-43a1-b0db-fe79f36587b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984634299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3984634299
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.3546811641
Short name T400
Test name
Test status
Simulation time 40970085 ps
CPU time 0.84 seconds
Started Jul 02 07:38:15 AM PDT 24
Finished Jul 02 07:38:34 AM PDT 24
Peak memory 196180 kb
Host smart-db5de230-21f8-4112-ad50-9b0c10b6e2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546811641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.3546811641
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.2890830588
Short name T200
Test name
Test status
Simulation time 5879073677 ps
CPU time 22.59 seconds
Started Jul 02 07:38:02 AM PDT 24
Finished Jul 02 07:38:35 AM PDT 24
Peak memory 197480 kb
Host smart-f47ad661-f5a5-4cca-94ba-43dccec37557
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890830588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.2890830588
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.2994106622
Short name T309
Test name
Test status
Simulation time 58439704 ps
CPU time 0.74 seconds
Started Jul 02 07:38:09 AM PDT 24
Finished Jul 02 07:38:26 AM PDT 24
Peak memory 196996 kb
Host smart-499a9a73-f291-4caa-bddd-e8c736108475
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994106622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2994106622
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2265738780
Short name T190
Test name
Test status
Simulation time 70311257 ps
CPU time 1.08 seconds
Started Jul 02 07:37:56 AM PDT 24
Finished Jul 02 07:38:08 AM PDT 24
Peak memory 196620 kb
Host smart-7fe91cfc-8077-4483-866f-140f84fc1003
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265738780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2265738780
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2202237852
Short name T266
Test name
Test status
Simulation time 94444610 ps
CPU time 3.32 seconds
Started Jul 02 07:38:08 AM PDT 24
Finished Jul 02 07:38:28 AM PDT 24
Peak memory 198420 kb
Host smart-6e26439e-8254-4bf2-aa45-72c708cfab3b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202237852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2202237852
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.3511413318
Short name T148
Test name
Test status
Simulation time 497577802 ps
CPU time 1.66 seconds
Started Jul 02 07:38:02 AM PDT 24
Finished Jul 02 07:38:15 AM PDT 24
Peak memory 196420 kb
Host smart-2661bc5e-7747-477e-9c20-1901ac70ab10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511413318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.3511413318
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.4229379057
Short name T460
Test name
Test status
Simulation time 64172730 ps
CPU time 0.77 seconds
Started Jul 02 07:38:03 AM PDT 24
Finished Jul 02 07:38:15 AM PDT 24
Peak memory 196688 kb
Host smart-509eda50-2afd-407d-9860-02942aaca861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229379057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.4229379057
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2307799051
Short name T702
Test name
Test status
Simulation time 77538632 ps
CPU time 0.97 seconds
Started Jul 02 07:38:28 AM PDT 24
Finished Jul 02 07:38:48 AM PDT 24
Peak memory 197164 kb
Host smart-9215af1f-9af8-41fe-93ba-65d1815019cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307799051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2307799051
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3925119129
Short name T624
Test name
Test status
Simulation time 80946448 ps
CPU time 3.38 seconds
Started Jul 02 07:38:08 AM PDT 24
Finished Jul 02 07:38:28 AM PDT 24
Peak memory 198528 kb
Host smart-bc1cdf52-47c6-45d4-8b08-cead3e99e26e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925119129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.3925119129
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.153583179
Short name T385
Test name
Test status
Simulation time 61877759 ps
CPU time 1.04 seconds
Started Jul 02 07:38:12 AM PDT 24
Finished Jul 02 07:38:30 AM PDT 24
Peak memory 197696 kb
Host smart-6d592bc3-f1da-41ef-94cb-6842e2c93cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153583179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.153583179
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2060895617
Short name T618
Test name
Test status
Simulation time 213690598 ps
CPU time 1.08 seconds
Started Jul 02 07:37:55 AM PDT 24
Finished Jul 02 07:38:08 AM PDT 24
Peak memory 196736 kb
Host smart-29857c08-f501-4bab-a05a-78072727cbc4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060895617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2060895617
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.3029227925
Short name T386
Test name
Test status
Simulation time 6393185150 ps
CPU time 46.11 seconds
Started Jul 02 07:38:34 AM PDT 24
Finished Jul 02 07:39:37 AM PDT 24
Peak memory 198612 kb
Host smart-14e4f69d-dabf-4f6d-b560-493e0b931d0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029227925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.3029227925
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1314379292
Short name T674
Test name
Test status
Simulation time 54684927 ps
CPU time 0.59 seconds
Started Jul 02 07:38:09 AM PDT 24
Finished Jul 02 07:38:25 AM PDT 24
Peak memory 194752 kb
Host smart-4371b11d-80bf-45fe-9f4e-8ff581288f5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314379292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1314379292
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3825898115
Short name T244
Test name
Test status
Simulation time 19046587 ps
CPU time 0.63 seconds
Started Jul 02 07:37:57 AM PDT 24
Finished Jul 02 07:38:08 AM PDT 24
Peak memory 194304 kb
Host smart-d9de8a84-b808-4987-8d68-1ee0855ba46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825898115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3825898115
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.3546277182
Short name T501
Test name
Test status
Simulation time 470064733 ps
CPU time 12.28 seconds
Started Jul 02 07:38:13 AM PDT 24
Finished Jul 02 07:38:44 AM PDT 24
Peak memory 197360 kb
Host smart-a9c71e19-b84b-4a7a-94f2-9c0635dfe69c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546277182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.3546277182
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.2812493837
Short name T547
Test name
Test status
Simulation time 72719090 ps
CPU time 0.59 seconds
Started Jul 02 07:38:13 AM PDT 24
Finished Jul 02 07:38:31 AM PDT 24
Peak memory 194876 kb
Host smart-cd3ae3ca-1a78-4f53-beab-2017348fb483
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812493837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.2812493837
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.2533831349
Short name T580
Test name
Test status
Simulation time 44923972 ps
CPU time 0.87 seconds
Started Jul 02 07:38:04 AM PDT 24
Finished Jul 02 07:38:17 AM PDT 24
Peak memory 196540 kb
Host smart-fb85f17e-5c3e-4dff-8e0a-786fb97f39a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533831349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.2533831349
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1403504079
Short name T369
Test name
Test status
Simulation time 554106676 ps
CPU time 1.86 seconds
Started Jul 02 07:38:23 AM PDT 24
Finished Jul 02 07:38:44 AM PDT 24
Peak memory 198452 kb
Host smart-2332bbca-9567-44eb-b1c4-a13eeeca1860
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403504079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1403504079
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.820826500
Short name T556
Test name
Test status
Simulation time 84545177 ps
CPU time 2.32 seconds
Started Jul 02 07:38:15 AM PDT 24
Finished Jul 02 07:38:36 AM PDT 24
Peak memory 198564 kb
Host smart-b826fe36-1d46-46da-84c0-740e808c157b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820826500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
820826500
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.184607799
Short name T283
Test name
Test status
Simulation time 97203696 ps
CPU time 1.1 seconds
Started Jul 02 07:38:03 AM PDT 24
Finished Jul 02 07:38:15 AM PDT 24
Peak memory 196548 kb
Host smart-e39a54ca-8402-4631-bb75-c99536bd4358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184607799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.184607799
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.2239287872
Short name T465
Test name
Test status
Simulation time 240307084 ps
CPU time 1.27 seconds
Started Jul 02 07:38:15 AM PDT 24
Finished Jul 02 07:38:35 AM PDT 24
Peak memory 197352 kb
Host smart-f79d82b2-da35-4078-bb3f-0c65d03ce486
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239287872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.2239287872
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1641382204
Short name T238
Test name
Test status
Simulation time 45449723 ps
CPU time 1.86 seconds
Started Jul 02 07:38:11 AM PDT 24
Finished Jul 02 07:38:30 AM PDT 24
Peak memory 198424 kb
Host smart-574f68c9-7657-4242-97c1-8168bcaeca5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641382204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.1641382204
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.1118469258
Short name T601
Test name
Test status
Simulation time 408172952 ps
CPU time 1 seconds
Started Jul 02 07:38:08 AM PDT 24
Finished Jul 02 07:38:25 AM PDT 24
Peak memory 196268 kb
Host smart-15158c97-214a-4456-8024-2ca4c2080cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118469258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.1118469258
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.2272738375
Short name T201
Test name
Test status
Simulation time 104589802 ps
CPU time 1.45 seconds
Started Jul 02 07:38:11 AM PDT 24
Finished Jul 02 07:38:29 AM PDT 24
Peak memory 197268 kb
Host smart-afa7e593-8ced-4801-a2de-3925e1e401c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272738375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.2272738375
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.1551654857
Short name T586
Test name
Test status
Simulation time 5973703975 ps
CPU time 39.44 seconds
Started Jul 02 07:38:13 AM PDT 24
Finished Jul 02 07:39:10 AM PDT 24
Peak memory 198616 kb
Host smart-267fd6c1-317e-4504-a80b-9cc6537810a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551654857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.1551654857
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.388519863
Short name T11
Test name
Test status
Simulation time 57971929 ps
CPU time 0.59 seconds
Started Jul 02 07:37:55 AM PDT 24
Finished Jul 02 07:38:07 AM PDT 24
Peak memory 194472 kb
Host smart-f7e3a8c6-00c9-491e-b753-12f6f95ad40d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388519863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.388519863
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1510535787
Short name T197
Test name
Test status
Simulation time 18373612 ps
CPU time 0.68 seconds
Started Jul 02 07:38:13 AM PDT 24
Finished Jul 02 07:38:31 AM PDT 24
Peak memory 194624 kb
Host smart-a63336e3-1a01-4de2-9cdd-d49bc37c1eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510535787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1510535787
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2991000304
Short name T544
Test name
Test status
Simulation time 2016499303 ps
CPU time 25.09 seconds
Started Jul 02 07:38:17 AM PDT 24
Finished Jul 02 07:39:01 AM PDT 24
Peak memory 198380 kb
Host smart-c2804c39-2f8e-48f5-b097-8b92e2ace524
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991000304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2991000304
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.3892716435
Short name T5
Test name
Test status
Simulation time 240672186 ps
CPU time 0.82 seconds
Started Jul 02 07:38:03 AM PDT 24
Finished Jul 02 07:38:16 AM PDT 24
Peak memory 197260 kb
Host smart-e538b554-19bc-4c22-b8eb-73c489eb944e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892716435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.3892716435
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3694913046
Short name T517
Test name
Test status
Simulation time 36644533 ps
CPU time 0.73 seconds
Started Jul 02 07:38:23 AM PDT 24
Finished Jul 02 07:38:43 AM PDT 24
Peak memory 195864 kb
Host smart-65f3a0a3-3271-4753-af2d-e9061f444366
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694913046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3694913046
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.746899811
Short name T678
Test name
Test status
Simulation time 193847733 ps
CPU time 3.41 seconds
Started Jul 02 07:38:12 AM PDT 24
Finished Jul 02 07:38:33 AM PDT 24
Peak memory 198456 kb
Host smart-4278391b-56b0-4731-9213-f2823b04ac51
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746899811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.gpio_intr_with_filter_rand_intr_event.746899811
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1146828059
Short name T682
Test name
Test status
Simulation time 161276715 ps
CPU time 3.05 seconds
Started Jul 02 07:38:10 AM PDT 24
Finished Jul 02 07:38:29 AM PDT 24
Peak memory 197044 kb
Host smart-92069255-4f74-463a-aef5-6b6ade079ffd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146828059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1146828059
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.454496304
Short name T412
Test name
Test status
Simulation time 28380217 ps
CPU time 0.74 seconds
Started Jul 02 07:38:17 AM PDT 24
Finished Jul 02 07:38:37 AM PDT 24
Peak memory 195916 kb
Host smart-bc6f995c-4d54-4ccb-9b1b-456e4d58bea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454496304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.454496304
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.609123125
Short name T362
Test name
Test status
Simulation time 223107135 ps
CPU time 0.99 seconds
Started Jul 02 07:38:14 AM PDT 24
Finished Jul 02 07:38:33 AM PDT 24
Peak memory 197236 kb
Host smart-2b4a57fe-b1ac-4d7f-8608-8b0a1c550816
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609123125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.609123125
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2650853104
Short name T533
Test name
Test status
Simulation time 772641491 ps
CPU time 4.82 seconds
Started Jul 02 07:38:12 AM PDT 24
Finished Jul 02 07:38:35 AM PDT 24
Peak memory 198384 kb
Host smart-88f2ccc6-5147-4c37-b275-003abd665023
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650853104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.2650853104
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.537915355
Short name T207
Test name
Test status
Simulation time 39162635 ps
CPU time 0.83 seconds
Started Jul 02 07:38:18 AM PDT 24
Finished Jul 02 07:38:39 AM PDT 24
Peak memory 196548 kb
Host smart-e4b46d6e-afe4-4576-b990-a4c92cb4a5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537915355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.537915355
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.2774624771
Short name T346
Test name
Test status
Simulation time 71944818 ps
CPU time 1.04 seconds
Started Jul 02 07:38:11 AM PDT 24
Finished Jul 02 07:38:29 AM PDT 24
Peak memory 196972 kb
Host smart-c88f3012-ef97-49c2-9a93-32309ea2dab2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774624771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.2774624771
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.329512379
Short name T557
Test name
Test status
Simulation time 21441101431 ps
CPU time 113.2 seconds
Started Jul 02 07:38:09 AM PDT 24
Finished Jul 02 07:40:19 AM PDT 24
Peak memory 198588 kb
Host smart-da80aff8-3394-4c4e-9fe4-f2457864bd04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329512379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.g
pio_stress_all.329512379
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1916208501
Short name T551
Test name
Test status
Simulation time 160542648 ps
CPU time 0.58 seconds
Started Jul 02 07:38:04 AM PDT 24
Finished Jul 02 07:38:17 AM PDT 24
Peak memory 194664 kb
Host smart-776a8c2d-6927-43d5-b769-0fcaed928fff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916208501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1916208501
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.233539580
Short name T199
Test name
Test status
Simulation time 204097326 ps
CPU time 0.73 seconds
Started Jul 02 07:38:17 AM PDT 24
Finished Jul 02 07:38:36 AM PDT 24
Peak memory 196348 kb
Host smart-70f50db4-de16-4e18-ae50-d36da30ec5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233539580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.233539580
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.1778606082
Short name T627
Test name
Test status
Simulation time 3535906023 ps
CPU time 22.8 seconds
Started Jul 02 07:38:17 AM PDT 24
Finished Jul 02 07:38:59 AM PDT 24
Peak memory 196260 kb
Host smart-ee0b0d10-5102-4e7f-a407-cb86b147ea50
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778606082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.1778606082
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.979927754
Short name T6
Test name
Test status
Simulation time 79423598 ps
CPU time 0.9 seconds
Started Jul 02 07:38:12 AM PDT 24
Finished Jul 02 07:38:30 AM PDT 24
Peak memory 197200 kb
Host smart-93d0dfa4-6de0-4fb9-837c-4673050244bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979927754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.979927754
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.1817121109
Short name T154
Test name
Test status
Simulation time 176844829 ps
CPU time 0.86 seconds
Started Jul 02 07:38:17 AM PDT 24
Finished Jul 02 07:38:37 AM PDT 24
Peak memory 196312 kb
Host smart-7cd9e09c-3896-403b-a38c-f8db24dccc2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817121109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.1817121109
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.460252425
Short name T693
Test name
Test status
Simulation time 100254337 ps
CPU time 1.19 seconds
Started Jul 02 07:38:04 AM PDT 24
Finished Jul 02 07:38:18 AM PDT 24
Peak memory 198628 kb
Host smart-82927b13-1c27-4df8-8b6a-58bfe0bca61c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460252425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.gpio_intr_with_filter_rand_intr_event.460252425
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3706146434
Short name T146
Test name
Test status
Simulation time 38396952 ps
CPU time 0.93 seconds
Started Jul 02 07:38:11 AM PDT 24
Finished Jul 02 07:38:29 AM PDT 24
Peak memory 195936 kb
Host smart-2cbf6bec-7998-46bc-80e3-1caa0dc26a5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706146434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3706146434
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1550169268
Short name T452
Test name
Test status
Simulation time 112775982 ps
CPU time 0.82 seconds
Started Jul 02 07:38:20 AM PDT 24
Finished Jul 02 07:38:40 AM PDT 24
Peak memory 196992 kb
Host smart-cc55bb0e-b2c0-4a77-9f7e-fabc3dbd829c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550169268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1550169268
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.4136139902
Short name T259
Test name
Test status
Simulation time 160581725 ps
CPU time 1 seconds
Started Jul 02 07:38:13 AM PDT 24
Finished Jul 02 07:38:31 AM PDT 24
Peak memory 197252 kb
Host smart-6276dab4-6dd3-48f0-a5aa-32bf16b89cf1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136139902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.4136139902
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.4026989936
Short name T579
Test name
Test status
Simulation time 157325865 ps
CPU time 2.68 seconds
Started Jul 02 07:38:06 AM PDT 24
Finished Jul 02 07:38:24 AM PDT 24
Peak memory 198412 kb
Host smart-dfa763f4-c10a-4593-81fb-ff3d2f6823e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026989936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.4026989936
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3242952036
Short name T539
Test name
Test status
Simulation time 226948026 ps
CPU time 1.1 seconds
Started Jul 02 07:38:07 AM PDT 24
Finished Jul 02 07:38:23 AM PDT 24
Peak memory 196272 kb
Host smart-81122401-1df9-43a9-819f-05c0f5492bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242952036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3242952036
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1337254565
Short name T183
Test name
Test status
Simulation time 29995385 ps
CPU time 0.94 seconds
Started Jul 02 07:38:13 AM PDT 24
Finished Jul 02 07:38:33 AM PDT 24
Peak memory 196200 kb
Host smart-40923c2c-a09a-46dd-9817-649b4232b8da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337254565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1337254565
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.2844464832
Short name T182
Test name
Test status
Simulation time 10692402205 ps
CPU time 66.37 seconds
Started Jul 02 07:38:07 AM PDT 24
Finished Jul 02 07:39:28 AM PDT 24
Peak memory 198560 kb
Host smart-1dca9c08-11c2-4407-a6a7-2aabad894659
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844464832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.2844464832
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.1325933926
Short name T695
Test name
Test status
Simulation time 1094524120175 ps
CPU time 2105.96 seconds
Started Jul 02 07:38:10 AM PDT 24
Finished Jul 02 08:13:34 AM PDT 24
Peak memory 198744 kb
Host smart-fb23daa4-78b7-47ac-b66b-7baac3aba954
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1325933926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.1325933926
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.3934325245
Short name T649
Test name
Test status
Simulation time 27778631 ps
CPU time 0.57 seconds
Started Jul 02 07:38:23 AM PDT 24
Finished Jul 02 07:38:42 AM PDT 24
Peak memory 195392 kb
Host smart-f24714fd-5e6c-44cb-8b89-22353bf09ac1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934325245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3934325245
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.1674667743
Short name T211
Test name
Test status
Simulation time 19372209 ps
CPU time 0.7 seconds
Started Jul 02 07:38:13 AM PDT 24
Finished Jul 02 07:38:31 AM PDT 24
Peak memory 194952 kb
Host smart-16b3fa0d-4822-4b1f-a3c1-6feba092b5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674667743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.1674667743
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.4139186956
Short name T401
Test name
Test status
Simulation time 969637959 ps
CPU time 25.78 seconds
Started Jul 02 07:38:08 AM PDT 24
Finished Jul 02 07:38:49 AM PDT 24
Peak memory 197352 kb
Host smart-fbc5e66a-9a80-47dd-a383-febb8fe3fd41
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139186956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.4139186956
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.1655250650
Short name T314
Test name
Test status
Simulation time 246471307 ps
CPU time 0.89 seconds
Started Jul 02 07:38:10 AM PDT 24
Finished Jul 02 07:38:27 AM PDT 24
Peak memory 198152 kb
Host smart-7b852183-60b6-41e7-ab18-c8260144d5d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655250650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.1655250650
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.769238306
Short name T553
Test name
Test status
Simulation time 121360687 ps
CPU time 0.88 seconds
Started Jul 02 07:38:17 AM PDT 24
Finished Jul 02 07:38:37 AM PDT 24
Peak memory 197028 kb
Host smart-ad96265d-51a7-4f15-af01-50b88719dbc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769238306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.769238306
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.2284011516
Short name T523
Test name
Test status
Simulation time 77945968 ps
CPU time 1.54 seconds
Started Jul 02 07:38:09 AM PDT 24
Finished Jul 02 07:38:28 AM PDT 24
Peak memory 198572 kb
Host smart-38438324-db69-4d48-baf0-601a589712ed
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284011516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.2284011516
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2460047533
Short name T700
Test name
Test status
Simulation time 255041409 ps
CPU time 3.37 seconds
Started Jul 02 07:38:13 AM PDT 24
Finished Jul 02 07:38:33 AM PDT 24
Peak memory 196332 kb
Host smart-81bd860d-aeaf-4925-bd78-76b366399960
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460047533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2460047533
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2001626099
Short name T226
Test name
Test status
Simulation time 104430793 ps
CPU time 0.91 seconds
Started Jul 02 07:38:02 AM PDT 24
Finished Jul 02 07:38:14 AM PDT 24
Peak memory 196556 kb
Host smart-6796835e-c081-4359-9d2b-c345562e94ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001626099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2001626099
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3203454456
Short name T117
Test name
Test status
Simulation time 51370782 ps
CPU time 1.01 seconds
Started Jul 02 07:38:12 AM PDT 24
Finished Jul 02 07:38:30 AM PDT 24
Peak memory 196476 kb
Host smart-7340ea22-6990-4832-8773-2a60b4134545
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203454456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3203454456
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.4138905558
Short name T122
Test name
Test status
Simulation time 231000131 ps
CPU time 1.21 seconds
Started Jul 02 07:38:03 AM PDT 24
Finished Jul 02 07:38:15 AM PDT 24
Peak memory 197964 kb
Host smart-1dec5210-31fd-4c2e-98a6-84c6e6907884
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138905558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.4138905558
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2389318279
Short name T298
Test name
Test status
Simulation time 53336394 ps
CPU time 0.83 seconds
Started Jul 02 07:38:14 AM PDT 24
Finished Jul 02 07:38:33 AM PDT 24
Peak memory 196496 kb
Host smart-c8f0a0e5-88c6-4835-ba11-4ea5022219f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389318279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2389318279
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2756735234
Short name T709
Test name
Test status
Simulation time 261829478 ps
CPU time 1.18 seconds
Started Jul 02 07:38:17 AM PDT 24
Finished Jul 02 07:38:37 AM PDT 24
Peak memory 196088 kb
Host smart-11786c9a-ff86-412e-91d5-339a4a781148
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756735234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2756735234
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.1601048525
Short name T589
Test name
Test status
Simulation time 29532269480 ps
CPU time 175.94 seconds
Started Jul 02 07:38:14 AM PDT 24
Finished Jul 02 07:41:28 AM PDT 24
Peak memory 198640 kb
Host smart-125868ec-b108-489e-91cc-e6df915bd464
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601048525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.1601048525
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.3964835376
Short name T29
Test name
Test status
Simulation time 360273927244 ps
CPU time 1741.18 seconds
Started Jul 02 07:38:11 AM PDT 24
Finished Jul 02 08:07:29 AM PDT 24
Peak memory 198712 kb
Host smart-106a2d9c-e8a6-41d6-8951-05e869dea7f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3964835376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.3964835376
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3590238300
Short name T49
Test name
Test status
Simulation time 38762806 ps
CPU time 0.55 seconds
Started Jul 02 07:38:07 AM PDT 24
Finished Jul 02 07:38:24 AM PDT 24
Peak memory 194540 kb
Host smart-122a0982-f3e4-4ccf-aef4-d2d8e7c073df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590238300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3590238300
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.4079855352
Short name T237
Test name
Test status
Simulation time 24762389 ps
CPU time 0.66 seconds
Started Jul 02 07:38:03 AM PDT 24
Finished Jul 02 07:38:15 AM PDT 24
Peak memory 194524 kb
Host smart-7ce2b67c-7b36-43df-969b-695b77a25f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079855352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.4079855352
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.1301167826
Short name T223
Test name
Test status
Simulation time 3009659058 ps
CPU time 21.73 seconds
Started Jul 02 07:38:18 AM PDT 24
Finished Jul 02 07:39:00 AM PDT 24
Peak memory 197464 kb
Host smart-cda72cd1-34f1-41a1-92d9-a396482fcd28
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301167826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.1301167826
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.2465510718
Short name T424
Test name
Test status
Simulation time 65537533 ps
CPU time 0.86 seconds
Started Jul 02 07:38:13 AM PDT 24
Finished Jul 02 07:38:31 AM PDT 24
Peak memory 198260 kb
Host smart-27ccb703-78be-4698-8797-3ab35f8a9de4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465510718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.2465510718
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1904875681
Short name T407
Test name
Test status
Simulation time 84821649 ps
CPU time 1.12 seconds
Started Jul 02 07:38:16 AM PDT 24
Finished Jul 02 07:38:36 AM PDT 24
Peak memory 197200 kb
Host smart-fe065e97-8dd4-4304-ad3c-febf3bf81681
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904875681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1904875681
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.2303526403
Short name T466
Test name
Test status
Simulation time 55632457 ps
CPU time 1.17 seconds
Started Jul 02 07:38:12 AM PDT 24
Finished Jul 02 07:38:30 AM PDT 24
Peak memory 198228 kb
Host smart-826e6058-8f59-4a07-92ee-cbd1bdaf4ccc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303526403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.2303526403
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.3271450298
Short name T427
Test name
Test status
Simulation time 274016114 ps
CPU time 1.44 seconds
Started Jul 02 07:38:13 AM PDT 24
Finished Jul 02 07:38:31 AM PDT 24
Peak memory 196564 kb
Host smart-2f13e5be-db76-4293-84ef-aabdd9c0a571
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271450298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.3271450298
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.1472899860
Short name T184
Test name
Test status
Simulation time 72788992 ps
CPU time 1.26 seconds
Started Jul 02 07:38:12 AM PDT 24
Finished Jul 02 07:38:31 AM PDT 24
Peak memory 198472 kb
Host smart-92fc1712-fbd5-444e-8a5a-1ff56666ea08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472899860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.1472899860
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3859317678
Short name T53
Test name
Test status
Simulation time 107875485 ps
CPU time 0.65 seconds
Started Jul 02 07:38:04 AM PDT 24
Finished Jul 02 07:38:17 AM PDT 24
Peak memory 195452 kb
Host smart-d70e8cce-2c4e-4747-af7c-2aabdecabb2d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859317678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3859317678
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.273576090
Short name T417
Test name
Test status
Simulation time 74012224 ps
CPU time 1.48 seconds
Started Jul 02 07:38:17 AM PDT 24
Finished Jul 02 07:38:37 AM PDT 24
Peak memory 198400 kb
Host smart-a35f1a20-091b-45a2-9c81-f9a957122d25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273576090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ran
dom_long_reg_writes_reg_reads.273576090
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.1287095971
Short name T596
Test name
Test status
Simulation time 101325060 ps
CPU time 0.99 seconds
Started Jul 02 07:38:11 AM PDT 24
Finished Jul 02 07:38:29 AM PDT 24
Peak memory 196928 kb
Host smart-4f0a205d-e998-4b28-8a7b-8ec43ad758d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287095971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.1287095971
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.214637125
Short name T659
Test name
Test status
Simulation time 131411967 ps
CPU time 1.03 seconds
Started Jul 02 07:38:12 AM PDT 24
Finished Jul 02 07:38:30 AM PDT 24
Peak memory 196184 kb
Host smart-20455c63-b72c-4451-a99e-ad2e9c4fbf1e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214637125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.214637125
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.3953958003
Short name T714
Test name
Test status
Simulation time 49449294740 ps
CPU time 152.74 seconds
Started Jul 02 07:38:09 AM PDT 24
Finished Jul 02 07:40:58 AM PDT 24
Peak memory 198640 kb
Host smart-d76073c9-2f48-4f08-90d2-b23baf1fe49c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953958003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.3953958003
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.2606085768
Short name T710
Test name
Test status
Simulation time 43195277020 ps
CPU time 785.8 seconds
Started Jul 02 07:38:17 AM PDT 24
Finished Jul 02 07:51:42 AM PDT 24
Peak memory 198720 kb
Host smart-863820c6-75ad-441f-aabd-ceec44d51ef4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2606085768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.2606085768
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2819866803
Short name T327
Test name
Test status
Simulation time 48190628 ps
CPU time 0.61 seconds
Started Jul 02 07:38:32 AM PDT 24
Finished Jul 02 07:38:50 AM PDT 24
Peak memory 195132 kb
Host smart-749dea9b-054f-4860-b09e-f2bcb93bece6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819866803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2819866803
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.896750302
Short name T701
Test name
Test status
Simulation time 46382408 ps
CPU time 0.59 seconds
Started Jul 02 07:38:15 AM PDT 24
Finished Jul 02 07:38:33 AM PDT 24
Peak memory 194312 kb
Host smart-fe32eae6-15e9-4605-be2c-43c386abb2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896750302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.896750302
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.2926060343
Short name T310
Test name
Test status
Simulation time 462381358 ps
CPU time 11.96 seconds
Started Jul 02 07:38:27 AM PDT 24
Finished Jul 02 07:38:58 AM PDT 24
Peak memory 197560 kb
Host smart-cfa08df4-97da-4e86-9f69-07e250dffcfc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926060343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.2926060343
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.1283356752
Short name T333
Test name
Test status
Simulation time 82967860 ps
CPU time 0.98 seconds
Started Jul 02 07:38:13 AM PDT 24
Finished Jul 02 07:38:31 AM PDT 24
Peak memory 198380 kb
Host smart-d7f53e97-123b-45ef-a664-7e33130946a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283356752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.1283356752
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.3727150533
Short name T671
Test name
Test status
Simulation time 92395080 ps
CPU time 1.21 seconds
Started Jul 02 07:38:12 AM PDT 24
Finished Jul 02 07:38:30 AM PDT 24
Peak memory 197432 kb
Host smart-fd1d744a-946c-43d9-94aa-9f860af2e7cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727150533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.3727150533
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1744781789
Short name T233
Test name
Test status
Simulation time 142227728 ps
CPU time 1.44 seconds
Started Jul 02 07:38:15 AM PDT 24
Finished Jul 02 07:38:35 AM PDT 24
Peak memory 197288 kb
Host smart-73f1fcd4-0b5d-47f3-aa79-12791bfc0525
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744781789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1744781789
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.1481407672
Short name T359
Test name
Test status
Simulation time 422796564 ps
CPU time 2.76 seconds
Started Jul 02 07:38:35 AM PDT 24
Finished Jul 02 07:38:54 AM PDT 24
Peak memory 198500 kb
Host smart-805d3208-4462-4960-a719-a8a4514f050e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481407672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.1481407672
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.1900859044
Short name T708
Test name
Test status
Simulation time 372541439 ps
CPU time 0.86 seconds
Started Jul 02 07:38:17 AM PDT 24
Finished Jul 02 07:38:37 AM PDT 24
Peak memory 197024 kb
Host smart-d34dc502-23dd-4aeb-aaa1-a89a44a96883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900859044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1900859044
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2908817898
Short name T528
Test name
Test status
Simulation time 54326965 ps
CPU time 1.11 seconds
Started Jul 02 07:38:17 AM PDT 24
Finished Jul 02 07:38:37 AM PDT 24
Peak memory 197080 kb
Host smart-503eeb20-6ba5-4f49-9293-22cccfdf2fb2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908817898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2908817898
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.999299546
Short name T350
Test name
Test status
Simulation time 1042194416 ps
CPU time 5.37 seconds
Started Jul 02 07:38:20 AM PDT 24
Finished Jul 02 07:38:44 AM PDT 24
Peak memory 198400 kb
Host smart-09b0abc7-b5db-4601-ab04-3c8cec74cfd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999299546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ran
dom_long_reg_writes_reg_reads.999299546
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.848122821
Short name T209
Test name
Test status
Simulation time 56485933 ps
CPU time 0.95 seconds
Started Jul 02 07:38:17 AM PDT 24
Finished Jul 02 07:38:37 AM PDT 24
Peak memory 196132 kb
Host smart-f5bbf8fa-460d-4f0b-b11e-bcb8a5555d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848122821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.848122821
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2571405831
Short name T581
Test name
Test status
Simulation time 411708788 ps
CPU time 1.27 seconds
Started Jul 02 07:38:15 AM PDT 24
Finished Jul 02 07:38:34 AM PDT 24
Peak memory 197036 kb
Host smart-aa207a91-e02b-41e1-a065-df8680179f53
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571405831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2571405831
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2719284323
Short name T297
Test name
Test status
Simulation time 12077662770 ps
CPU time 173.62 seconds
Started Jul 02 07:38:22 AM PDT 24
Finished Jul 02 07:41:35 AM PDT 24
Peak memory 198620 kb
Host smart-8fff6cae-832e-4dda-a300-99bc2f086d1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719284323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2719284323
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.2119793525
Short name T643
Test name
Test status
Simulation time 35860246797 ps
CPU time 263.84 seconds
Started Jul 02 07:38:16 AM PDT 24
Finished Jul 02 07:42:58 AM PDT 24
Peak memory 198704 kb
Host smart-4ab8883f-bed4-46d9-9a00-84b105199453
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2119793525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.2119793525
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.2231138811
Short name T368
Test name
Test status
Simulation time 10937917 ps
CPU time 0.55 seconds
Started Jul 02 07:38:08 AM PDT 24
Finished Jul 02 07:38:24 AM PDT 24
Peak memory 194496 kb
Host smart-9b88bd2d-8e20-4bd2-affc-0c831a4235b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231138811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.2231138811
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.3222699987
Short name T306
Test name
Test status
Simulation time 23646047 ps
CPU time 0.65 seconds
Started Jul 02 07:38:17 AM PDT 24
Finished Jul 02 07:38:36 AM PDT 24
Peak memory 194556 kb
Host smart-0f7e5f86-db4a-41ee-af62-a6c74e5927c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222699987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.3222699987
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.1965900496
Short name T254
Test name
Test status
Simulation time 555089615 ps
CPU time 7.04 seconds
Started Jul 02 07:38:27 AM PDT 24
Finished Jul 02 07:38:53 AM PDT 24
Peak memory 197604 kb
Host smart-f5adeba3-4a10-42ba-9d7f-6915b32c79c9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965900496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.1965900496
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.4227028714
Short name T635
Test name
Test status
Simulation time 59206662 ps
CPU time 0.69 seconds
Started Jul 02 07:38:15 AM PDT 24
Finished Jul 02 07:38:34 AM PDT 24
Peak memory 195296 kb
Host smart-df40349e-0c9e-43ba-a45a-91c179c6fb89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227028714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.4227028714
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2854191362
Short name T691
Test name
Test status
Simulation time 127855912 ps
CPU time 0.84 seconds
Started Jul 02 07:38:26 AM PDT 24
Finished Jul 02 07:38:45 AM PDT 24
Peak memory 197612 kb
Host smart-7d7390f8-f498-4cc6-965f-f0179384d7ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854191362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2854191362
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.541465649
Short name T343
Test name
Test status
Simulation time 355061131 ps
CPU time 3.41 seconds
Started Jul 02 07:38:15 AM PDT 24
Finished Jul 02 07:38:36 AM PDT 24
Peak memory 198500 kb
Host smart-c8c7773f-e19f-49b4-be55-3a3a267f47f0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541465649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.gpio_intr_with_filter_rand_intr_event.541465649
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1966549505
Short name T294
Test name
Test status
Simulation time 339315194 ps
CPU time 2.32 seconds
Started Jul 02 07:38:15 AM PDT 24
Finished Jul 02 07:38:35 AM PDT 24
Peak memory 196936 kb
Host smart-3a7afc34-b777-4a37-8503-c30041a2c7a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966549505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1966549505
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1000190333
Short name T164
Test name
Test status
Simulation time 22669638 ps
CPU time 0.92 seconds
Started Jul 02 07:38:15 AM PDT 24
Finished Jul 02 07:38:35 AM PDT 24
Peak memory 196820 kb
Host smart-03eac5ee-06ed-4455-b4ca-a89165835dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000190333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1000190333
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.2215048242
Short name T173
Test name
Test status
Simulation time 27989550 ps
CPU time 1.02 seconds
Started Jul 02 07:38:15 AM PDT 24
Finished Jul 02 07:38:35 AM PDT 24
Peak memory 196608 kb
Host smart-171ec6a1-2844-4d3d-957f-bf3bf0f48e6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215048242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.2215048242
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.3289385771
Short name T144
Test name
Test status
Simulation time 1028019226 ps
CPU time 3.79 seconds
Started Jul 02 07:38:14 AM PDT 24
Finished Jul 02 07:38:36 AM PDT 24
Peak memory 198380 kb
Host smart-c8809774-c368-4809-ae2e-cff47e33ba2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289385771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.3289385771
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.3837174671
Short name T158
Test name
Test status
Simulation time 296410572 ps
CPU time 1.3 seconds
Started Jul 02 07:38:40 AM PDT 24
Finished Jul 02 07:38:57 AM PDT 24
Peak memory 197352 kb
Host smart-41ac9b94-5ed2-4a64-9c4b-4a40506cbecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837174671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.3837174671
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1467592779
Short name T230
Test name
Test status
Simulation time 270990678 ps
CPU time 1.14 seconds
Started Jul 02 07:38:14 AM PDT 24
Finished Jul 02 07:38:34 AM PDT 24
Peak memory 197596 kb
Host smart-28745fdd-b019-43a7-930a-1056789da7fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467592779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1467592779
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.1976588181
Short name T488
Test name
Test status
Simulation time 73126250598 ps
CPU time 199.15 seconds
Started Jul 02 07:38:34 AM PDT 24
Finished Jul 02 07:42:10 AM PDT 24
Peak memory 198536 kb
Host smart-d6b9d29b-0a27-47e3-bae8-4f8a6d34da59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976588181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.1976588181
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.1980375493
Short name T128
Test name
Test status
Simulation time 13793799 ps
CPU time 0.61 seconds
Started Jul 02 07:36:31 AM PDT 24
Finished Jul 02 07:36:38 AM PDT 24
Peak memory 193840 kb
Host smart-f03a9119-ab47-4634-b080-40708cd3072c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980375493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.1980375493
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.2006798596
Short name T293
Test name
Test status
Simulation time 18333753 ps
CPU time 0.62 seconds
Started Jul 02 07:37:17 AM PDT 24
Finished Jul 02 07:37:23 AM PDT 24
Peak memory 194508 kb
Host smart-21839173-e769-47f9-b5ed-d11c96e92f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006798596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.2006798596
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.3186554241
Short name T43
Test name
Test status
Simulation time 2796842535 ps
CPU time 10.65 seconds
Started Jul 02 07:36:37 AM PDT 24
Finished Jul 02 07:36:57 AM PDT 24
Peak memory 196844 kb
Host smart-52115eb0-370e-4fbf-8d0b-0fa45374a8c4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186554241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.3186554241
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.362358778
Short name T614
Test name
Test status
Simulation time 131649210 ps
CPU time 0.85 seconds
Started Jul 02 07:36:46 AM PDT 24
Finished Jul 02 07:36:53 AM PDT 24
Peak memory 196280 kb
Host smart-e8f7cc90-0808-4e83-b21e-21e867521ebb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362358778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.362358778
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2576381883
Short name T276
Test name
Test status
Simulation time 38373514 ps
CPU time 1.21 seconds
Started Jul 02 07:34:04 AM PDT 24
Finished Jul 02 07:34:06 AM PDT 24
Peak memory 196604 kb
Host smart-179a2b83-23b3-4716-8691-c71d51bb8c52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576381883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2576381883
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.3957881880
Short name T665
Test name
Test status
Simulation time 301785250 ps
CPU time 2.86 seconds
Started Jul 02 07:36:31 AM PDT 24
Finished Jul 02 07:36:40 AM PDT 24
Peak memory 198140 kb
Host smart-d63afd41-ef04-4a93-9b1e-7519d6582180
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957881880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.3957881880
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2689757420
Short name T496
Test name
Test status
Simulation time 100211943 ps
CPU time 2.5 seconds
Started Jul 02 07:35:15 AM PDT 24
Finished Jul 02 07:35:18 AM PDT 24
Peak memory 198580 kb
Host smart-827a5263-2cd5-477e-8c44-aee92d208f53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689757420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2689757420
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3824852881
Short name T337
Test name
Test status
Simulation time 132305615 ps
CPU time 0.76 seconds
Started Jul 02 07:37:27 AM PDT 24
Finished Jul 02 07:37:38 AM PDT 24
Peak memory 196428 kb
Host smart-cb51ff80-298d-4c36-a9d4-556a50c5a4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824852881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3824852881
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.690223263
Short name T593
Test name
Test status
Simulation time 228150124 ps
CPU time 1.32 seconds
Started Jul 02 07:36:33 AM PDT 24
Finished Jul 02 07:36:41 AM PDT 24
Peak memory 194552 kb
Host smart-1da7f78f-35e2-4cb9-8878-2800e3a45930
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690223263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup_
pulldown.690223263
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2077834250
Short name T642
Test name
Test status
Simulation time 130037559 ps
CPU time 4.94 seconds
Started Jul 02 07:37:17 AM PDT 24
Finished Jul 02 07:37:27 AM PDT 24
Peak memory 197640 kb
Host smart-82926060-7993-44dc-a809-f788af66d292
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077834250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.2077834250
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.3333923450
Short name T35
Test name
Test status
Simulation time 742788333 ps
CPU time 1.09 seconds
Started Jul 02 07:31:55 AM PDT 24
Finished Jul 02 07:31:57 AM PDT 24
Peak memory 215172 kb
Host smart-030a2c29-1c82-4918-861b-e46e59585cf0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333923450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.3333923450
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.3464012181
Short name T500
Test name
Test status
Simulation time 612640186 ps
CPU time 1.16 seconds
Started Jul 02 07:36:45 AM PDT 24
Finished Jul 02 07:36:53 AM PDT 24
Peak memory 196108 kb
Host smart-c899e20f-302d-434d-9fe2-780e9c417203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464012181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3464012181
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.530190207
Short name T140
Test name
Test status
Simulation time 68273121 ps
CPU time 1.22 seconds
Started Jul 02 07:36:33 AM PDT 24
Finished Jul 02 07:36:41 AM PDT 24
Peak memory 195464 kb
Host smart-ae1c1fb7-5d4d-4db9-8ccb-2675e894eedb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530190207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.530190207
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.1150850527
Short name T51
Test name
Test status
Simulation time 4992991276 ps
CPU time 59.34 seconds
Started Jul 02 07:37:19 AM PDT 24
Finished Jul 02 07:38:25 AM PDT 24
Peak memory 197840 kb
Host smart-de6349f3-b3ea-4d21-820b-3137c72eb157
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150850527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.1150850527
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.509331064
Short name T477
Test name
Test status
Simulation time 12449767 ps
CPU time 0.56 seconds
Started Jul 02 07:38:35 AM PDT 24
Finished Jul 02 07:38:52 AM PDT 24
Peak memory 194468 kb
Host smart-5a52eea9-2710-4ce7-a437-2e60934c4bd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509331064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.509331064
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1618957825
Short name T262
Test name
Test status
Simulation time 39888619 ps
CPU time 0.6 seconds
Started Jul 02 07:38:13 AM PDT 24
Finished Jul 02 07:38:31 AM PDT 24
Peak memory 194420 kb
Host smart-b48848af-24e2-42af-9ad8-51065773f2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618957825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1618957825
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.679868784
Short name T147
Test name
Test status
Simulation time 574007129 ps
CPU time 9.57 seconds
Started Jul 02 07:38:11 AM PDT 24
Finished Jul 02 07:38:38 AM PDT 24
Peak memory 197592 kb
Host smart-5fddc72c-2d74-4104-8189-f26fa30ab2f6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679868784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stres
s.679868784
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2018147910
Short name T221
Test name
Test status
Simulation time 54730203 ps
CPU time 0.82 seconds
Started Jul 02 07:38:29 AM PDT 24
Finished Jul 02 07:38:48 AM PDT 24
Peak memory 197160 kb
Host smart-65016eac-8e1e-4834-851a-0ebba705aab2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018147910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2018147910
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3824937381
Short name T444
Test name
Test status
Simulation time 49143096 ps
CPU time 0.84 seconds
Started Jul 02 07:38:15 AM PDT 24
Finished Jul 02 07:38:35 AM PDT 24
Peak memory 196980 kb
Host smart-31ad0695-6ab0-41ea-b7a8-c2883f80a57b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824937381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3824937381
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1964609843
Short name T261
Test name
Test status
Simulation time 28612168 ps
CPU time 1.16 seconds
Started Jul 02 07:38:12 AM PDT 24
Finished Jul 02 07:38:30 AM PDT 24
Peak memory 198084 kb
Host smart-31f7c53b-8918-4cd3-b0f1-6b5321403af8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964609843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1964609843
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.3519344593
Short name T118
Test name
Test status
Simulation time 98819907 ps
CPU time 1.08 seconds
Started Jul 02 07:38:13 AM PDT 24
Finished Jul 02 07:38:31 AM PDT 24
Peak memory 196108 kb
Host smart-c57b4539-23a3-4c6d-8b92-db4d65dfca72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519344593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.3519344593
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.4218949364
Short name T69
Test name
Test status
Simulation time 114595893 ps
CPU time 1.08 seconds
Started Jul 02 07:38:11 AM PDT 24
Finished Jul 02 07:38:29 AM PDT 24
Peak memory 197416 kb
Host smart-6b791163-3795-4cef-821e-4f457e58be62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218949364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.4218949364
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2294195749
Short name T438
Test name
Test status
Simulation time 65512236 ps
CPU time 1.23 seconds
Started Jul 02 07:38:21 AM PDT 24
Finished Jul 02 07:38:41 AM PDT 24
Peak memory 198508 kb
Host smart-95d3c79b-47e5-447b-a77c-0a49dc431269
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294195749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2294195749
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.669868319
Short name T383
Test name
Test status
Simulation time 414023519 ps
CPU time 4.48 seconds
Started Jul 02 07:38:13 AM PDT 24
Finished Jul 02 07:38:35 AM PDT 24
Peak memory 198592 kb
Host smart-d8c34999-aed7-4026-9150-697f383d1063
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669868319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ran
dom_long_reg_writes_reg_reads.669868319
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.2143040254
Short name T489
Test name
Test status
Simulation time 85270645 ps
CPU time 1.14 seconds
Started Jul 02 07:38:18 AM PDT 24
Finished Jul 02 07:38:39 AM PDT 24
Peak memory 197320 kb
Host smart-ad53448c-7749-42a0-9ce4-4001eeb976de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143040254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2143040254
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.2759823751
Short name T224
Test name
Test status
Simulation time 262519548 ps
CPU time 1.36 seconds
Started Jul 02 07:38:33 AM PDT 24
Finished Jul 02 07:38:53 AM PDT 24
Peak memory 198452 kb
Host smart-ba936816-f631-47f8-be81-60c6fd280291
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759823751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.2759823751
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.608715724
Short name T361
Test name
Test status
Simulation time 39007694872 ps
CPU time 91.72 seconds
Started Jul 02 07:38:12 AM PDT 24
Finished Jul 02 07:40:01 AM PDT 24
Peak memory 198584 kb
Host smart-a0861a0e-c304-4126-8578-c098654a650d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608715724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.g
pio_stress_all.608715724
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.2891334232
Short name T174
Test name
Test status
Simulation time 28670594 ps
CPU time 0.56 seconds
Started Jul 02 07:38:15 AM PDT 24
Finished Jul 02 07:38:33 AM PDT 24
Peak memory 195136 kb
Host smart-a9428068-1b88-4ade-9d22-ddf3b1c4cc57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891334232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.2891334232
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2365077274
Short name T524
Test name
Test status
Simulation time 198385644 ps
CPU time 0.9 seconds
Started Jul 02 07:38:16 AM PDT 24
Finished Jul 02 07:38:35 AM PDT 24
Peak memory 196436 kb
Host smart-f6c2e284-8f8d-4af5-819a-ffdbbd44c8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365077274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2365077274
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1583810819
Short name T503
Test name
Test status
Simulation time 396132717 ps
CPU time 14.2 seconds
Started Jul 02 07:38:17 AM PDT 24
Finished Jul 02 07:38:50 AM PDT 24
Peak memory 197404 kb
Host smart-d6e177aa-099c-4af2-8341-903e58ad0cf0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583810819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1583810819
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.2499896775
Short name T663
Test name
Test status
Simulation time 400745215 ps
CPU time 0.96 seconds
Started Jul 02 07:38:38 AM PDT 24
Finished Jul 02 07:38:54 AM PDT 24
Peak memory 196812 kb
Host smart-a110e283-8a68-4111-aad3-01c2112f8bda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499896775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.2499896775
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.1668790508
Short name T462
Test name
Test status
Simulation time 55950630 ps
CPU time 1.33 seconds
Started Jul 02 07:38:16 AM PDT 24
Finished Jul 02 07:38:36 AM PDT 24
Peak memory 198556 kb
Host smart-c8f0ae9d-4847-419d-9d9b-d99b91ab36de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668790508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.1668790508
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2639769771
Short name T513
Test name
Test status
Simulation time 62883400 ps
CPU time 2.23 seconds
Started Jul 02 07:38:25 AM PDT 24
Finished Jul 02 07:38:46 AM PDT 24
Peak memory 196788 kb
Host smart-2947443b-9260-48cf-b5df-cad165932dfa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639769771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2639769771
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.4032582887
Short name T241
Test name
Test status
Simulation time 76097659 ps
CPU time 1.47 seconds
Started Jul 02 07:38:13 AM PDT 24
Finished Jul 02 07:38:32 AM PDT 24
Peak memory 196460 kb
Host smart-e5db5be0-d420-4098-a572-0a321380918a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032582887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.4032582887
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.1768217643
Short name T456
Test name
Test status
Simulation time 93536190 ps
CPU time 0.91 seconds
Started Jul 02 07:38:36 AM PDT 24
Finished Jul 02 07:38:53 AM PDT 24
Peak memory 196464 kb
Host smart-a8e06e85-1e42-4d6c-9a3a-82e4bee1d251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768217643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.1768217643
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.1064388634
Short name T265
Test name
Test status
Simulation time 52916102 ps
CPU time 1.03 seconds
Started Jul 02 07:38:18 AM PDT 24
Finished Jul 02 07:38:37 AM PDT 24
Peak memory 196536 kb
Host smart-583398f4-734b-49af-ac29-f765e627b116
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064388634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.1064388634
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3406490807
Short name T630
Test name
Test status
Simulation time 612950823 ps
CPU time 2.28 seconds
Started Jul 02 07:38:33 AM PDT 24
Finished Jul 02 07:38:52 AM PDT 24
Peak memory 198436 kb
Host smart-f12d978f-75bb-4bfe-8a36-f5e5bf89b2b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406490807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3406490807
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.1136863164
Short name T269
Test name
Test status
Simulation time 43391966 ps
CPU time 0.95 seconds
Started Jul 02 07:38:46 AM PDT 24
Finished Jul 02 07:39:02 AM PDT 24
Peak memory 196184 kb
Host smart-d712f4b4-8f41-4cda-b0fb-eb2408f1de23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136863164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.1136863164
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.1740315593
Short name T181
Test name
Test status
Simulation time 186899547 ps
CPU time 0.98 seconds
Started Jul 02 07:38:15 AM PDT 24
Finished Jul 02 07:38:35 AM PDT 24
Peak memory 196724 kb
Host smart-09cd02d8-61ac-4da3-98be-7fa1a4d2a7f5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740315593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.1740315593
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.2435590252
Short name T355
Test name
Test status
Simulation time 8565707813 ps
CPU time 110.82 seconds
Started Jul 02 07:38:18 AM PDT 24
Finished Jul 02 07:40:29 AM PDT 24
Peak memory 198592 kb
Host smart-0b329dcf-7c3d-41b9-9158-8f97ffc052be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435590252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.2435590252
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3413196034
Short name T484
Test name
Test status
Simulation time 36960219 ps
CPU time 0.57 seconds
Started Jul 02 07:38:15 AM PDT 24
Finished Jul 02 07:38:35 AM PDT 24
Peak memory 194668 kb
Host smart-9621741b-9141-4aef-92ec-239d30400b95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413196034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3413196034
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2598377858
Short name T317
Test name
Test status
Simulation time 22941925 ps
CPU time 0.74 seconds
Started Jul 02 07:38:38 AM PDT 24
Finished Jul 02 07:38:54 AM PDT 24
Peak memory 194768 kb
Host smart-b4955902-5d2b-453c-9eb0-49c6e9b0368a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598377858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2598377858
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2753662495
Short name T679
Test name
Test status
Simulation time 3572889449 ps
CPU time 19.58 seconds
Started Jul 02 07:38:16 AM PDT 24
Finished Jul 02 07:38:54 AM PDT 24
Peak memory 198564 kb
Host smart-16da698b-44ab-416c-ad64-81aee825109b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753662495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2753662495
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.363686927
Short name T712
Test name
Test status
Simulation time 49765785 ps
CPU time 0.78 seconds
Started Jul 02 07:38:23 AM PDT 24
Finished Jul 02 07:38:43 AM PDT 24
Peak memory 196984 kb
Host smart-4d132621-74c0-49d4-b791-ecafd56eb850
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363686927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.363686927
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.939721332
Short name T641
Test name
Test status
Simulation time 76758586 ps
CPU time 1.3 seconds
Started Jul 02 07:38:47 AM PDT 24
Finished Jul 02 07:39:05 AM PDT 24
Peak memory 197616 kb
Host smart-d8139821-895c-459a-9e50-ae0479e590a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939721332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.939721332
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2981484419
Short name T284
Test name
Test status
Simulation time 63245375 ps
CPU time 1.36 seconds
Started Jul 02 07:38:15 AM PDT 24
Finished Jul 02 07:38:35 AM PDT 24
Peak memory 198360 kb
Host smart-1135ea7c-0e48-4be5-afd8-8cd8eb628294
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981484419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2981484419
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.3401880111
Short name T474
Test name
Test status
Simulation time 105384856 ps
CPU time 2.17 seconds
Started Jul 02 07:38:24 AM PDT 24
Finished Jul 02 07:38:45 AM PDT 24
Peak memory 196380 kb
Host smart-52094023-e232-405c-a329-91eda63d2c6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401880111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.3401880111
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.791820680
Short name T214
Test name
Test status
Simulation time 26784293 ps
CPU time 0.69 seconds
Started Jul 02 07:38:14 AM PDT 24
Finished Jul 02 07:38:33 AM PDT 24
Peak memory 195848 kb
Host smart-662f5a80-6529-4f0f-9c0c-482e3b36b59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791820680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.791820680
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1506183668
Short name T582
Test name
Test status
Simulation time 47795159 ps
CPU time 0.72 seconds
Started Jul 02 07:38:14 AM PDT 24
Finished Jul 02 07:38:34 AM PDT 24
Peak memory 196608 kb
Host smart-db080e91-6178-47ae-84f9-5bc00cefb845
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506183668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.1506183668
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2370738191
Short name T160
Test name
Test status
Simulation time 1248106706 ps
CPU time 5.65 seconds
Started Jul 02 07:38:44 AM PDT 24
Finished Jul 02 07:39:06 AM PDT 24
Peak memory 198468 kb
Host smart-8b62f57b-f6b3-45a0-8982-e59ce965b8c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370738191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2370738191
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2739014608
Short name T675
Test name
Test status
Simulation time 37862358 ps
CPU time 1.01 seconds
Started Jul 02 07:38:47 AM PDT 24
Finished Jul 02 07:39:04 AM PDT 24
Peak memory 196288 kb
Host smart-fbddf2ff-1217-4205-9cb1-9e07811dd9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739014608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2739014608
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3175266325
Short name T403
Test name
Test status
Simulation time 32848965 ps
CPU time 0.84 seconds
Started Jul 02 07:38:14 AM PDT 24
Finished Jul 02 07:38:33 AM PDT 24
Peak memory 196852 kb
Host smart-beb4eea8-a906-45a0-a3c6-c973a47bfa94
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175266325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3175266325
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.3825489109
Short name T9
Test name
Test status
Simulation time 57446080551 ps
CPU time 164.14 seconds
Started Jul 02 07:38:11 AM PDT 24
Finished Jul 02 07:41:12 AM PDT 24
Peak memory 198612 kb
Host smart-16729e01-860d-4e07-a9f1-8536bd97ae7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825489109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.3825489109
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.3202614404
Short name T413
Test name
Test status
Simulation time 39726531 ps
CPU time 0.54 seconds
Started Jul 02 07:38:16 AM PDT 24
Finished Jul 02 07:38:35 AM PDT 24
Peak memory 194436 kb
Host smart-45235224-bfd2-4602-ba97-f457fd52b4a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202614404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.3202614404
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2087417775
Short name T608
Test name
Test status
Simulation time 20696887 ps
CPU time 0.69 seconds
Started Jul 02 07:38:17 AM PDT 24
Finished Jul 02 07:38:37 AM PDT 24
Peak memory 195736 kb
Host smart-886be87f-fd87-429f-9eaa-71ef7d980dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087417775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2087417775
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3959225360
Short name T295
Test name
Test status
Simulation time 3350243179 ps
CPU time 19.78 seconds
Started Jul 02 07:38:19 AM PDT 24
Finished Jul 02 07:38:58 AM PDT 24
Peak memory 196372 kb
Host smart-d4f683e0-d7f1-43c5-99e0-f7824b3342f9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959225360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3959225360
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2106159232
Short name T378
Test name
Test status
Simulation time 55265300 ps
CPU time 0.76 seconds
Started Jul 02 07:38:14 AM PDT 24
Finished Jul 02 07:38:33 AM PDT 24
Peak memory 196428 kb
Host smart-c7e9db32-eaaf-4bbd-b614-ae30256d2519
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106159232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2106159232
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.745668867
Short name T104
Test name
Test status
Simulation time 114973614 ps
CPU time 0.87 seconds
Started Jul 02 07:38:14 AM PDT 24
Finished Jul 02 07:38:34 AM PDT 24
Peak memory 196520 kb
Host smart-f4854a5f-5b17-4d03-9d6c-55723ae11f91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745668867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.745668867
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.20119743
Short name T648
Test name
Test status
Simulation time 108503836 ps
CPU time 2.75 seconds
Started Jul 02 07:38:40 AM PDT 24
Finished Jul 02 07:38:58 AM PDT 24
Peak memory 196824 kb
Host smart-953aa2ae-fd56-43c1-9225-8c97c086f461
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20119743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 33.gpio_intr_with_filter_rand_intr_event.20119743
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3272409960
Short name T392
Test name
Test status
Simulation time 33921066 ps
CPU time 1.09 seconds
Started Jul 02 07:38:20 AM PDT 24
Finished Jul 02 07:38:40 AM PDT 24
Peak memory 197176 kb
Host smart-df266bde-971f-4ad3-ba89-145d71ab8ab9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272409960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3272409960
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.34897376
Short name T189
Test name
Test status
Simulation time 666985025 ps
CPU time 1.02 seconds
Started Jul 02 07:38:12 AM PDT 24
Finished Jul 02 07:38:30 AM PDT 24
Peak memory 196460 kb
Host smart-2523b80c-cf37-4416-9eca-94b9b97ae0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34897376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.34897376
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.623757856
Short name T110
Test name
Test status
Simulation time 54925447 ps
CPU time 1.13 seconds
Started Jul 02 07:38:20 AM PDT 24
Finished Jul 02 07:38:40 AM PDT 24
Peak memory 198480 kb
Host smart-59e11882-f8fc-4348-aa62-64f862867e6c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623757856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup
_pulldown.623757856
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1440263250
Short name T508
Test name
Test status
Simulation time 1082878481 ps
CPU time 4.49 seconds
Started Jul 02 07:38:14 AM PDT 24
Finished Jul 02 07:38:37 AM PDT 24
Peak memory 198484 kb
Host smart-945086fa-c4d8-459d-aecb-65d7cbf3b084
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440263250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1440263250
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.954251341
Short name T548
Test name
Test status
Simulation time 80983818 ps
CPU time 1.45 seconds
Started Jul 02 07:38:36 AM PDT 24
Finished Jul 02 07:38:53 AM PDT 24
Peak memory 198488 kb
Host smart-66bc1ff7-65a1-488f-964f-e870e4fa8c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954251341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.954251341
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3878155708
Short name T459
Test name
Test status
Simulation time 57546656 ps
CPU time 1.11 seconds
Started Jul 02 07:38:14 AM PDT 24
Finished Jul 02 07:38:34 AM PDT 24
Peak memory 196156 kb
Host smart-81cca9e6-f982-4f1c-a8a1-d3d23f799382
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878155708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.3878155708
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3959801112
Short name T363
Test name
Test status
Simulation time 8788784061 ps
CPU time 91.38 seconds
Started Jul 02 07:38:21 AM PDT 24
Finished Jul 02 07:40:17 AM PDT 24
Peak memory 198556 kb
Host smart-b161fea5-2ef5-4b5e-9937-d75dfa397e85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959801112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3959801112
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.3632009127
Short name T312
Test name
Test status
Simulation time 49211346 ps
CPU time 0.59 seconds
Started Jul 02 07:38:16 AM PDT 24
Finished Jul 02 07:38:35 AM PDT 24
Peak memory 194840 kb
Host smart-33e1aa09-354c-432e-9e21-011515de25dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632009127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3632009127
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.4294482927
Short name T191
Test name
Test status
Simulation time 135728405 ps
CPU time 0.75 seconds
Started Jul 02 07:38:14 AM PDT 24
Finished Jul 02 07:38:33 AM PDT 24
Peak memory 195740 kb
Host smart-fd71c4c2-c363-44de-8b7a-0d7332e48f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294482927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.4294482927
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.34007342
Short name T202
Test name
Test status
Simulation time 192747763 ps
CPU time 6.29 seconds
Started Jul 02 07:38:19 AM PDT 24
Finished Jul 02 07:38:45 AM PDT 24
Peak memory 197176 kb
Host smart-90e73654-cab9-4c22-8eca-5f7a867cc471
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34007342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stress
.34007342
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2294181564
Short name T423
Test name
Test status
Simulation time 46412602 ps
CPU time 0.62 seconds
Started Jul 02 07:38:14 AM PDT 24
Finished Jul 02 07:38:33 AM PDT 24
Peak memory 194896 kb
Host smart-5e142210-6435-4b49-8174-f53b357d54ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294181564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2294181564
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.44459788
Short name T120
Test name
Test status
Simulation time 57967827 ps
CPU time 1.06 seconds
Started Jul 02 07:38:19 AM PDT 24
Finished Jul 02 07:38:39 AM PDT 24
Peak memory 196516 kb
Host smart-35169940-ae26-4854-b94c-30c7504b2101
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44459788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.44459788
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.4157703965
Short name T654
Test name
Test status
Simulation time 331277076 ps
CPU time 2.71 seconds
Started Jul 02 07:38:21 AM PDT 24
Finished Jul 02 07:38:43 AM PDT 24
Peak memory 198540 kb
Host smart-6e37d963-ea7b-4298-b6b0-24dbf111d95f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157703965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.4157703965
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2122592208
Short name T609
Test name
Test status
Simulation time 453968718 ps
CPU time 3.18 seconds
Started Jul 02 07:38:16 AM PDT 24
Finished Jul 02 07:38:37 AM PDT 24
Peak memory 197880 kb
Host smart-da9984f4-621e-4662-a7f7-4469677b9f95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122592208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2122592208
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.1353100116
Short name T516
Test name
Test status
Simulation time 229583272 ps
CPU time 1.2 seconds
Started Jul 02 07:38:30 AM PDT 24
Finished Jul 02 07:38:50 AM PDT 24
Peak memory 196324 kb
Host smart-92ed4727-0c50-453c-ae1c-5c47d0c53557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353100116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1353100116
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.3153474007
Short name T592
Test name
Test status
Simulation time 33508370 ps
CPU time 0.88 seconds
Started Jul 02 07:38:35 AM PDT 24
Finished Jul 02 07:38:52 AM PDT 24
Peak memory 196456 kb
Host smart-e16df794-df06-4a5d-87bc-7c24420ff2f8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153474007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.3153474007
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.4128613268
Short name T7
Test name
Test status
Simulation time 573050014 ps
CPU time 5.15 seconds
Started Jul 02 07:38:56 AM PDT 24
Finished Jul 02 07:39:14 AM PDT 24
Peak memory 198480 kb
Host smart-110001a5-3b35-49fb-8e0d-a75c79a5b8cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128613268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.4128613268
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.1607584307
Short name T365
Test name
Test status
Simulation time 146209948 ps
CPU time 1.11 seconds
Started Jul 02 07:38:36 AM PDT 24
Finished Jul 02 07:38:53 AM PDT 24
Peak memory 196936 kb
Host smart-d41e2f3a-8dab-449b-9d01-058cd5b9f2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607584307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.1607584307
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.1057129773
Short name T149
Test name
Test status
Simulation time 56025456 ps
CPU time 1.06 seconds
Started Jul 02 07:38:43 AM PDT 24
Finished Jul 02 07:39:00 AM PDT 24
Peak memory 195984 kb
Host smart-05975311-8a0c-434f-8524-f985c7138d52
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057129773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.1057129773
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.330228036
Short name T137
Test name
Test status
Simulation time 13581273684 ps
CPU time 165.78 seconds
Started Jul 02 07:38:22 AM PDT 24
Finished Jul 02 07:41:27 AM PDT 24
Peak memory 198624 kb
Host smart-1d0c84e0-bbc8-4a86-9ce6-3513e6a75d7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330228036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.330228036
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1593027565
Short name T36
Test name
Test status
Simulation time 287091247 ps
CPU time 0.57 seconds
Started Jul 02 07:38:39 AM PDT 24
Finished Jul 02 07:38:55 AM PDT 24
Peak memory 194648 kb
Host smart-99717173-e021-4a6d-af11-1f46b7c861ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593027565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1593027565
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1493086850
Short name T656
Test name
Test status
Simulation time 36276842 ps
CPU time 0.71 seconds
Started Jul 02 07:38:40 AM PDT 24
Finished Jul 02 07:38:56 AM PDT 24
Peak memory 195740 kb
Host smart-b1bd288f-2d1b-48d7-bcb2-1fb43c6b1b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493086850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1493086850
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1869629548
Short name T583
Test name
Test status
Simulation time 1049112373 ps
CPU time 28.75 seconds
Started Jul 02 07:38:18 AM PDT 24
Finished Jul 02 07:39:07 AM PDT 24
Peak memory 195976 kb
Host smart-be80e655-8cd1-46fd-9e05-4c9ef3a5d96f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869629548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1869629548
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.567400938
Short name T564
Test name
Test status
Simulation time 36107639 ps
CPU time 0.64 seconds
Started Jul 02 07:38:27 AM PDT 24
Finished Jul 02 07:38:46 AM PDT 24
Peak memory 194940 kb
Host smart-81fa5dd5-9707-4bdc-a687-ab195da93b8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567400938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.567400938
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.459509199
Short name T463
Test name
Test status
Simulation time 102466568 ps
CPU time 0.94 seconds
Started Jul 02 07:38:50 AM PDT 24
Finished Jul 02 07:39:07 AM PDT 24
Peak memory 196972 kb
Host smart-5f96f162-153a-4587-a84d-9d3755310c75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459509199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.459509199
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1025795057
Short name T436
Test name
Test status
Simulation time 67453274 ps
CPU time 0.9 seconds
Started Jul 02 07:38:26 AM PDT 24
Finished Jul 02 07:38:45 AM PDT 24
Peak memory 197372 kb
Host smart-a6a410a4-917c-40d5-b5fe-46fc35f8ed34
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025795057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1025795057
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.4026705092
Short name T492
Test name
Test status
Simulation time 465535265 ps
CPU time 1.75 seconds
Started Jul 02 07:38:34 AM PDT 24
Finished Jul 02 07:38:53 AM PDT 24
Peak memory 196736 kb
Host smart-8fa36c23-ef68-4c9d-ace4-f106cda6473b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026705092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.4026705092
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.178523510
Short name T243
Test name
Test status
Simulation time 241281512 ps
CPU time 1.2 seconds
Started Jul 02 07:38:14 AM PDT 24
Finished Jul 02 07:38:34 AM PDT 24
Peak memory 196572 kb
Host smart-6903b947-6e0a-4fc6-99ab-20e8ec1b3051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178523510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.178523510
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2292317985
Short name T483
Test name
Test status
Simulation time 117792028 ps
CPU time 1.07 seconds
Started Jul 02 07:38:39 AM PDT 24
Finished Jul 02 07:38:56 AM PDT 24
Peak memory 196296 kb
Host smart-7b9ee460-10a6-4bb5-b21e-b693cbffde85
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292317985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.2292317985
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.2540162415
Short name T175
Test name
Test status
Simulation time 300746653 ps
CPU time 4.87 seconds
Started Jul 02 07:38:41 AM PDT 24
Finished Jul 02 07:39:01 AM PDT 24
Peak memory 198392 kb
Host smart-7f1c206b-7d1f-497c-9c8e-a55448a705e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540162415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.2540162415
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.1040252191
Short name T605
Test name
Test status
Simulation time 361556295 ps
CPU time 0.87 seconds
Started Jul 02 07:38:17 AM PDT 24
Finished Jul 02 07:38:37 AM PDT 24
Peak memory 195944 kb
Host smart-9015b9be-4bf2-4f30-a55d-33f314a4b2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040252191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.1040252191
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2825767825
Short name T389
Test name
Test status
Simulation time 27567279 ps
CPU time 0.8 seconds
Started Jul 02 07:38:40 AM PDT 24
Finished Jul 02 07:38:56 AM PDT 24
Peak memory 195772 kb
Host smart-8a95a460-b26b-4dfe-999e-e00b083134a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825767825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2825767825
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3806951140
Short name T172
Test name
Test status
Simulation time 32681419606 ps
CPU time 217.75 seconds
Started Jul 02 07:38:37 AM PDT 24
Finished Jul 02 07:42:31 AM PDT 24
Peak memory 198596 kb
Host smart-37ae5d90-530a-4c7d-bb8b-5255c8db995d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806951140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3806951140
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.3217265313
Short name T366
Test name
Test status
Simulation time 182571061 ps
CPU time 0.54 seconds
Started Jul 02 07:38:21 AM PDT 24
Finished Jul 02 07:38:41 AM PDT 24
Peak memory 194428 kb
Host smart-4dc66b69-2a65-4555-881f-8226c494334d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217265313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.3217265313
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.115888181
Short name T253
Test name
Test status
Simulation time 75549379 ps
CPU time 0.65 seconds
Started Jul 02 07:38:54 AM PDT 24
Finished Jul 02 07:39:08 AM PDT 24
Peak memory 194472 kb
Host smart-4c78c1e1-ed82-4aa4-8090-9c8a4ff62696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115888181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.115888181
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.180737755
Short name T257
Test name
Test status
Simulation time 1771074336 ps
CPU time 22 seconds
Started Jul 02 07:38:20 AM PDT 24
Finished Jul 02 07:39:01 AM PDT 24
Peak memory 197412 kb
Host smart-6a0abbb7-0eb7-4b7f-9a8a-8a2f31f24719
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180737755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stres
s.180737755
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3253016314
Short name T546
Test name
Test status
Simulation time 94244790 ps
CPU time 1.03 seconds
Started Jul 02 07:38:15 AM PDT 24
Finished Jul 02 07:38:35 AM PDT 24
Peak memory 196748 kb
Host smart-ee74bdc3-5823-4f9b-9af3-a7490566654c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253016314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3253016314
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.578894022
Short name T541
Test name
Test status
Simulation time 79777088 ps
CPU time 1.13 seconds
Started Jul 02 07:38:21 AM PDT 24
Finished Jul 02 07:38:42 AM PDT 24
Peak memory 196244 kb
Host smart-868aa3c8-e161-4497-b203-d43855fdacf6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578894022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.578894022
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.1552187402
Short name T587
Test name
Test status
Simulation time 144224562 ps
CPU time 1.34 seconds
Started Jul 02 07:38:41 AM PDT 24
Finished Jul 02 07:38:58 AM PDT 24
Peak memory 197140 kb
Host smart-60fac372-02d8-4324-ace0-c712728a5d6a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552187402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.1552187402
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.1676704483
Short name T545
Test name
Test status
Simulation time 733036979 ps
CPU time 0.94 seconds
Started Jul 02 07:38:24 AM PDT 24
Finished Jul 02 07:38:44 AM PDT 24
Peak memory 195880 kb
Host smart-9fdc8c0e-98c2-4587-9dca-320489223775
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676704483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.1676704483
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.366922290
Short name T607
Test name
Test status
Simulation time 107192102 ps
CPU time 0.84 seconds
Started Jul 02 07:38:34 AM PDT 24
Finished Jul 02 07:38:52 AM PDT 24
Peak memory 196968 kb
Host smart-cf18b69d-e441-469b-b23b-0a3f170fad71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366922290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.366922290
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2000894219
Short name T13
Test name
Test status
Simulation time 44400193 ps
CPU time 0.92 seconds
Started Jul 02 07:38:37 AM PDT 24
Finished Jul 02 07:38:53 AM PDT 24
Peak memory 196960 kb
Host smart-2833e988-f116-4750-b89d-29ef57afa93e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000894219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2000894219
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.3330934016
Short name T464
Test name
Test status
Simulation time 333840239 ps
CPU time 1.31 seconds
Started Jul 02 07:38:41 AM PDT 24
Finished Jul 02 07:39:00 AM PDT 24
Peak memory 198420 kb
Host smart-43ea7f6a-3dcc-4edf-9408-bd2041f40c14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330934016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.3330934016
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.2107630051
Short name T645
Test name
Test status
Simulation time 62599134 ps
CPU time 1.01 seconds
Started Jul 02 07:38:25 AM PDT 24
Finished Jul 02 07:38:44 AM PDT 24
Peak memory 196092 kb
Host smart-6ccfe003-6eea-46b5-b898-39cfc9548d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107630051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.2107630051
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.294159074
Short name T622
Test name
Test status
Simulation time 107998937 ps
CPU time 0.87 seconds
Started Jul 02 07:38:33 AM PDT 24
Finished Jul 02 07:38:51 AM PDT 24
Peak memory 195644 kb
Host smart-bb2b6f19-04df-48e8-aa9c-fa10a9220478
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294159074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.294159074
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.2483753567
Short name T338
Test name
Test status
Simulation time 47882908949 ps
CPU time 61.81 seconds
Started Jul 02 07:38:42 AM PDT 24
Finished Jul 02 07:39:59 AM PDT 24
Peak memory 198544 kb
Host smart-6eedb697-2231-4540-98f6-67774ff045cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483753567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.2483753567
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.1782234234
Short name T518
Test name
Test status
Simulation time 23161938037 ps
CPU time 595.54 seconds
Started Jul 02 07:38:56 AM PDT 24
Finished Jul 02 07:49:04 AM PDT 24
Peak memory 198744 kb
Host smart-762381c5-837d-4bb8-a8eb-346aabf8f811
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1782234234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.1782234234
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.498443126
Short name T156
Test name
Test status
Simulation time 59167426 ps
CPU time 0.55 seconds
Started Jul 02 07:38:23 AM PDT 24
Finished Jul 02 07:38:42 AM PDT 24
Peak memory 194468 kb
Host smart-3e564bcd-8d47-4896-a47b-98f5539ad9d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498443126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.498443126
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.2510876556
Short name T487
Test name
Test status
Simulation time 75668679 ps
CPU time 0.71 seconds
Started Jul 02 07:38:28 AM PDT 24
Finished Jul 02 07:38:47 AM PDT 24
Peak memory 195744 kb
Host smart-93c6f367-3f22-4294-8d31-2f6ed9cbb6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510876556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.2510876556
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.506694714
Short name T367
Test name
Test status
Simulation time 2248525997 ps
CPU time 16.03 seconds
Started Jul 02 07:38:41 AM PDT 24
Finished Jul 02 07:39:12 AM PDT 24
Peak memory 196032 kb
Host smart-d13dbc69-c046-4ea0-8c9d-23f4b8a83713
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506694714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.506694714
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3195820000
Short name T22
Test name
Test status
Simulation time 93757924 ps
CPU time 0.99 seconds
Started Jul 02 07:38:28 AM PDT 24
Finished Jul 02 07:38:47 AM PDT 24
Peak memory 196860 kb
Host smart-10f60be6-249a-457b-9ab7-0d87d9cb5e14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195820000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3195820000
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2070189006
Short name T504
Test name
Test status
Simulation time 31474373 ps
CPU time 0.71 seconds
Started Jul 02 07:38:14 AM PDT 24
Finished Jul 02 07:38:33 AM PDT 24
Peak memory 195752 kb
Host smart-78184525-fc9f-41cf-a0f9-80d644e4fdf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070189006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2070189006
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1702999585
Short name T102
Test name
Test status
Simulation time 36763966 ps
CPU time 0.89 seconds
Started Jul 02 07:38:40 AM PDT 24
Finished Jul 02 07:38:56 AM PDT 24
Peak memory 197108 kb
Host smart-dad8cba8-3580-4042-bcfd-69cb1f8b3de0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702999585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1702999585
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.682533941
Short name T364
Test name
Test status
Simulation time 145937291 ps
CPU time 1.62 seconds
Started Jul 02 07:38:33 AM PDT 24
Finished Jul 02 07:38:52 AM PDT 24
Peak memory 196624 kb
Host smart-7b23fdb1-3570-4623-a18c-cad8ac019b73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682533941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.
682533941
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.65878193
Short name T493
Test name
Test status
Simulation time 74821333 ps
CPU time 1.34 seconds
Started Jul 02 07:38:14 AM PDT 24
Finished Jul 02 07:38:34 AM PDT 24
Peak memory 198496 kb
Host smart-670495ae-44c2-4dc3-a98e-2ae68b768ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65878193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.65878193
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3548538375
Short name T505
Test name
Test status
Simulation time 52321215 ps
CPU time 0.82 seconds
Started Jul 02 07:38:27 AM PDT 24
Finished Jul 02 07:38:47 AM PDT 24
Peak memory 196932 kb
Host smart-91df1e91-ef45-4f75-8d5f-5120d9349f40
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548538375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3548538375
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3154084042
Short name T677
Test name
Test status
Simulation time 417109803 ps
CPU time 1.29 seconds
Started Jul 02 07:38:20 AM PDT 24
Finished Jul 02 07:38:41 AM PDT 24
Peak memory 198348 kb
Host smart-5faf410e-918f-4acd-b865-fff0cdaefba5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154084042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3154084042
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.4240662522
Short name T141
Test name
Test status
Simulation time 66231479 ps
CPU time 1.26 seconds
Started Jul 02 07:38:36 AM PDT 24
Finished Jul 02 07:38:53 AM PDT 24
Peak memory 196092 kb
Host smart-b370f236-7b53-4ca1-a52d-1cc48d7d17ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240662522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.4240662522
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.2241416303
Short name T246
Test name
Test status
Simulation time 138239788 ps
CPU time 1.33 seconds
Started Jul 02 07:38:23 AM PDT 24
Finished Jul 02 07:38:43 AM PDT 24
Peak memory 197248 kb
Host smart-31f627a6-9963-434c-bda0-2c4e01b196cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241416303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.2241416303
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.2175218801
Short name T457
Test name
Test status
Simulation time 31954381809 ps
CPU time 69.75 seconds
Started Jul 02 07:39:12 AM PDT 24
Finished Jul 02 07:40:26 AM PDT 24
Peak memory 198596 kb
Host smart-c65c99ec-3759-428e-a154-0d5588e67b84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175218801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.2175218801
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2522782639
Short name T24
Test name
Test status
Simulation time 14601898 ps
CPU time 0.58 seconds
Started Jul 02 07:38:45 AM PDT 24
Finished Jul 02 07:39:01 AM PDT 24
Peak memory 194428 kb
Host smart-3cae2823-f426-4f9a-9fff-bedc4afb9b09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522782639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2522782639
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.1136921189
Short name T358
Test name
Test status
Simulation time 53045972 ps
CPU time 0.81 seconds
Started Jul 02 07:38:40 AM PDT 24
Finished Jul 02 07:38:56 AM PDT 24
Peak memory 195708 kb
Host smart-4703c6d6-7a61-44c8-816b-424992010662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136921189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.1136921189
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.4048726397
Short name T291
Test name
Test status
Simulation time 975959770 ps
CPU time 13.79 seconds
Started Jul 02 07:38:13 AM PDT 24
Finished Jul 02 07:38:44 AM PDT 24
Peak memory 195980 kb
Host smart-7f5bcd81-2953-4d69-8629-79aa08cf3b1e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048726397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.4048726397
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3792767439
Short name T352
Test name
Test status
Simulation time 531998665 ps
CPU time 1.04 seconds
Started Jul 02 07:38:34 AM PDT 24
Finished Jul 02 07:38:52 AM PDT 24
Peak memory 197096 kb
Host smart-5f245e75-e295-4d36-89db-01e06112b5f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792767439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3792767439
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2472567330
Short name T552
Test name
Test status
Simulation time 50153043 ps
CPU time 0.82 seconds
Started Jul 02 07:38:30 AM PDT 24
Finished Jul 02 07:38:49 AM PDT 24
Peak memory 196912 kb
Host smart-8e8a83b9-6513-4a72-81e2-eef79a93d105
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472567330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2472567330
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.3269570565
Short name T273
Test name
Test status
Simulation time 68219456 ps
CPU time 1.3 seconds
Started Jul 02 07:38:35 AM PDT 24
Finished Jul 02 07:38:53 AM PDT 24
Peak memory 196884 kb
Host smart-74aea67f-e3e4-4325-93f8-904e62706651
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269570565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.3269570565
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2988683714
Short name T467
Test name
Test status
Simulation time 953348475 ps
CPU time 3.04 seconds
Started Jul 02 07:38:15 AM PDT 24
Finished Jul 02 07:38:37 AM PDT 24
Peak memory 197716 kb
Host smart-f13a5beb-a940-4015-a427-4e6ad4f6200c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988683714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2988683714
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.1482939699
Short name T666
Test name
Test status
Simulation time 47094100 ps
CPU time 0.92 seconds
Started Jul 02 07:38:40 AM PDT 24
Finished Jul 02 07:38:56 AM PDT 24
Peak memory 196468 kb
Host smart-2b3df080-ffe7-4bbd-9b68-cddf09e4ee5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482939699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.1482939699
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.193468701
Short name T115
Test name
Test status
Simulation time 242055396 ps
CPU time 1.27 seconds
Started Jul 02 07:38:19 AM PDT 24
Finished Jul 02 07:38:40 AM PDT 24
Peak memory 197420 kb
Host smart-d5225b3a-2951-49fe-9f5f-6de749640820
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193468701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup
_pulldown.193468701
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.515326373
Short name T222
Test name
Test status
Simulation time 58433932 ps
CPU time 2.56 seconds
Started Jul 02 07:38:25 AM PDT 24
Finished Jul 02 07:38:49 AM PDT 24
Peak memory 198420 kb
Host smart-e3b7f7c6-1acf-4b5d-8195-8697d3c343e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515326373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ran
dom_long_reg_writes_reg_reads.515326373
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3232249564
Short name T625
Test name
Test status
Simulation time 32564443 ps
CPU time 0.94 seconds
Started Jul 02 07:38:14 AM PDT 24
Finished Jul 02 07:38:34 AM PDT 24
Peak memory 196904 kb
Host smart-6a392789-8f20-411d-abdf-60fd49dff43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232249564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3232249564
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3854784319
Short name T302
Test name
Test status
Simulation time 61000660 ps
CPU time 1.12 seconds
Started Jul 02 07:38:24 AM PDT 24
Finished Jul 02 07:38:44 AM PDT 24
Peak memory 196984 kb
Host smart-1e8a3dfc-a213-492f-865f-595d0c1afe2e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854784319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3854784319
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.4155075932
Short name T381
Test name
Test status
Simulation time 18726463470 ps
CPU time 107 seconds
Started Jul 02 07:38:47 AM PDT 24
Finished Jul 02 07:40:49 AM PDT 24
Peak memory 198536 kb
Host smart-37bb57d8-a3f9-4c3c-80f8-3a7acdb8ed3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155075932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.4155075932
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.555224285
Short name T60
Test name
Test status
Simulation time 101096747743 ps
CPU time 271.17 seconds
Started Jul 02 07:38:41 AM PDT 24
Finished Jul 02 07:43:28 AM PDT 24
Peak memory 198708 kb
Host smart-a1ca5021-2a77-493d-b066-2116a7ee8efd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=555224285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.555224285
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.3362741004
Short name T303
Test name
Test status
Simulation time 11104812 ps
CPU time 0.55 seconds
Started Jul 02 07:38:20 AM PDT 24
Finished Jul 02 07:38:40 AM PDT 24
Peak memory 194456 kb
Host smart-175e9923-7b5b-4827-a3e9-af6a62d3199b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362741004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.3362741004
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.4167021779
Short name T316
Test name
Test status
Simulation time 160529968 ps
CPU time 0.94 seconds
Started Jul 02 07:38:54 AM PDT 24
Finished Jul 02 07:39:09 AM PDT 24
Peak memory 197560 kb
Host smart-28361141-f623-4b12-afe6-02e0bc8a618b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167021779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.4167021779
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1953831753
Short name T393
Test name
Test status
Simulation time 1387088265 ps
CPU time 17.24 seconds
Started Jul 02 07:38:40 AM PDT 24
Finished Jul 02 07:39:12 AM PDT 24
Peak memory 198524 kb
Host smart-154a4ccc-bbdf-4dc4-88dd-18318ffc20f4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953831753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1953831753
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2602654615
Short name T520
Test name
Test status
Simulation time 743633614 ps
CPU time 0.73 seconds
Started Jul 02 07:39:13 AM PDT 24
Finished Jul 02 07:39:18 AM PDT 24
Peak memory 196196 kb
Host smart-f775c924-086a-4ced-8a9f-245b330715b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602654615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2602654615
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.4174155698
Short name T485
Test name
Test status
Simulation time 146038129 ps
CPU time 1.39 seconds
Started Jul 02 07:39:00 AM PDT 24
Finished Jul 02 07:39:13 AM PDT 24
Peak memory 196304 kb
Host smart-c1098aa2-f80b-4e6e-be07-8024c957f419
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174155698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.4174155698
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.3695629199
Short name T227
Test name
Test status
Simulation time 61643948 ps
CPU time 2.33 seconds
Started Jul 02 07:38:46 AM PDT 24
Finished Jul 02 07:39:04 AM PDT 24
Peak memory 198468 kb
Host smart-0d5a285d-eb26-4ad5-9f55-aba96499b1c2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695629199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.3695629199
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.715008526
Short name T615
Test name
Test status
Simulation time 52564365 ps
CPU time 1.35 seconds
Started Jul 02 07:38:29 AM PDT 24
Finished Jul 02 07:38:48 AM PDT 24
Peak memory 196588 kb
Host smart-37ebe800-7d12-4504-bb85-21ff80a17ce7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715008526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
715008526
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.3353655278
Short name T522
Test name
Test status
Simulation time 33598851 ps
CPU time 0.75 seconds
Started Jul 02 07:38:21 AM PDT 24
Finished Jul 02 07:38:41 AM PDT 24
Peak memory 196540 kb
Host smart-54e9387c-8349-40eb-ab3d-2ef6b579f72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353655278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3353655278
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2382126414
Short name T196
Test name
Test status
Simulation time 138612100 ps
CPU time 1.23 seconds
Started Jul 02 07:38:55 AM PDT 24
Finished Jul 02 07:39:10 AM PDT 24
Peak memory 196312 kb
Host smart-70b512e3-9479-4e58-bb88-d3becf433381
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382126414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2382126414
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2492960254
Short name T410
Test name
Test status
Simulation time 184173841 ps
CPU time 2.14 seconds
Started Jul 02 07:38:43 AM PDT 24
Finished Jul 02 07:39:01 AM PDT 24
Peak memory 198408 kb
Host smart-ccf4c948-4b70-4cf0-8017-725eec374aa5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492960254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2492960254
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.2851419748
Short name T203
Test name
Test status
Simulation time 47562659 ps
CPU time 1.24 seconds
Started Jul 02 07:39:04 AM PDT 24
Finished Jul 02 07:39:14 AM PDT 24
Peak memory 198496 kb
Host smart-1462849c-a567-4293-8b8a-7e0cba68b1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851419748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.2851419748
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.2274899611
Short name T150
Test name
Test status
Simulation time 85620880 ps
CPU time 0.98 seconds
Started Jul 02 07:38:44 AM PDT 24
Finished Jul 02 07:39:01 AM PDT 24
Peak memory 196260 kb
Host smart-a93975ea-c6bf-4ec1-afd0-74647f10796a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274899611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.2274899611
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.2031449805
Short name T354
Test name
Test status
Simulation time 17268872570 ps
CPU time 165.14 seconds
Started Jul 02 07:38:40 AM PDT 24
Finished Jul 02 07:41:40 AM PDT 24
Peak memory 198580 kb
Host smart-56cad491-be90-4a13-ab04-46812ef3dfee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031449805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.2031449805
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.4230531621
Short name T68
Test name
Test status
Simulation time 15645838 ps
CPU time 0.55 seconds
Started Jul 02 07:37:34 AM PDT 24
Finished Jul 02 07:37:46 AM PDT 24
Peak memory 194396 kb
Host smart-610840da-9d4c-4557-addd-2c99d964c521
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230531621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.4230531621
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1137678360
Short name T193
Test name
Test status
Simulation time 242390607 ps
CPU time 0.88 seconds
Started Jul 02 07:34:31 AM PDT 24
Finished Jul 02 07:34:33 AM PDT 24
Peak memory 194964 kb
Host smart-11b357f8-a59a-4ab8-8b65-724455b80ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137678360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1137678360
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.645159111
Short name T667
Test name
Test status
Simulation time 4493367782 ps
CPU time 20.81 seconds
Started Jul 02 07:37:32 AM PDT 24
Finished Jul 02 07:38:03 AM PDT 24
Peak memory 197080 kb
Host smart-9ebbd002-97e1-4f0b-bdef-1d690b991065
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645159111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stress
.645159111
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.432367612
Short name T416
Test name
Test status
Simulation time 65639603 ps
CPU time 1.01 seconds
Started Jul 02 07:37:18 AM PDT 24
Finished Jul 02 07:37:25 AM PDT 24
Peak memory 197140 kb
Host smart-8689cbc5-9ffa-4b82-a038-a91111ff93a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432367612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.432367612
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.1018555304
Short name T555
Test name
Test status
Simulation time 32792396 ps
CPU time 0.99 seconds
Started Jul 02 07:37:17 AM PDT 24
Finished Jul 02 07:37:24 AM PDT 24
Peak memory 196020 kb
Host smart-68da5861-71a0-4205-93a2-614bc6709fa8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018555304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1018555304
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1902421660
Short name T274
Test name
Test status
Simulation time 86906941 ps
CPU time 2.61 seconds
Started Jul 02 07:37:25 AM PDT 24
Finished Jul 02 07:37:35 AM PDT 24
Peak memory 198528 kb
Host smart-1756a10e-b593-476e-949d-20f6801ace95
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902421660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1902421660
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.4076843914
Short name T482
Test name
Test status
Simulation time 696779466 ps
CPU time 2.6 seconds
Started Jul 02 07:37:43 AM PDT 24
Finished Jul 02 07:37:57 AM PDT 24
Peak memory 198552 kb
Host smart-5b8c72ab-18c5-443a-aaea-a5a258c08ca7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076843914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
4076843914
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.2701912811
Short name T647
Test name
Test status
Simulation time 23640580 ps
CPU time 0.72 seconds
Started Jul 02 07:36:40 AM PDT 24
Finished Jul 02 07:36:48 AM PDT 24
Peak memory 195436 kb
Host smart-0782a6c2-20de-459a-830c-494c35b14d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701912811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.2701912811
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.1945472164
Short name T264
Test name
Test status
Simulation time 37107423 ps
CPU time 0.64 seconds
Started Jul 02 07:37:27 AM PDT 24
Finished Jul 02 07:37:36 AM PDT 24
Peak memory 194620 kb
Host smart-6032d63b-59b8-4dfb-b42a-881cbbfa995e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945472164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.1945472164
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1735683192
Short name T19
Test name
Test status
Simulation time 3386593940 ps
CPU time 6.54 seconds
Started Jul 02 07:37:13 AM PDT 24
Finished Jul 02 07:37:24 AM PDT 24
Peak memory 198516 kb
Host smart-154f102f-4ec0-403c-a5e7-825dd9bc9daf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735683192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1735683192
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3700329119
Short name T44
Test name
Test status
Simulation time 358921674 ps
CPU time 0.76 seconds
Started Jul 02 07:37:42 AM PDT 24
Finished Jul 02 07:37:54 AM PDT 24
Peak memory 214024 kb
Host smart-d7eed320-de21-492b-a452-142356d560d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700329119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3700329119
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.2629984500
Short name T439
Test name
Test status
Simulation time 53947501 ps
CPU time 1.02 seconds
Started Jul 02 07:37:28 AM PDT 24
Finished Jul 02 07:37:38 AM PDT 24
Peak memory 196804 kb
Host smart-4739a76b-d22c-4318-8ed7-e83d107df370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629984500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2629984500
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.2504623276
Short name T572
Test name
Test status
Simulation time 36103376 ps
CPU time 0.91 seconds
Started Jul 02 07:37:28 AM PDT 24
Finished Jul 02 07:37:38 AM PDT 24
Peak memory 196060 kb
Host smart-a3bba898-8b25-4a2f-bdc4-8a7de95d2a6d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504623276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.2504623276
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.2475519588
Short name T15
Test name
Test status
Simulation time 6534942429 ps
CPU time 86.96 seconds
Started Jul 02 07:37:30 AM PDT 24
Finished Jul 02 07:39:06 AM PDT 24
Peak memory 198616 kb
Host smart-e58433d2-bc99-4cbf-a369-8327c0478b21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475519588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.2475519588
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.818982605
Short name T56
Test name
Test status
Simulation time 278701409060 ps
CPU time 1602.69 seconds
Started Jul 02 07:37:30 AM PDT 24
Finished Jul 02 08:04:22 AM PDT 24
Peak memory 206872 kb
Host smart-04ed1aca-0f2a-45cd-b9c1-8e2b25249949
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=818982605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.818982605
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.1167476743
Short name T286
Test name
Test status
Simulation time 44958123 ps
CPU time 0.56 seconds
Started Jul 02 07:38:43 AM PDT 24
Finished Jul 02 07:39:00 AM PDT 24
Peak memory 194448 kb
Host smart-89c4fb30-7ce1-4296-a48f-44555b81ea82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167476743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.1167476743
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1086958806
Short name T342
Test name
Test status
Simulation time 96632882 ps
CPU time 0.81 seconds
Started Jul 02 07:38:26 AM PDT 24
Finished Jul 02 07:38:45 AM PDT 24
Peak memory 196368 kb
Host smart-0965f82d-26e6-44d3-89d7-2ef6ac9d6c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086958806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1086958806
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.4235955081
Short name T142
Test name
Test status
Simulation time 497971540 ps
CPU time 13.61 seconds
Started Jul 02 07:38:44 AM PDT 24
Finished Jul 02 07:39:14 AM PDT 24
Peak memory 195972 kb
Host smart-46ec36ac-1449-44cf-aa8b-a3512c2fa7fd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235955081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.4235955081
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.325847929
Short name T653
Test name
Test status
Simulation time 203779368 ps
CPU time 0.87 seconds
Started Jul 02 07:38:51 AM PDT 24
Finished Jul 02 07:39:07 AM PDT 24
Peak memory 197488 kb
Host smart-1b232d7c-1d24-48c8-b14e-2ca750663e8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325847929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.325847929
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1457682925
Short name T304
Test name
Test status
Simulation time 271594010 ps
CPU time 1.05 seconds
Started Jul 02 07:38:42 AM PDT 24
Finished Jul 02 07:38:58 AM PDT 24
Peak memory 196420 kb
Host smart-f41bd423-bae0-4843-b41f-df20f28c78af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457682925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1457682925
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.559905437
Short name T687
Test name
Test status
Simulation time 360916664 ps
CPU time 1.07 seconds
Started Jul 02 07:38:47 AM PDT 24
Finished Jul 02 07:39:03 AM PDT 24
Peak memory 196876 kb
Host smart-057a1791-74b7-4c58-b377-6ccf0033060c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559905437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.559905437
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2523477924
Short name T344
Test name
Test status
Simulation time 34369440 ps
CPU time 0.88 seconds
Started Jul 02 07:38:49 AM PDT 24
Finished Jul 02 07:39:05 AM PDT 24
Peak memory 195936 kb
Host smart-2f64b074-82ed-4c98-8dc9-d5ea3a15149e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523477924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2523477924
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.3767261651
Short name T497
Test name
Test status
Simulation time 278670436 ps
CPU time 1.22 seconds
Started Jul 02 07:38:55 AM PDT 24
Finished Jul 02 07:39:10 AM PDT 24
Peak memory 198528 kb
Host smart-babc7388-0916-41d7-aaa7-18cd5952c8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767261651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.3767261651
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.4046980977
Short name T433
Test name
Test status
Simulation time 75514559 ps
CPU time 0.88 seconds
Started Jul 02 07:38:42 AM PDT 24
Finished Jul 02 07:38:58 AM PDT 24
Peak memory 196420 kb
Host smart-bf4094fa-925f-419d-a86e-db14342b2859
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046980977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.4046980977
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_smoke.3632052991
Short name T177
Test name
Test status
Simulation time 813199435 ps
CPU time 1.13 seconds
Started Jul 02 07:38:27 AM PDT 24
Finished Jul 02 07:38:47 AM PDT 24
Peak memory 196064 kb
Host smart-e0c40367-a92b-497b-afa3-0aff05e7ecbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632052991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.3632052991
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2421500881
Short name T17
Test name
Test status
Simulation time 119945573 ps
CPU time 1.11 seconds
Started Jul 02 07:38:34 AM PDT 24
Finished Jul 02 07:38:52 AM PDT 24
Peak memory 196780 kb
Host smart-8eb88f07-f19e-4d86-9f2b-8d9372377f71
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421500881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2421500881
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.2654522182
Short name T8
Test name
Test status
Simulation time 8669116607 ps
CPU time 101.46 seconds
Started Jul 02 07:38:37 AM PDT 24
Finished Jul 02 07:40:33 AM PDT 24
Peak memory 198504 kb
Host smart-4b5ddd5d-5861-4922-990a-99d85d6876e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654522182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.2654522182
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.357752639
Short name T143
Test name
Test status
Simulation time 22524123 ps
CPU time 0.56 seconds
Started Jul 02 07:38:34 AM PDT 24
Finished Jul 02 07:38:52 AM PDT 24
Peak memory 194440 kb
Host smart-0336abec-81b8-461e-8e00-0e2bed22a1b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357752639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.357752639
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2097630682
Short name T129
Test name
Test status
Simulation time 40033407 ps
CPU time 0.65 seconds
Started Jul 02 07:38:51 AM PDT 24
Finished Jul 02 07:39:06 AM PDT 24
Peak memory 194492 kb
Host smart-235c94f5-b4d3-4d2c-a141-6e98cada5194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097630682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2097630682
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3576344568
Short name T18
Test name
Test status
Simulation time 783297432 ps
CPU time 21.71 seconds
Started Jul 02 07:38:34 AM PDT 24
Finished Jul 02 07:39:13 AM PDT 24
Peak memory 197824 kb
Host smart-4b7ecbf1-9456-4763-9b54-3c637581e9a0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576344568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3576344568
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1250876675
Short name T127
Test name
Test status
Simulation time 68780055 ps
CPU time 1.02 seconds
Started Jul 02 07:38:59 AM PDT 24
Finished Jul 02 07:39:12 AM PDT 24
Peak memory 197172 kb
Host smart-bcba3496-ebd2-4876-b25d-88d2a5b79d7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250876675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1250876675
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.3651885603
Short name T157
Test name
Test status
Simulation time 50237990 ps
CPU time 0.98 seconds
Started Jul 02 07:39:09 AM PDT 24
Finished Jul 02 07:39:16 AM PDT 24
Peak memory 196884 kb
Host smart-9353a109-8b6f-4000-84cf-91ac1ef739dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651885603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3651885603
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3165341839
Short name T573
Test name
Test status
Simulation time 66687042 ps
CPU time 2.59 seconds
Started Jul 02 07:38:33 AM PDT 24
Finished Jul 02 07:38:53 AM PDT 24
Peak memory 198456 kb
Host smart-b6aa4458-e1fe-47b6-be57-2c49103e470a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165341839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.3165341839
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2756728593
Short name T563
Test name
Test status
Simulation time 246062258 ps
CPU time 2.48 seconds
Started Jul 02 07:38:42 AM PDT 24
Finished Jul 02 07:39:00 AM PDT 24
Peak memory 198532 kb
Host smart-b41bdda8-dec9-4149-823a-16b2bcb0f661
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756728593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2756728593
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.4231330187
Short name T340
Test name
Test status
Simulation time 19310827 ps
CPU time 0.82 seconds
Started Jul 02 07:39:14 AM PDT 24
Finished Jul 02 07:39:18 AM PDT 24
Peak memory 196928 kb
Host smart-1faa14a6-0e83-4f2e-8b7f-2571c9affca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231330187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.4231330187
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3741574383
Short name T480
Test name
Test status
Simulation time 114159906 ps
CPU time 0.93 seconds
Started Jul 02 07:38:34 AM PDT 24
Finished Jul 02 07:38:52 AM PDT 24
Peak memory 197152 kb
Host smart-5f1f5a22-308b-4712-b71d-e37b2b74e250
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741574383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3741574383
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2438654238
Short name T107
Test name
Test status
Simulation time 201375485 ps
CPU time 3.26 seconds
Started Jul 02 07:38:43 AM PDT 24
Finished Jul 02 07:39:02 AM PDT 24
Peak memory 198476 kb
Host smart-6e8a6da5-e201-49d3-a5dd-4a3f7c175e19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438654238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2438654238
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.104956451
Short name T239
Test name
Test status
Simulation time 47754533 ps
CPU time 0.95 seconds
Started Jul 02 07:38:49 AM PDT 24
Finished Jul 02 07:39:06 AM PDT 24
Peak memory 196760 kb
Host smart-d351e29c-b166-42c2-923d-2fb17d157cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104956451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.104956451
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3312198221
Short name T706
Test name
Test status
Simulation time 96991459 ps
CPU time 1.01 seconds
Started Jul 02 07:38:42 AM PDT 24
Finished Jul 02 07:38:59 AM PDT 24
Peak memory 195988 kb
Host smart-faddc4e9-ff1a-4a77-a989-f277dd69f31b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312198221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3312198221
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.3463658534
Short name T387
Test name
Test status
Simulation time 23330811376 ps
CPU time 148.65 seconds
Started Jul 02 07:38:39 AM PDT 24
Finished Jul 02 07:41:23 AM PDT 24
Peak memory 198500 kb
Host smart-8bece0a7-69b1-48fe-ad64-4d807342e057
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463658534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3463658534
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.1934103479
Short name T170
Test name
Test status
Simulation time 19847931 ps
CPU time 0.56 seconds
Started Jul 02 07:39:15 AM PDT 24
Finished Jul 02 07:39:18 AM PDT 24
Peak memory 194448 kb
Host smart-733f1baf-b19a-40b1-90be-1c9900149e50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934103479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.1934103479
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.708666399
Short name T135
Test name
Test status
Simulation time 119463970 ps
CPU time 0.7 seconds
Started Jul 02 07:39:05 AM PDT 24
Finished Jul 02 07:39:14 AM PDT 24
Peak memory 195736 kb
Host smart-00b56e45-33e3-4d0a-aa68-6aa92f8e96c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708666399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.708666399
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2775979010
Short name T288
Test name
Test status
Simulation time 3066266724 ps
CPU time 26.55 seconds
Started Jul 02 07:38:44 AM PDT 24
Finished Jul 02 07:39:26 AM PDT 24
Peak memory 198400 kb
Host smart-8bfacbcb-07ea-4b41-bd14-e778f384f657
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775979010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2775979010
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3396353978
Short name T375
Test name
Test status
Simulation time 213105673 ps
CPU time 0.88 seconds
Started Jul 02 07:38:34 AM PDT 24
Finished Jul 02 07:38:52 AM PDT 24
Peak memory 198140 kb
Host smart-2330e2b3-ed04-4805-9bb1-b411c54bcc1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396353978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3396353978
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2736307034
Short name T290
Test name
Test status
Simulation time 214430544 ps
CPU time 0.94 seconds
Started Jul 02 07:38:50 AM PDT 24
Finished Jul 02 07:39:06 AM PDT 24
Peak memory 196996 kb
Host smart-ac63e744-a617-4036-9cd0-630b34a6478e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736307034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2736307034
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3589266808
Short name T629
Test name
Test status
Simulation time 249720639 ps
CPU time 2.36 seconds
Started Jul 02 07:38:34 AM PDT 24
Finished Jul 02 07:38:53 AM PDT 24
Peak memory 198392 kb
Host smart-23ea0ef3-e68e-4a02-9484-f47beba80d7b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589266808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3589266808
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.3099140066
Short name T272
Test name
Test status
Simulation time 71295261 ps
CPU time 1.17 seconds
Started Jul 02 07:39:17 AM PDT 24
Finished Jul 02 07:39:20 AM PDT 24
Peak memory 195864 kb
Host smart-ccc9c8f9-1cb0-4e2e-b908-8d6c10f21d43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099140066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.3099140066
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.21284347
Short name T370
Test name
Test status
Simulation time 122578343 ps
CPU time 0.88 seconds
Started Jul 02 07:39:39 AM PDT 24
Finished Jul 02 07:39:41 AM PDT 24
Peak memory 196272 kb
Host smart-6c019898-954b-4656-a05c-427edb7dc194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21284347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.21284347
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.2383380174
Short name T646
Test name
Test status
Simulation time 41554029 ps
CPU time 0.86 seconds
Started Jul 02 07:39:02 AM PDT 24
Finished Jul 02 07:39:13 AM PDT 24
Peak memory 196280 kb
Host smart-2b925aa3-6e3b-4047-b6e8-0d1f7f43a2eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383380174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.2383380174
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2043492025
Short name T395
Test name
Test status
Simulation time 721442982 ps
CPU time 2.95 seconds
Started Jul 02 07:38:57 AM PDT 24
Finished Jul 02 07:39:12 AM PDT 24
Peak memory 198416 kb
Host smart-49a156f7-028f-4e14-baba-8d33c6165812
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043492025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2043492025
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.1669022084
Short name T396
Test name
Test status
Simulation time 91622765 ps
CPU time 1.16 seconds
Started Jul 02 07:38:38 AM PDT 24
Finished Jul 02 07:38:54 AM PDT 24
Peak memory 196740 kb
Host smart-565e7ff7-49a4-4769-81d4-ef41074a49d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669022084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.1669022084
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2533029924
Short name T165
Test name
Test status
Simulation time 38344192 ps
CPU time 0.82 seconds
Started Jul 02 07:38:53 AM PDT 24
Finished Jul 02 07:39:09 AM PDT 24
Peak memory 195752 kb
Host smart-908a248d-dd08-40ca-8b65-e002f2756cac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533029924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2533029924
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3594821275
Short name T685
Test name
Test status
Simulation time 10339405096 ps
CPU time 144.61 seconds
Started Jul 02 07:38:44 AM PDT 24
Finished Jul 02 07:41:24 AM PDT 24
Peak memory 198980 kb
Host smart-55db8abd-6116-43bf-a55a-79a50f61a869
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594821275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3594821275
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.222421993
Short name T672
Test name
Test status
Simulation time 39226377 ps
CPU time 0.63 seconds
Started Jul 02 07:38:56 AM PDT 24
Finished Jul 02 07:39:09 AM PDT 24
Peak memory 194468 kb
Host smart-f2cd0d54-4681-425a-9f67-961e5b820229
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222421993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.222421993
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.576944593
Short name T371
Test name
Test status
Simulation time 65302790 ps
CPU time 0.67 seconds
Started Jul 02 07:38:43 AM PDT 24
Finished Jul 02 07:38:59 AM PDT 24
Peak memory 194920 kb
Host smart-48dec0da-86bf-4289-928c-bf20225a1331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576944593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.576944593
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2065544623
Short name T502
Test name
Test status
Simulation time 4315987902 ps
CPU time 25.84 seconds
Started Jul 02 07:38:40 AM PDT 24
Finished Jul 02 07:39:21 AM PDT 24
Peak memory 198508 kb
Host smart-1508c270-ea6c-4245-ba7a-ab702d0700c2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065544623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2065544623
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2062830366
Short name T623
Test name
Test status
Simulation time 21896756 ps
CPU time 0.77 seconds
Started Jul 02 07:39:02 AM PDT 24
Finished Jul 02 07:39:13 AM PDT 24
Peak memory 196580 kb
Host smart-3174286a-9c2a-4444-b4a6-25ee027ba200
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062830366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2062830366
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.1250017584
Short name T531
Test name
Test status
Simulation time 25713152 ps
CPU time 1.04 seconds
Started Jul 02 07:39:03 AM PDT 24
Finished Jul 02 07:39:14 AM PDT 24
Peak memory 197596 kb
Host smart-62898e7b-8457-4dbe-9841-55118dc71fd5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250017584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.1250017584
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.826176017
Short name T133
Test name
Test status
Simulation time 317708455 ps
CPU time 0.96 seconds
Started Jul 02 07:38:26 AM PDT 24
Finished Jul 02 07:38:45 AM PDT 24
Peak memory 196036 kb
Host smart-117f19df-bce8-45ca-8e9c-805fe99d6576
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826176017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.
826176017
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2839497327
Short name T332
Test name
Test status
Simulation time 27096065 ps
CPU time 0.9 seconds
Started Jul 02 07:39:55 AM PDT 24
Finished Jul 02 07:39:56 AM PDT 24
Peak memory 196528 kb
Host smart-f1c58352-bb6a-4eee-98fa-e94d86135353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839497327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2839497327
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1786431074
Short name T519
Test name
Test status
Simulation time 29058637 ps
CPU time 1.1 seconds
Started Jul 02 07:39:23 AM PDT 24
Finished Jul 02 07:39:24 AM PDT 24
Peak memory 196636 kb
Host smart-d05e78ce-2fdd-4928-ba32-90812bc94798
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786431074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.1786431074
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.1722076964
Short name T499
Test name
Test status
Simulation time 358465589 ps
CPU time 5.41 seconds
Started Jul 02 07:38:59 AM PDT 24
Finished Jul 02 07:39:16 AM PDT 24
Peak memory 198480 kb
Host smart-dfe55cd4-4806-4bde-997b-bb8790b551e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722076964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.1722076964
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2677565212
Short name T25
Test name
Test status
Simulation time 135320506 ps
CPU time 0.94 seconds
Started Jul 02 07:39:01 AM PDT 24
Finished Jul 02 07:39:12 AM PDT 24
Peak memory 196424 kb
Host smart-67b6f950-6026-4eac-92b9-3779f81c740b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677565212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2677565212
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.3497281004
Short name T318
Test name
Test status
Simulation time 34003937 ps
CPU time 0.98 seconds
Started Jul 02 07:39:03 AM PDT 24
Finished Jul 02 07:39:14 AM PDT 24
Peak memory 196104 kb
Host smart-537d676c-b669-435b-bf59-d95f113b2d95
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497281004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.3497281004
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.1403533401
Short name T441
Test name
Test status
Simulation time 11664387947 ps
CPU time 124.72 seconds
Started Jul 02 07:39:02 AM PDT 24
Finished Jul 02 07:41:17 AM PDT 24
Peak memory 198532 kb
Host smart-b6c3d5f2-85b3-40b4-9fff-4129362cc28c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403533401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.1403533401
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.2971165879
Short name T55
Test name
Test status
Simulation time 216331654850 ps
CPU time 765.09 seconds
Started Jul 02 07:38:52 AM PDT 24
Finished Jul 02 07:51:52 AM PDT 24
Peak memory 198692 kb
Host smart-d911a119-46b5-4dbf-a703-3b84c28a08d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2971165879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.2971165879
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1100190918
Short name T509
Test name
Test status
Simulation time 40849675 ps
CPU time 0.55 seconds
Started Jul 02 07:39:14 AM PDT 24
Finished Jul 02 07:39:18 AM PDT 24
Peak memory 194468 kb
Host smart-dc287e6f-45f1-4473-b824-635b249188d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100190918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1100190918
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1082610699
Short name T430
Test name
Test status
Simulation time 22766721 ps
CPU time 0.64 seconds
Started Jul 02 07:39:00 AM PDT 24
Finished Jul 02 07:39:12 AM PDT 24
Peak memory 195240 kb
Host smart-c26a1e8a-f1bd-4fb4-ac12-89da06e49f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082610699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1082610699
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.102855670
Short name T636
Test name
Test status
Simulation time 6539065745 ps
CPU time 26.52 seconds
Started Jul 02 07:38:39 AM PDT 24
Finished Jul 02 07:39:21 AM PDT 24
Peak memory 197216 kb
Host smart-d96da221-9fb1-43d7-82c5-8b595254fec9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102855670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stres
s.102855670
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.1921869064
Short name T379
Test name
Test status
Simulation time 209564011 ps
CPU time 1 seconds
Started Jul 02 07:39:11 AM PDT 24
Finished Jul 02 07:39:17 AM PDT 24
Peak memory 196924 kb
Host smart-d4a6cce1-a145-407c-96fa-8511fa70b3ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921869064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1921869064
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.708141787
Short name T495
Test name
Test status
Simulation time 90492719 ps
CPU time 0.68 seconds
Started Jul 02 07:38:45 AM PDT 24
Finished Jul 02 07:39:01 AM PDT 24
Peak memory 194728 kb
Host smart-67ad383b-9f80-4800-a6c7-ca2fc1333c96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708141787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.708141787
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.825279760
Short name T101
Test name
Test status
Simulation time 34757760 ps
CPU time 1.32 seconds
Started Jul 02 07:38:40 AM PDT 24
Finished Jul 02 07:38:57 AM PDT 24
Peak memory 196768 kb
Host smart-ef88ed7e-fdbc-4cc8-8c5e-19c355a248f8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825279760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.gpio_intr_with_filter_rand_intr_event.825279760
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1784337317
Short name T255
Test name
Test status
Simulation time 183439255 ps
CPU time 1.53 seconds
Started Jul 02 07:38:49 AM PDT 24
Finished Jul 02 07:39:06 AM PDT 24
Peak memory 197252 kb
Host smart-a69533a9-b687-47d1-a3f0-d0bdef33b5a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784337317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1784337317
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3144223179
Short name T248
Test name
Test status
Simulation time 102155394 ps
CPU time 1.06 seconds
Started Jul 02 07:38:46 AM PDT 24
Finished Jul 02 07:39:02 AM PDT 24
Peak memory 196464 kb
Host smart-3e9f13d1-b39e-48e7-8957-dd1ec37930c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144223179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3144223179
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.898706528
Short name T406
Test name
Test status
Simulation time 113656068 ps
CPU time 0.81 seconds
Started Jul 02 07:39:39 AM PDT 24
Finished Jul 02 07:39:40 AM PDT 24
Peak memory 196880 kb
Host smart-d7d8b50e-18fe-4824-ae1a-0da07f9f7721
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898706528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.898706528
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.256954957
Short name T285
Test name
Test status
Simulation time 32651287 ps
CPU time 1.41 seconds
Started Jul 02 07:39:14 AM PDT 24
Finished Jul 02 07:39:18 AM PDT 24
Peak memory 198236 kb
Host smart-fed62e62-acec-4cac-8693-6b72670d392c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256954957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ran
dom_long_reg_writes_reg_reads.256954957
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1088045309
Short name T287
Test name
Test status
Simulation time 105903783 ps
CPU time 0.96 seconds
Started Jul 02 07:39:16 AM PDT 24
Finished Jul 02 07:39:19 AM PDT 24
Peak memory 196060 kb
Host smart-9ed07f2c-bf42-491a-a5bd-e0767d56675f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088045309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1088045309
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.4222882940
Short name T668
Test name
Test status
Simulation time 280648404 ps
CPU time 1.22 seconds
Started Jul 02 07:38:52 AM PDT 24
Finished Jul 02 07:39:08 AM PDT 24
Peak memory 197164 kb
Host smart-cb2ff501-b26e-4521-b932-6b01296c2df1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222882940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.4222882940
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.208681202
Short name T397
Test name
Test status
Simulation time 53144330588 ps
CPU time 136.15 seconds
Started Jul 02 07:38:43 AM PDT 24
Finished Jul 02 07:41:15 AM PDT 24
Peak memory 198988 kb
Host smart-d6661c60-bccb-4cc2-bac1-dc1e39b9200c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208681202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.208681202
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.1335656155
Short name T715
Test name
Test status
Simulation time 66447544537 ps
CPU time 1276.3 seconds
Started Jul 02 07:39:15 AM PDT 24
Finished Jul 02 08:00:34 AM PDT 24
Peak memory 198720 kb
Host smart-fbdc9810-ab89-4c62-80fa-2c9674f23279
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1335656155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.1335656155
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3529797982
Short name T319
Test name
Test status
Simulation time 12553390 ps
CPU time 0.6 seconds
Started Jul 02 07:38:54 AM PDT 24
Finished Jul 02 07:39:09 AM PDT 24
Peak memory 194440 kb
Host smart-f05b0216-321e-4b2a-a83a-10bb20c32547
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529797982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3529797982
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3222724606
Short name T260
Test name
Test status
Simulation time 47807634 ps
CPU time 0.87 seconds
Started Jul 02 07:38:51 AM PDT 24
Finished Jul 02 07:39:07 AM PDT 24
Peak memory 196792 kb
Host smart-77fe10b8-d56c-425c-bcbd-461bfadc31ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222724606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3222724606
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2918924520
Short name T324
Test name
Test status
Simulation time 506540695 ps
CPU time 8.09 seconds
Started Jul 02 07:38:53 AM PDT 24
Finished Jul 02 07:39:16 AM PDT 24
Peak memory 197228 kb
Host smart-51565518-c472-4a31-8997-52c0abfc433c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918924520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2918924520
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.3143014080
Short name T534
Test name
Test status
Simulation time 102038059 ps
CPU time 1.09 seconds
Started Jul 02 07:38:45 AM PDT 24
Finished Jul 02 07:39:01 AM PDT 24
Peak memory 198480 kb
Host smart-596e4954-e265-4d73-be3c-5d600ff53fed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143014080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3143014080
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.2129697460
Short name T658
Test name
Test status
Simulation time 91495926 ps
CPU time 0.79 seconds
Started Jul 02 07:38:50 AM PDT 24
Finished Jul 02 07:39:06 AM PDT 24
Peak memory 195956 kb
Host smart-b39e4fd4-76e6-4934-9f3a-5043a7ccb530
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129697460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.2129697460
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.4264959083
Short name T669
Test name
Test status
Simulation time 738202530 ps
CPU time 3 seconds
Started Jul 02 07:38:59 AM PDT 24
Finished Jul 02 07:39:14 AM PDT 24
Peak memory 198468 kb
Host smart-65d312ed-0387-4bad-9727-162c3eb59d93
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264959083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.4264959083
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.3591645512
Short name T247
Test name
Test status
Simulation time 292374334 ps
CPU time 1.74 seconds
Started Jul 02 07:38:44 AM PDT 24
Finished Jul 02 07:39:07 AM PDT 24
Peak memory 197152 kb
Host smart-d2f070e0-0293-439c-a8e2-e076709e6f20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591645512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.3591645512
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1487644490
Short name T351
Test name
Test status
Simulation time 31388305 ps
CPU time 0.73 seconds
Started Jul 02 07:38:41 AM PDT 24
Finished Jul 02 07:38:57 AM PDT 24
Peak memory 195920 kb
Host smart-7073ae0c-b565-4e84-a5b4-68705fbb51e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487644490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1487644490
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3418874960
Short name T655
Test name
Test status
Simulation time 64876131 ps
CPU time 1.22 seconds
Started Jul 02 07:38:32 AM PDT 24
Finished Jul 02 07:38:51 AM PDT 24
Peak memory 196304 kb
Host smart-71442148-62f5-4329-9d2f-39828fb5bebe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418874960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.3418874960
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.665127780
Short name T619
Test name
Test status
Simulation time 341164871 ps
CPU time 3.89 seconds
Started Jul 02 07:38:54 AM PDT 24
Finished Jul 02 07:39:12 AM PDT 24
Peak memory 198464 kb
Host smart-f346bab6-8403-4294-9a94-a2a05ee69941
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665127780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ran
dom_long_reg_writes_reg_reads.665127780
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1302584586
Short name T515
Test name
Test status
Simulation time 220347076 ps
CPU time 1.17 seconds
Started Jul 02 07:39:22 AM PDT 24
Finished Jul 02 07:39:24 AM PDT 24
Peak memory 196748 kb
Host smart-1c307004-10c6-41d1-ad76-985c53274eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302584586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1302584586
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.1135581333
Short name T105
Test name
Test status
Simulation time 42110454 ps
CPU time 0.92 seconds
Started Jul 02 07:39:18 AM PDT 24
Finished Jul 02 07:39:20 AM PDT 24
Peak memory 196892 kb
Host smart-f3090606-0d6a-43af-a994-aeb6f46e56b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135581333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.1135581333
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2821612670
Short name T250
Test name
Test status
Simulation time 4874012174 ps
CPU time 68.77 seconds
Started Jul 02 07:38:43 AM PDT 24
Finished Jul 02 07:40:08 AM PDT 24
Peak memory 198552 kb
Host smart-5b82d8d4-eb84-4ce0-ac88-fd03124e57f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821612670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2821612670
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.711391057
Short name T57
Test name
Test status
Simulation time 52584271148 ps
CPU time 774.56 seconds
Started Jul 02 07:38:53 AM PDT 24
Finished Jul 02 07:52:02 AM PDT 24
Peak memory 198632 kb
Host smart-af3c15d6-cd1c-4a77-8276-a71f3ffcc43c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=711391057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.711391057
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.1431954335
Short name T152
Test name
Test status
Simulation time 44407481 ps
CPU time 0.55 seconds
Started Jul 02 07:39:07 AM PDT 24
Finished Jul 02 07:39:15 AM PDT 24
Peak memory 194504 kb
Host smart-5ecbf615-fb40-421f-8694-facc13c00e0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431954335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.1431954335
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1441775269
Short name T634
Test name
Test status
Simulation time 356132474 ps
CPU time 0.92 seconds
Started Jul 02 07:38:37 AM PDT 24
Finished Jul 02 07:38:53 AM PDT 24
Peak memory 196276 kb
Host smart-393d5cc9-75d9-48b5-98cf-29982570f568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441775269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1441775269
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3941253502
Short name T590
Test name
Test status
Simulation time 426005421 ps
CPU time 10.09 seconds
Started Jul 02 07:39:01 AM PDT 24
Finished Jul 02 07:39:21 AM PDT 24
Peak memory 197428 kb
Host smart-579bb9ac-c3d5-4567-b65e-c6aed457eb19
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941253502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3941253502
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3059075753
Short name T345
Test name
Test status
Simulation time 311747810 ps
CPU time 0.88 seconds
Started Jul 02 07:38:53 AM PDT 24
Finished Jul 02 07:39:09 AM PDT 24
Peak memory 196324 kb
Host smart-cfe763b2-41f8-49cf-ac15-33a87d944b07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059075753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3059075753
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2074749142
Short name T188
Test name
Test status
Simulation time 185935596 ps
CPU time 0.96 seconds
Started Jul 02 07:38:48 AM PDT 24
Finished Jul 02 07:39:05 AM PDT 24
Peak memory 196988 kb
Host smart-557ca25e-0496-4db9-b52d-47d391de3dd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074749142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2074749142
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2366604969
Short name T478
Test name
Test status
Simulation time 215489949 ps
CPU time 2.11 seconds
Started Jul 02 07:38:44 AM PDT 24
Finished Jul 02 07:39:02 AM PDT 24
Peak memory 198532 kb
Host smart-f06fa01b-c78a-459c-b08b-a8e6e5866142
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366604969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2366604969
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.331311895
Short name T632
Test name
Test status
Simulation time 179685679 ps
CPU time 2.94 seconds
Started Jul 02 07:38:48 AM PDT 24
Finished Jul 02 07:39:07 AM PDT 24
Peak memory 197748 kb
Host smart-1cf523d5-4586-4563-bda9-b07ab662ca19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331311895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger.
331311895
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.4120172616
Short name T468
Test name
Test status
Simulation time 58311761 ps
CPU time 0.7 seconds
Started Jul 02 07:38:44 AM PDT 24
Finished Jul 02 07:39:00 AM PDT 24
Peak memory 195716 kb
Host smart-01c4d602-c0dd-495b-9910-a862acdb57bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120172616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.4120172616
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1327622826
Short name T116
Test name
Test status
Simulation time 108155012 ps
CPU time 0.9 seconds
Started Jul 02 07:38:55 AM PDT 24
Finished Jul 02 07:39:10 AM PDT 24
Peak memory 196496 kb
Host smart-f3e4b769-4ef8-429a-a133-3b0f9b65deeb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327622826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1327622826
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1708157386
Short name T280
Test name
Test status
Simulation time 271527782 ps
CPU time 2.66 seconds
Started Jul 02 07:38:37 AM PDT 24
Finished Jul 02 07:38:55 AM PDT 24
Peak memory 198440 kb
Host smart-59f7af91-5843-4d63-b989-cf3066fea34b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708157386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1708157386
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.3640031012
Short name T578
Test name
Test status
Simulation time 36996902 ps
CPU time 0.88 seconds
Started Jul 02 07:38:37 AM PDT 24
Finished Jul 02 07:38:53 AM PDT 24
Peak memory 196524 kb
Host smart-a1056320-a4ba-44ae-8f17-31419d288156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640031012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.3640031012
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.2956341242
Short name T64
Test name
Test status
Simulation time 41684261 ps
CPU time 1.17 seconds
Started Jul 02 07:38:39 AM PDT 24
Finished Jul 02 07:38:54 AM PDT 24
Peak memory 196904 kb
Host smart-078de113-d9f2-404d-aa5b-0b4fbe2574e0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956341242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.2956341242
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.995238979
Short name T571
Test name
Test status
Simulation time 183424193289 ps
CPU time 211.47 seconds
Started Jul 02 07:38:40 AM PDT 24
Finished Jul 02 07:42:27 AM PDT 24
Peak memory 198556 kb
Host smart-58d6d19e-db17-461b-a21a-a5f664a05e65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995238979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.g
pio_stress_all.995238979
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.2710199853
Short name T138
Test name
Test status
Simulation time 27569239 ps
CPU time 0.57 seconds
Started Jul 02 07:38:44 AM PDT 24
Finished Jul 02 07:39:00 AM PDT 24
Peak memory 194628 kb
Host smart-15667045-9db6-4340-854e-b20b3cb659ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710199853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2710199853
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3447542469
Short name T661
Test name
Test status
Simulation time 97786473 ps
CPU time 0.78 seconds
Started Jul 02 07:38:45 AM PDT 24
Finished Jul 02 07:39:01 AM PDT 24
Peak memory 195792 kb
Host smart-7e7cf8c2-dc1a-4c6b-aa78-d96f96fac684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447542469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3447542469
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.4229932406
Short name T617
Test name
Test status
Simulation time 194626927 ps
CPU time 9.85 seconds
Started Jul 02 07:38:55 AM PDT 24
Finished Jul 02 07:39:19 AM PDT 24
Peak memory 195984 kb
Host smart-db1a1830-e318-466f-b12d-1d4e8831afbb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229932406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.4229932406
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.4212475780
Short name T114
Test name
Test status
Simulation time 156527854 ps
CPU time 0.75 seconds
Started Jul 02 07:38:37 AM PDT 24
Finished Jul 02 07:38:59 AM PDT 24
Peak memory 196212 kb
Host smart-64c8fe35-92e6-46d3-8094-013608243dc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212475780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.4212475780
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1673501773
Short name T249
Test name
Test status
Simulation time 32353985 ps
CPU time 0.7 seconds
Started Jul 02 07:38:59 AM PDT 24
Finished Jul 02 07:39:11 AM PDT 24
Peak memory 195900 kb
Host smart-c2d7099a-391c-4a55-9dc8-f6bedca35d42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673501773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1673501773
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.2116644111
Short name T454
Test name
Test status
Simulation time 43677759 ps
CPU time 0.92 seconds
Started Jul 02 07:38:51 AM PDT 24
Finished Jul 02 07:39:07 AM PDT 24
Peak memory 196344 kb
Host smart-d2f60ab1-095e-4804-9ed0-b3c2a32179d4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116644111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.2116644111
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.812217812
Short name T576
Test name
Test status
Simulation time 99083486 ps
CPU time 1.75 seconds
Started Jul 02 07:38:37 AM PDT 24
Finished Jul 02 07:38:54 AM PDT 24
Peak memory 196424 kb
Host smart-701114af-0b1f-4ffd-9e7d-ed0a454b8f61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812217812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger.
812217812
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3659407572
Short name T512
Test name
Test status
Simulation time 60370424 ps
CPU time 0.79 seconds
Started Jul 02 07:38:53 AM PDT 24
Finished Jul 02 07:39:09 AM PDT 24
Peak memory 196484 kb
Host smart-a169ccc7-06a8-43cf-8d89-c310adb25da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659407572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3659407572
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.356674320
Short name T422
Test name
Test status
Simulation time 21034192 ps
CPU time 0.65 seconds
Started Jul 02 07:38:59 AM PDT 24
Finished Jul 02 07:39:11 AM PDT 24
Peak memory 194700 kb
Host smart-5e13d099-e748-4ab7-8f70-dddc00cea21e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356674320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup
_pulldown.356674320
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1520948768
Short name T644
Test name
Test status
Simulation time 166498181 ps
CPU time 1.33 seconds
Started Jul 02 07:39:02 AM PDT 24
Finished Jul 02 07:39:13 AM PDT 24
Peak memory 198388 kb
Host smart-8649ec56-62d6-4ad4-a789-da4b5c945286
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520948768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.1520948768
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1556684939
Short name T600
Test name
Test status
Simulation time 87266281 ps
CPU time 1.25 seconds
Started Jul 02 07:38:53 AM PDT 24
Finished Jul 02 07:39:09 AM PDT 24
Peak memory 196060 kb
Host smart-044ff421-7cf5-49ab-9bad-3fb9c44f58b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556684939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1556684939
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3123552229
Short name T187
Test name
Test status
Simulation time 107254759 ps
CPU time 1.03 seconds
Started Jul 02 07:39:02 AM PDT 24
Finished Jul 02 07:39:13 AM PDT 24
Peak memory 196004 kb
Host smart-723d9675-e9bb-45db-8872-b7ccc780dfc4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123552229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3123552229
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.493566314
Short name T353
Test name
Test status
Simulation time 8465238690 ps
CPU time 110.32 seconds
Started Jul 02 07:38:39 AM PDT 24
Finished Jul 02 07:40:44 AM PDT 24
Peak memory 198544 kb
Host smart-66f380b9-f3c4-4881-be99-12b23946c1e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493566314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.g
pio_stress_all.493566314
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.2500164392
Short name T61
Test name
Test status
Simulation time 26642529423 ps
CPU time 858.69 seconds
Started Jul 02 07:38:39 AM PDT 24
Finished Jul 02 07:53:12 AM PDT 24
Peak memory 198704 kb
Host smart-cb978d6e-5f88-4715-852a-f407363557f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2500164392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.2500164392
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.4185360248
Short name T380
Test name
Test status
Simulation time 12227829 ps
CPU time 0.58 seconds
Started Jul 02 07:39:04 AM PDT 24
Finished Jul 02 07:39:14 AM PDT 24
Peak memory 194480 kb
Host smart-2eedf9fb-d4c9-4dcd-98db-6a46e1e04550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185360248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.4185360248
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1769042206
Short name T139
Test name
Test status
Simulation time 23952299 ps
CPU time 0.77 seconds
Started Jul 02 07:38:48 AM PDT 24
Finished Jul 02 07:39:05 AM PDT 24
Peak memory 195816 kb
Host smart-96ef4415-14d9-4f15-a1a0-b9280e52448f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769042206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1769042206
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.441399178
Short name T692
Test name
Test status
Simulation time 592065527 ps
CPU time 3.86 seconds
Started Jul 02 07:39:02 AM PDT 24
Finished Jul 02 07:39:16 AM PDT 24
Peak memory 196276 kb
Host smart-760d3107-9a4c-429e-b8c9-af140f8fbf50
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441399178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.441399178
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2758588464
Short name T281
Test name
Test status
Simulation time 73420253 ps
CPU time 1.06 seconds
Started Jul 02 07:38:49 AM PDT 24
Finished Jul 02 07:39:06 AM PDT 24
Peak memory 197520 kb
Host smart-991017e8-24c4-4df6-9b4a-bd1ae9ec7846
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758588464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2758588464
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.2870227403
Short name T356
Test name
Test status
Simulation time 25155174 ps
CPU time 0.75 seconds
Started Jul 02 07:38:43 AM PDT 24
Finished Jul 02 07:39:00 AM PDT 24
Peak memory 196056 kb
Host smart-1c38ee0b-2d79-48b2-a6f7-2c114b2a6eca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870227403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2870227403
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.3973468432
Short name T428
Test name
Test status
Simulation time 372945885 ps
CPU time 1.94 seconds
Started Jul 02 07:39:05 AM PDT 24
Finished Jul 02 07:39:16 AM PDT 24
Peak memory 198468 kb
Host smart-5b3a356d-8828-44b9-b24f-0df7f351be48
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973468432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.3973468432
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.1686775006
Short name T611
Test name
Test status
Simulation time 278120557 ps
CPU time 1.7 seconds
Started Jul 02 07:38:48 AM PDT 24
Finished Jul 02 07:39:06 AM PDT 24
Peak memory 197216 kb
Host smart-d0961e56-ff1c-4a0f-9b97-92405613839b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686775006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.1686775006
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.2704942136
Short name T130
Test name
Test status
Simulation time 29367646 ps
CPU time 0.75 seconds
Started Jul 02 07:38:53 AM PDT 24
Finished Jul 02 07:39:09 AM PDT 24
Peak memory 195936 kb
Host smart-75894234-e75a-4c90-8310-93b172817559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704942136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.2704942136
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.143207704
Short name T510
Test name
Test status
Simulation time 84044852 ps
CPU time 0.73 seconds
Started Jul 02 07:39:00 AM PDT 24
Finished Jul 02 07:39:12 AM PDT 24
Peak memory 196572 kb
Host smart-4724a569-4ad4-49ed-b37f-1010208d4a01
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143207704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.143207704
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.713398731
Short name T449
Test name
Test status
Simulation time 338006584 ps
CPU time 4.06 seconds
Started Jul 02 07:38:56 AM PDT 24
Finished Jul 02 07:39:13 AM PDT 24
Peak memory 198440 kb
Host smart-5a50a0ca-1fbe-4523-bba8-7dae3ec7b27e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713398731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ran
dom_long_reg_writes_reg_reads.713398731
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1580678396
Short name T455
Test name
Test status
Simulation time 272886198 ps
CPU time 1.25 seconds
Started Jul 02 07:39:05 AM PDT 24
Finished Jul 02 07:39:15 AM PDT 24
Peak memory 196116 kb
Host smart-19aa07e2-c0d6-4906-9b0f-70fcd6f9c1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580678396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1580678396
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.3114303066
Short name T429
Test name
Test status
Simulation time 58868076 ps
CPU time 1.12 seconds
Started Jul 02 07:39:05 AM PDT 24
Finished Jul 02 07:39:15 AM PDT 24
Peak memory 196340 kb
Host smart-f15e2b7d-f97e-4f02-b1ae-62855c29e54c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114303066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.3114303066
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2479722786
Short name T47
Test name
Test status
Simulation time 1937771181 ps
CPU time 28.57 seconds
Started Jul 02 07:39:04 AM PDT 24
Finished Jul 02 07:39:44 AM PDT 24
Peak memory 198656 kb
Host smart-9949d368-a4c4-4865-8856-d3d8e95da4ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479722786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2479722786
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3648413188
Short name T584
Test name
Test status
Simulation time 83765803 ps
CPU time 0.55 seconds
Started Jul 02 07:38:59 AM PDT 24
Finished Jul 02 07:39:11 AM PDT 24
Peak memory 194636 kb
Host smart-e6b3add8-1a3b-43be-a0bb-ed534871f964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648413188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3648413188
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.2400555178
Short name T594
Test name
Test status
Simulation time 101413237 ps
CPU time 0.72 seconds
Started Jul 02 07:39:02 AM PDT 24
Finished Jul 02 07:39:13 AM PDT 24
Peak memory 195684 kb
Host smart-809eeadd-c1da-4a72-a6ef-5cce493ef566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400555178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.2400555178
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1907431612
Short name T176
Test name
Test status
Simulation time 885279801 ps
CPU time 8.04 seconds
Started Jul 02 07:39:06 AM PDT 24
Finished Jul 02 07:39:23 AM PDT 24
Peak memory 198432 kb
Host smart-b7a987e2-3a46-4da2-9703-6bed1e01a985
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907431612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1907431612
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.3620295282
Short name T357
Test name
Test status
Simulation time 129433911 ps
CPU time 0.67 seconds
Started Jul 02 07:38:57 AM PDT 24
Finished Jul 02 07:39:10 AM PDT 24
Peak memory 194988 kb
Host smart-13ab220a-19fb-4757-b364-0d6bfa39808f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620295282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.3620295282
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.3699876341
Short name T169
Test name
Test status
Simulation time 85407810 ps
CPU time 0.65 seconds
Started Jul 02 07:39:00 AM PDT 24
Finished Jul 02 07:39:12 AM PDT 24
Peak memory 194728 kb
Host smart-ff60867c-96af-486b-aa8e-c3e3e304ece2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699876341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.3699876341
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3470723812
Short name T384
Test name
Test status
Simulation time 28271312 ps
CPU time 1.12 seconds
Started Jul 02 07:39:07 AM PDT 24
Finished Jul 02 07:39:16 AM PDT 24
Peak memory 198312 kb
Host smart-2feb288d-fde3-43dc-b67e-c2d33dc154e2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470723812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3470723812
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.4254880007
Short name T673
Test name
Test status
Simulation time 17237271 ps
CPU time 0.7 seconds
Started Jul 02 07:39:01 AM PDT 24
Finished Jul 02 07:39:12 AM PDT 24
Peak memory 194788 kb
Host smart-90a9510d-e705-41a7-82c6-289812297793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254880007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.4254880007
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.542576249
Short name T405
Test name
Test status
Simulation time 124191142 ps
CPU time 1.16 seconds
Started Jul 02 07:38:50 AM PDT 24
Finished Jul 02 07:39:06 AM PDT 24
Peak memory 197364 kb
Host smart-a9f2cbde-6cd7-4815-802c-a9a895da0fd2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542576249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup
_pulldown.542576249
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1239286966
Short name T494
Test name
Test status
Simulation time 1325528432 ps
CPU time 5.98 seconds
Started Jul 02 07:39:01 AM PDT 24
Finished Jul 02 07:39:17 AM PDT 24
Peak memory 198376 kb
Host smart-f67173a9-2804-4408-a8b8-785d818b5d10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239286966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1239286966
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.207199336
Short name T686
Test name
Test status
Simulation time 103199207 ps
CPU time 1.36 seconds
Started Jul 02 07:38:53 AM PDT 24
Finished Jul 02 07:39:09 AM PDT 24
Peak memory 197360 kb
Host smart-040b73fe-bbf4-417e-a775-17f0d77949b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207199336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.207199336
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.1482099102
Short name T491
Test name
Test status
Simulation time 41581856 ps
CPU time 0.93 seconds
Started Jul 02 07:38:46 AM PDT 24
Finished Jul 02 07:39:02 AM PDT 24
Peak memory 196200 kb
Host smart-cddfe243-519b-4934-9ead-25b0b356753f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482099102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.1482099102
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.1892052671
Short name T65
Test name
Test status
Simulation time 4522056653 ps
CPU time 57.03 seconds
Started Jul 02 07:39:07 AM PDT 24
Finished Jul 02 07:40:12 AM PDT 24
Peak memory 198560 kb
Host smart-e0dbe0e8-f722-4511-9c91-b691810f4e77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892052671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1892052671
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.2691740339
Short name T388
Test name
Test status
Simulation time 14054142 ps
CPU time 0.56 seconds
Started Jul 02 07:37:31 AM PDT 24
Finished Jul 02 07:37:41 AM PDT 24
Peak memory 195040 kb
Host smart-33b301c0-ca3d-444f-982b-c30f8a4e8835
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691740339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.2691740339
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.482118898
Short name T530
Test name
Test status
Simulation time 12292048 ps
CPU time 0.61 seconds
Started Jul 02 07:37:19 AM PDT 24
Finished Jul 02 07:37:26 AM PDT 24
Peak memory 195024 kb
Host smart-c1086e5b-32f6-4c16-a9d4-1d42cfb922e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482118898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.482118898
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.3935406902
Short name T54
Test name
Test status
Simulation time 1077286677 ps
CPU time 5.44 seconds
Started Jul 02 07:37:24 AM PDT 24
Finished Jul 02 07:37:38 AM PDT 24
Peak memory 197352 kb
Host smart-dbfd72d1-717f-4f09-a811-ee522fb54715
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935406902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.3935406902
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.878977011
Short name T570
Test name
Test status
Simulation time 192381752 ps
CPU time 1.02 seconds
Started Jul 02 07:39:02 AM PDT 24
Finished Jul 02 07:39:13 AM PDT 24
Peak memory 196784 kb
Host smart-126fe4ef-9635-48be-ae30-947add169c1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878977011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.878977011
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.2601806506
Short name T220
Test name
Test status
Simulation time 91076492 ps
CPU time 1.3 seconds
Started Jul 02 07:37:19 AM PDT 24
Finished Jul 02 07:37:27 AM PDT 24
Peak memory 197876 kb
Host smart-000fb1f5-1a67-4db0-9c87-e5305b9a3dea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601806506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.2601806506
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.1366555861
Short name T299
Test name
Test status
Simulation time 68147426 ps
CPU time 2.58 seconds
Started Jul 02 07:37:29 AM PDT 24
Finished Jul 02 07:37:41 AM PDT 24
Peak memory 198516 kb
Host smart-7f59d2ea-effd-4c88-9173-e84a589d94ef
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366555861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.1366555861
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.3859731397
Short name T415
Test name
Test status
Simulation time 595362820 ps
CPU time 2.34 seconds
Started Jul 02 07:37:30 AM PDT 24
Finished Jul 02 07:37:41 AM PDT 24
Peak memory 198548 kb
Host smart-7b1a0e96-a33b-4737-ba83-3e054935c2ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859731397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
3859731397
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1691079962
Short name T109
Test name
Test status
Simulation time 308006273 ps
CPU time 0.83 seconds
Started Jul 02 07:37:34 AM PDT 24
Finished Jul 02 07:37:46 AM PDT 24
Peak memory 196416 kb
Host smart-15b78b9f-be87-466f-beb9-b3e7617eb427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691079962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1691079962
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1881844483
Short name T490
Test name
Test status
Simulation time 153990711 ps
CPU time 0.86 seconds
Started Jul 02 07:37:19 AM PDT 24
Finished Jul 02 07:37:26 AM PDT 24
Peak memory 196292 kb
Host smart-f51e8801-81d9-4802-8de7-c84cccbeb870
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881844483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.1881844483
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2123518575
Short name T194
Test name
Test status
Simulation time 944977844 ps
CPU time 3.8 seconds
Started Jul 02 07:37:19 AM PDT 24
Finished Jul 02 07:37:29 AM PDT 24
Peak memory 197540 kb
Host smart-2e2704b4-f385-4e90-b390-b4986d27b0c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123518575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2123518575
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1259027244
Short name T640
Test name
Test status
Simulation time 35261234 ps
CPU time 0.86 seconds
Started Jul 02 07:37:27 AM PDT 24
Finished Jul 02 07:37:36 AM PDT 24
Peak memory 196924 kb
Host smart-5cca005e-76f8-46de-be22-bb5c0a897fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259027244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1259027244
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3343390425
Short name T178
Test name
Test status
Simulation time 188224923 ps
CPU time 1.35 seconds
Started Jul 02 07:37:13 AM PDT 24
Finished Jul 02 07:37:17 AM PDT 24
Peak memory 197300 kb
Host smart-694f4a6b-840e-4647-aac5-6f3cb2ffff49
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343390425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3343390425
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.2426094187
Short name T698
Test name
Test status
Simulation time 7657368377 ps
CPU time 178.87 seconds
Started Jul 02 07:37:39 AM PDT 24
Finished Jul 02 07:40:49 AM PDT 24
Peak memory 198556 kb
Host smart-53294600-e4bb-4347-9828-094dc4e26adc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426094187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.2426094187
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.1567573688
Short name T311
Test name
Test status
Simulation time 26140679 ps
CPU time 0.57 seconds
Started Jul 02 07:37:25 AM PDT 24
Finished Jul 02 07:37:34 AM PDT 24
Peak memory 194888 kb
Host smart-4265013e-eec3-480c-9bd4-671538092d7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567573688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.1567573688
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2847301884
Short name T168
Test name
Test status
Simulation time 184889433 ps
CPU time 0.94 seconds
Started Jul 02 07:37:54 AM PDT 24
Finished Jul 02 07:38:06 AM PDT 24
Peak memory 197796 kb
Host smart-6c106876-32ee-480d-99ec-9191304134a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847301884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2847301884
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.2904386198
Short name T536
Test name
Test status
Simulation time 627926771 ps
CPU time 17.67 seconds
Started Jul 02 07:37:29 AM PDT 24
Finished Jul 02 07:37:56 AM PDT 24
Peak memory 196924 kb
Host smart-6883616d-aeb8-40ad-b5a5-7a1cde760361
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904386198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.2904386198
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.1243687641
Short name T426
Test name
Test status
Simulation time 265978609 ps
CPU time 0.83 seconds
Started Jul 02 07:39:02 AM PDT 24
Finished Jul 02 07:39:13 AM PDT 24
Peak memory 197512 kb
Host smart-806dd60a-08cc-4152-a742-a05c0584bd0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243687641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1243687641
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2894609428
Short name T606
Test name
Test status
Simulation time 329238964 ps
CPU time 1.15 seconds
Started Jul 02 07:37:29 AM PDT 24
Finished Jul 02 07:37:39 AM PDT 24
Peak memory 196476 kb
Host smart-fb9e491e-a1b9-4db1-9d4c-4166c4de80a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894609428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2894609428
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2716824823
Short name T631
Test name
Test status
Simulation time 33613621 ps
CPU time 1.31 seconds
Started Jul 02 07:37:25 AM PDT 24
Finished Jul 02 07:37:35 AM PDT 24
Peak memory 196436 kb
Host smart-b294908e-78d1-468d-a34c-661a24d7a695
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716824823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2716824823
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1492437644
Short name T511
Test name
Test status
Simulation time 59893105 ps
CPU time 0.97 seconds
Started Jul 02 07:37:23 AM PDT 24
Finished Jul 02 07:37:32 AM PDT 24
Peak memory 197088 kb
Host smart-91971d55-ef2f-4ea4-ad9c-fa172c43af8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492437644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1492437644
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.235036494
Short name T481
Test name
Test status
Simulation time 44608211 ps
CPU time 0.96 seconds
Started Jul 02 07:38:31 AM PDT 24
Finished Jul 02 07:38:50 AM PDT 24
Peak memory 195460 kb
Host smart-c2da7ac5-994d-44a6-9adf-c2a34f31a727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235036494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.235036494
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.2552998886
Short name T697
Test name
Test status
Simulation time 24777314 ps
CPU time 0.93 seconds
Started Jul 02 07:37:30 AM PDT 24
Finished Jul 02 07:37:40 AM PDT 24
Peak memory 196200 kb
Host smart-28515c15-3d7e-4a12-a034-bae4d6bdced3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552998886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.2552998886
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.3222026756
Short name T670
Test name
Test status
Simulation time 313717185 ps
CPU time 4.81 seconds
Started Jul 02 07:38:31 AM PDT 24
Finished Jul 02 07:38:54 AM PDT 24
Peak memory 196968 kb
Host smart-a95ce9c8-e20e-49d6-8794-163a326d9d35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222026756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.3222026756
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.426574522
Short name T694
Test name
Test status
Simulation time 101673244 ps
CPU time 0.99 seconds
Started Jul 02 07:37:25 AM PDT 24
Finished Jul 02 07:37:34 AM PDT 24
Peak memory 196152 kb
Host smart-32958270-9d11-46d8-9469-2da209e6e02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426574522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.426574522
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.2797156470
Short name T289
Test name
Test status
Simulation time 89621215 ps
CPU time 1.03 seconds
Started Jul 02 07:37:20 AM PDT 24
Finished Jul 02 07:37:28 AM PDT 24
Peak memory 196444 kb
Host smart-3c7b0906-e2a4-43c9-911f-82a6f3c27b99
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797156470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.2797156470
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.937876478
Short name T334
Test name
Test status
Simulation time 3033515756 ps
CPU time 73.59 seconds
Started Jul 02 07:37:25 AM PDT 24
Finished Jul 02 07:38:47 AM PDT 24
Peak memory 198572 kb
Host smart-78a5a3aa-6ad1-4876-9330-a9d100e92227
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937876478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gp
io_stress_all.937876478
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.2093236176
Short name T610
Test name
Test status
Simulation time 469545760324 ps
CPU time 2399.48 seconds
Started Jul 02 07:37:32 AM PDT 24
Finished Jul 02 08:17:42 AM PDT 24
Peak memory 198724 kb
Host smart-c37cb379-7903-4605-8115-2951b2160424
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2093236176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.2093236176
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.1840465828
Short name T151
Test name
Test status
Simulation time 22559633 ps
CPU time 0.59 seconds
Started Jul 02 07:37:33 AM PDT 24
Finished Jul 02 07:37:45 AM PDT 24
Peak memory 195176 kb
Host smart-e73e497e-a551-490f-87ac-9df113cca2c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840465828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.1840465828
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.1428787486
Short name T473
Test name
Test status
Simulation time 51993409 ps
CPU time 0.88 seconds
Started Jul 02 07:37:26 AM PDT 24
Finished Jul 02 07:37:41 AM PDT 24
Peak memory 196408 kb
Host smart-7a59dfe8-e7a4-45c3-b967-5157b072e319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428787486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.1428787486
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2905809671
Short name T565
Test name
Test status
Simulation time 123721321 ps
CPU time 3.31 seconds
Started Jul 02 07:39:03 AM PDT 24
Finished Jul 02 07:39:16 AM PDT 24
Peak memory 196352 kb
Host smart-17571463-b9a0-45a3-b926-638ffd5e337a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905809671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2905809671
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1128973703
Short name T256
Test name
Test status
Simulation time 346098887 ps
CPU time 0.82 seconds
Started Jul 02 07:37:25 AM PDT 24
Finished Jul 02 07:37:34 AM PDT 24
Peak memory 196220 kb
Host smart-8d30c0b3-0244-45ec-ba1e-36cc62459b93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128973703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1128973703
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.4188762556
Short name T450
Test name
Test status
Simulation time 222841273 ps
CPU time 1 seconds
Started Jul 02 07:37:25 AM PDT 24
Finished Jul 02 07:37:34 AM PDT 24
Peak memory 196928 kb
Host smart-65f01d0f-60c1-4a1a-adf8-9f4f127db1fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188762556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.4188762556
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.2819142210
Short name T526
Test name
Test status
Simulation time 127548221 ps
CPU time 2.27 seconds
Started Jul 02 07:39:03 AM PDT 24
Finished Jul 02 07:39:15 AM PDT 24
Peak memory 198424 kb
Host smart-c57fcd15-b7d6-4125-9eba-f4f5969e9816
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819142210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.2819142210
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.734778571
Short name T437
Test name
Test status
Simulation time 91604459 ps
CPU time 1.8 seconds
Started Jul 02 07:37:25 AM PDT 24
Finished Jul 02 07:37:35 AM PDT 24
Peak memory 197244 kb
Host smart-0f8eca90-3cf0-4470-83b3-8c7555ad4ef6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734778571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.734778571
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1605391979
Short name T67
Test name
Test status
Simulation time 88683578 ps
CPU time 0.96 seconds
Started Jul 02 07:37:19 AM PDT 24
Finished Jul 02 07:37:26 AM PDT 24
Peak memory 196700 kb
Host smart-20c7ca08-159d-4173-9ff3-b75f274cb286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605391979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1605391979
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.4142981435
Short name T696
Test name
Test status
Simulation time 111023105 ps
CPU time 0.66 seconds
Started Jul 02 07:37:28 AM PDT 24
Finished Jul 02 07:37:38 AM PDT 24
Peak memory 195852 kb
Host smart-3c2072da-21c9-4939-8eea-af88ccab5827
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142981435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.4142981435
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3492915518
Short name T216
Test name
Test status
Simulation time 177195001 ps
CPU time 1.95 seconds
Started Jul 02 07:38:31 AM PDT 24
Finished Jul 02 07:38:51 AM PDT 24
Peak memory 197132 kb
Host smart-66f58a01-9c04-4c1c-9ec5-c21e8ed32dec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492915518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3492915518
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1488052356
Short name T292
Test name
Test status
Simulation time 279960072 ps
CPU time 1.12 seconds
Started Jul 02 07:37:26 AM PDT 24
Finished Jul 02 07:37:35 AM PDT 24
Peak memory 196116 kb
Host smart-224968d9-866d-4e5d-87a4-d479c32e247b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488052356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1488052356
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.198052853
Short name T121
Test name
Test status
Simulation time 499875543 ps
CPU time 1.37 seconds
Started Jul 02 07:37:37 AM PDT 24
Finished Jul 02 07:37:50 AM PDT 24
Peak memory 197292 kb
Host smart-fb220bfd-b944-4b99-90bf-89f445c8a2c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198052853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.198052853
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.168923507
Short name T228
Test name
Test status
Simulation time 135119635973 ps
CPU time 187.59 seconds
Started Jul 02 07:37:26 AM PDT 24
Finished Jul 02 07:40:42 AM PDT 24
Peak memory 198440 kb
Host smart-cf4d4c9e-99fa-4c6c-acf1-eacca67a2efc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168923507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.168923507
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.140143646
Short name T330
Test name
Test status
Simulation time 39305108 ps
CPU time 0.57 seconds
Started Jul 02 07:37:40 AM PDT 24
Finished Jul 02 07:37:52 AM PDT 24
Peak memory 194696 kb
Host smart-2c62659a-ecd6-4770-af51-e2d0aafb36ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140143646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.140143646
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.3885640817
Short name T711
Test name
Test status
Simulation time 27547230 ps
CPU time 0.83 seconds
Started Jul 02 07:37:28 AM PDT 24
Finished Jul 02 07:37:38 AM PDT 24
Peak memory 195824 kb
Host smart-39748a98-8fbb-4f54-914c-8bf3757de158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885640817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.3885640817
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.249011970
Short name T348
Test name
Test status
Simulation time 348727035 ps
CPU time 9.41 seconds
Started Jul 02 07:37:28 AM PDT 24
Finished Jul 02 07:37:48 AM PDT 24
Peak memory 197364 kb
Host smart-c2564192-e4fb-4805-ac20-ab39d22683d7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249011970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress
.249011970
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1622650745
Short name T527
Test name
Test status
Simulation time 83037635 ps
CPU time 0.64 seconds
Started Jul 02 07:37:22 AM PDT 24
Finished Jul 02 07:37:30 AM PDT 24
Peak memory 194872 kb
Host smart-81a579f8-77b8-48cc-94d1-65243fe08519
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622650745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1622650745
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1697107223
Short name T282
Test name
Test status
Simulation time 24410392 ps
CPU time 0.72 seconds
Started Jul 02 07:37:30 AM PDT 24
Finished Jul 02 07:37:40 AM PDT 24
Peak memory 194732 kb
Host smart-e2a9b679-2156-4683-a24f-980fb313baf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697107223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1697107223
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.3073343765
Short name T475
Test name
Test status
Simulation time 127283270 ps
CPU time 2.22 seconds
Started Jul 02 07:37:45 AM PDT 24
Finished Jul 02 07:38:03 AM PDT 24
Peak memory 198556 kb
Host smart-39ee8803-fdd6-44b8-990c-9c7b00b92689
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073343765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.3073343765
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.3120212561
Short name T476
Test name
Test status
Simulation time 213583516 ps
CPU time 2.96 seconds
Started Jul 02 07:37:25 AM PDT 24
Finished Jul 02 07:37:37 AM PDT 24
Peak memory 197240 kb
Host smart-e44cb00b-27fc-46ce-80d7-08616f9f4427
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120212561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
3120212561
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3472750082
Short name T447
Test name
Test status
Simulation time 52803259 ps
CPU time 1.13 seconds
Started Jul 02 07:39:02 AM PDT 24
Finished Jul 02 07:39:13 AM PDT 24
Peak memory 197356 kb
Host smart-aaeda28c-1da8-4768-8760-65d00f813d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472750082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3472750082
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3414883100
Short name T251
Test name
Test status
Simulation time 279259840 ps
CPU time 0.72 seconds
Started Jul 02 07:39:02 AM PDT 24
Finished Jul 02 07:39:13 AM PDT 24
Peak memory 195804 kb
Host smart-efd0a925-f405-4e3c-b5b6-4c1982c69641
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414883100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3414883100
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.3888462074
Short name T328
Test name
Test status
Simulation time 423808825 ps
CPU time 1.8 seconds
Started Jul 02 07:37:46 AM PDT 24
Finished Jul 02 07:37:59 AM PDT 24
Peak memory 198440 kb
Host smart-f82ef2fb-b8a3-46b1-8d5c-6536183e19ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888462074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.3888462074
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.3133615618
Short name T339
Test name
Test status
Simulation time 238062357 ps
CPU time 1.14 seconds
Started Jul 02 07:37:19 AM PDT 24
Finished Jul 02 07:37:27 AM PDT 24
Peak memory 196124 kb
Host smart-5e240111-03fd-4064-b92f-27f4edc86f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133615618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3133615618
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.1194272596
Short name T569
Test name
Test status
Simulation time 125232813 ps
CPU time 1.3 seconds
Started Jul 02 07:38:57 AM PDT 24
Finished Jul 02 07:39:11 AM PDT 24
Peak memory 197240 kb
Host smart-3ed199a2-7b8c-4fd8-bc3c-c309f4e739bc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194272596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.1194272596
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2093121169
Short name T566
Test name
Test status
Simulation time 6244948383 ps
CPU time 176.57 seconds
Started Jul 02 07:37:35 AM PDT 24
Finished Jul 02 07:40:44 AM PDT 24
Peak memory 199020 kb
Host smart-366431ea-e5d6-4b4b-bef4-08da36b1e0b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093121169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2093121169
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2851303700
Short name T684
Test name
Test status
Simulation time 44027766 ps
CPU time 0.54 seconds
Started Jul 02 07:37:34 AM PDT 24
Finished Jul 02 07:37:46 AM PDT 24
Peak memory 194452 kb
Host smart-bc046c51-4deb-40e0-855e-6eaf02d8961b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851303700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2851303700
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.667588509
Short name T411
Test name
Test status
Simulation time 74246742 ps
CPU time 0.59 seconds
Started Jul 02 07:37:41 AM PDT 24
Finished Jul 02 07:37:57 AM PDT 24
Peak memory 195028 kb
Host smart-e83cd828-e3d4-4b9f-ab32-6fab1ac802e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667588509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.667588509
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1976508944
Short name T595
Test name
Test status
Simulation time 3631565508 ps
CPU time 28.28 seconds
Started Jul 02 07:37:23 AM PDT 24
Finished Jul 02 07:38:00 AM PDT 24
Peak memory 197808 kb
Host smart-9a63a520-802c-4037-a81b-1f61853f51e2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976508944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1976508944
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.756046323
Short name T704
Test name
Test status
Simulation time 70652353 ps
CPU time 0.71 seconds
Started Jul 02 07:37:33 AM PDT 24
Finished Jul 02 07:37:45 AM PDT 24
Peak memory 195112 kb
Host smart-e8bf0a9e-c6db-44dd-a98c-072bad6b477f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756046323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.756046323
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.2761602189
Short name T204
Test name
Test status
Simulation time 110379940 ps
CPU time 1.42 seconds
Started Jul 02 07:37:32 AM PDT 24
Finished Jul 02 07:37:43 AM PDT 24
Peak memory 196980 kb
Host smart-3f2eb8f8-f9d2-4d8d-b357-1eb4ec8f767b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761602189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.2761602189
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.3554313130
Short name T612
Test name
Test status
Simulation time 278776264 ps
CPU time 2.54 seconds
Started Jul 02 07:38:42 AM PDT 24
Finished Jul 02 07:39:00 AM PDT 24
Peak memory 197712 kb
Host smart-1a99f739-3635-4481-88a6-a9a799f88e1d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554313130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.3554313130
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.2320104188
Short name T420
Test name
Test status
Simulation time 203639745 ps
CPU time 1.56 seconds
Started Jul 02 07:37:31 AM PDT 24
Finished Jul 02 07:37:43 AM PDT 24
Peak memory 196916 kb
Host smart-448e206c-3a28-4b58-aeb3-c234abd666eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320104188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
2320104188
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.3647058439
Short name T390
Test name
Test status
Simulation time 29672399 ps
CPU time 0.72 seconds
Started Jul 02 07:37:25 AM PDT 24
Finished Jul 02 07:37:34 AM PDT 24
Peak memory 195872 kb
Host smart-70208b66-9273-40b2-8872-74504a20718a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647058439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3647058439
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3548835192
Short name T402
Test name
Test status
Simulation time 20402890 ps
CPU time 0.78 seconds
Started Jul 02 07:37:48 AM PDT 24
Finished Jul 02 07:37:59 AM PDT 24
Peak memory 196860 kb
Host smart-bf9019d4-bcd6-42b2-a016-0aea3aa6e9bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548835192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3548835192
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.517009244
Short name T198
Test name
Test status
Simulation time 262271801 ps
CPU time 2.31 seconds
Started Jul 02 07:39:00 AM PDT 24
Finished Jul 02 07:39:13 AM PDT 24
Peak memory 198208 kb
Host smart-2c646210-6ce0-4b6a-ab98-c6d857bca1ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517009244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.517009244
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1691074913
Short name T225
Test name
Test status
Simulation time 73633220 ps
CPU time 1.27 seconds
Started Jul 02 07:37:20 AM PDT 24
Finished Jul 02 07:37:29 AM PDT 24
Peak memory 198428 kb
Host smart-a5fa735c-f9b3-4e23-b14e-f4997b57a930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691074913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1691074913
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2530324297
Short name T414
Test name
Test status
Simulation time 68065278 ps
CPU time 1.28 seconds
Started Jul 02 07:37:30 AM PDT 24
Finished Jul 02 07:37:41 AM PDT 24
Peak memory 197308 kb
Host smart-c0a22d50-65ec-47de-a31b-0d60c63ef562
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530324297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2530324297
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.3386028231
Short name T167
Test name
Test status
Simulation time 9139945675 ps
CPU time 45.65 seconds
Started Jul 02 07:39:06 AM PDT 24
Finished Jul 02 07:40:00 AM PDT 24
Peak memory 198540 kb
Host smart-0414e062-b68f-4534-822e-10d5421dc079
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386028231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.3386028231
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1363972415
Short name T864
Test name
Test status
Simulation time 81712838 ps
CPU time 1.02 seconds
Started Jul 02 07:33:43 AM PDT 24
Finished Jul 02 07:33:46 AM PDT 24
Peak memory 197108 kb
Host smart-654d5c76-756b-4236-bc19-dbd3747f0a8e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1363972415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.1363972415
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3888967798
Short name T935
Test name
Test status
Simulation time 102724908 ps
CPU time 1.44 seconds
Started Jul 02 07:33:06 AM PDT 24
Finished Jul 02 07:33:08 AM PDT 24
Peak memory 197052 kb
Host smart-ab36a204-b032-4e60-a0b4-a5a5a24af4bd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888967798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3888967798
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1058233054
Short name T940
Test name
Test status
Simulation time 161707771 ps
CPU time 0.89 seconds
Started Jul 02 07:32:32 AM PDT 24
Finished Jul 02 07:32:34 AM PDT 24
Peak memory 196648 kb
Host smart-1c13048f-5c6d-41e3-beac-f942cb3ccf86
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1058233054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.1058233054
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1898829598
Short name T928
Test name
Test status
Simulation time 40023142 ps
CPU time 0.92 seconds
Started Jul 02 07:35:49 AM PDT 24
Finished Jul 02 07:35:51 AM PDT 24
Peak memory 196196 kb
Host smart-81e01b92-9a82-4fca-9ccb-5ee0533bb358
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898829598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1898829598
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3942763388
Short name T941
Test name
Test status
Simulation time 348869335 ps
CPU time 1.53 seconds
Started Jul 02 07:36:01 AM PDT 24
Finished Jul 02 07:36:03 AM PDT 24
Peak memory 198728 kb
Host smart-8dccfcf3-f742-4403-af37-12447ab8afbd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3942763388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3942763388
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3981446351
Short name T923
Test name
Test status
Simulation time 157802065 ps
CPU time 0.99 seconds
Started Jul 02 07:33:50 AM PDT 24
Finished Jul 02 07:33:51 AM PDT 24
Peak memory 196792 kb
Host smart-e25257bc-5029-4368-b286-bcbce847ea7c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981446351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3981446351
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.885173136
Short name T845
Test name
Test status
Simulation time 43116944 ps
CPU time 0.85 seconds
Started Jul 02 07:36:17 AM PDT 24
Finished Jul 02 07:36:19 AM PDT 24
Peak memory 195824 kb
Host smart-1b205a87-c692-414f-b081-7b73d745160e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=885173136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.885173136
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2442474158
Short name T919
Test name
Test status
Simulation time 191329865 ps
CPU time 1.13 seconds
Started Jul 02 07:31:48 AM PDT 24
Finished Jul 02 07:31:49 AM PDT 24
Peak memory 196824 kb
Host smart-c921aa6f-edd2-4ef1-896d-4fcfefc7e46c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442474158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2442474158
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.4108037157
Short name T868
Test name
Test status
Simulation time 88354333 ps
CPU time 0.91 seconds
Started Jul 02 07:36:45 AM PDT 24
Finished Jul 02 07:36:53 AM PDT 24
Peak memory 198056 kb
Host smart-5efe5249-3694-4a6e-88d4-9b8d7a29a2e1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4108037157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.4108037157
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3613189516
Short name T903
Test name
Test status
Simulation time 81167113 ps
CPU time 0.73 seconds
Started Jul 02 07:36:49 AM PDT 24
Finished Jul 02 07:36:55 AM PDT 24
Peak memory 195580 kb
Host smart-383d97af-f97d-4947-9ca8-ccb86ab9a714
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613189516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3613189516
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.575268912
Short name T916
Test name
Test status
Simulation time 79806468 ps
CPU time 1.41 seconds
Started Jul 02 07:32:06 AM PDT 24
Finished Jul 02 07:32:08 AM PDT 24
Peak memory 196844 kb
Host smart-0c06641d-d6fb-4414-85f0-c5f628fcb7de
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=575268912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.575268912
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.158489051
Short name T932
Test name
Test status
Simulation time 184372764 ps
CPU time 1.11 seconds
Started Jul 02 07:31:38 AM PDT 24
Finished Jul 02 07:31:41 AM PDT 24
Peak memory 196088 kb
Host smart-02714a8e-5b93-48e4-aec2-b39f154899a9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158489051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.158489051
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2493424105
Short name T880
Test name
Test status
Simulation time 122266914 ps
CPU time 1.23 seconds
Started Jul 02 07:36:48 AM PDT 24
Finished Jul 02 07:36:55 AM PDT 24
Peak memory 195988 kb
Host smart-325c3679-13d0-499d-a827-4f816f7a8e40
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2493424105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.2493424105
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2130339202
Short name T874
Test name
Test status
Simulation time 133719841 ps
CPU time 1.2 seconds
Started Jul 02 07:36:48 AM PDT 24
Finished Jul 02 07:36:55 AM PDT 24
Peak memory 196080 kb
Host smart-d14979d7-c050-4f7a-8a06-21ef3b3a8a24
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130339202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2130339202
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2027408052
Short name T876
Test name
Test status
Simulation time 103765432 ps
CPU time 1.24 seconds
Started Jul 02 07:31:47 AM PDT 24
Finished Jul 02 07:31:49 AM PDT 24
Peak memory 197224 kb
Host smart-26e54e62-9247-41d7-a02c-1396d6fb712d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2027408052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2027408052
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1263283661
Short name T850
Test name
Test status
Simulation time 285002333 ps
CPU time 1.24 seconds
Started Jul 02 07:34:48 AM PDT 24
Finished Jul 02 07:34:50 AM PDT 24
Peak memory 197164 kb
Host smart-c431bd46-7497-43b2-8575-36ee83af6657
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263283661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1263283661
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.137353726
Short name T857
Test name
Test status
Simulation time 59990712 ps
CPU time 1.07 seconds
Started Jul 02 07:32:22 AM PDT 24
Finished Jul 02 07:32:23 AM PDT 24
Peak memory 197280 kb
Host smart-4f5f7888-bf34-4409-bad7-ad615b3e4387
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=137353726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.137353726
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1800106649
Short name T872
Test name
Test status
Simulation time 31589328 ps
CPU time 1.06 seconds
Started Jul 02 07:33:43 AM PDT 24
Finished Jul 02 07:33:45 AM PDT 24
Peak memory 196872 kb
Host smart-c6e9c067-c108-4c29-bbcc-92286855a4a1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800106649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1800106649
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2232192632
Short name T933
Test name
Test status
Simulation time 231757496 ps
CPU time 1.04 seconds
Started Jul 02 07:34:31 AM PDT 24
Finished Jul 02 07:34:33 AM PDT 24
Peak memory 194376 kb
Host smart-5e400b20-c1b5-4e69-93e7-7ed0df7e3476
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2232192632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2232192632
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3923363657
Short name T858
Test name
Test status
Simulation time 125039655 ps
CPU time 1.17 seconds
Started Jul 02 07:37:34 AM PDT 24
Finished Jul 02 07:37:47 AM PDT 24
Peak memory 197768 kb
Host smart-28d78ed5-1a00-4813-92a3-a2c53419da24
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923363657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3923363657
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2210613487
Short name T894
Test name
Test status
Simulation time 189846644 ps
CPU time 1.16 seconds
Started Jul 02 07:36:56 AM PDT 24
Finished Jul 02 07:36:59 AM PDT 24
Peak memory 195100 kb
Host smart-7988fd32-57dd-4494-ac1f-3191d70d83de
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2210613487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2210613487
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.146957620
Short name T907
Test name
Test status
Simulation time 151275435 ps
CPU time 1.33 seconds
Started Jul 02 07:36:57 AM PDT 24
Finished Jul 02 07:36:59 AM PDT 24
Peak memory 195808 kb
Host smart-7755b8f3-0551-414b-9cae-efc264a9e266
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146957620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.146957620
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.4089473546
Short name T842
Test name
Test status
Simulation time 81884326 ps
CPU time 1.09 seconds
Started Jul 02 07:33:22 AM PDT 24
Finished Jul 02 07:33:23 AM PDT 24
Peak memory 198628 kb
Host smart-ffd2492f-dab1-4624-bcc4-4ccc7f0f3a2b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4089473546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.4089473546
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.341154588
Short name T848
Test name
Test status
Simulation time 147808496 ps
CPU time 1.43 seconds
Started Jul 02 07:32:15 AM PDT 24
Finished Jul 02 07:32:17 AM PDT 24
Peak memory 197676 kb
Host smart-209ceb90-a61e-4dbc-9bb0-eb0310df0dfc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341154588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.341154588
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1227429353
Short name T855
Test name
Test status
Simulation time 46204008 ps
CPU time 0.92 seconds
Started Jul 02 07:33:05 AM PDT 24
Finished Jul 02 07:33:06 AM PDT 24
Peak memory 196752 kb
Host smart-6ffc737f-83df-4adc-aafb-258309a60bd8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1227429353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1227429353
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.716232632
Short name T863
Test name
Test status
Simulation time 150755855 ps
CPU time 0.92 seconds
Started Jul 02 07:33:43 AM PDT 24
Finished Jul 02 07:33:46 AM PDT 24
Peak memory 198472 kb
Host smart-6cb06b91-52d8-46f3-8027-5f6cc873bcd3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716232632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.716232632
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.448402603
Short name T915
Test name
Test status
Simulation time 64850243 ps
CPU time 1.2 seconds
Started Jul 02 07:37:26 AM PDT 24
Finished Jul 02 07:37:35 AM PDT 24
Peak memory 197308 kb
Host smart-497b1fff-2ce1-4cd9-a5ae-1a364b6b4a24
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=448402603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.448402603
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1006831530
Short name T861
Test name
Test status
Simulation time 129956690 ps
CPU time 0.86 seconds
Started Jul 02 07:33:49 AM PDT 24
Finished Jul 02 07:33:50 AM PDT 24
Peak memory 198096 kb
Host smart-ec12a051-8b88-4329-b3a4-b689a43d7152
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006831530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1006831530
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2594005201
Short name T905
Test name
Test status
Simulation time 238549709 ps
CPU time 1.14 seconds
Started Jul 02 07:36:31 AM PDT 24
Finished Jul 02 07:36:38 AM PDT 24
Peak memory 195092 kb
Host smart-af58d9ec-f64c-409a-ba99-250a234449fa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2594005201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2594005201
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1866771531
Short name T934
Test name
Test status
Simulation time 93375279 ps
CPU time 1.35 seconds
Started Jul 02 07:37:26 AM PDT 24
Finished Jul 02 07:37:35 AM PDT 24
Peak memory 196820 kb
Host smart-72093925-55b9-4493-bce5-1c6e910279f0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866771531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1866771531
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2990281294
Short name T918
Test name
Test status
Simulation time 39809449 ps
CPU time 1.01 seconds
Started Jul 02 07:37:25 AM PDT 24
Finished Jul 02 07:37:34 AM PDT 24
Peak memory 198088 kb
Host smart-a85d4e22-6d97-48c9-a320-c9c0ff8b329e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2990281294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.2990281294
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.199172
Short name T879
Test name
Test status
Simulation time 34661182 ps
CPU time 0.94 seconds
Started Jul 02 07:32:51 AM PDT 24
Finished Jul 02 07:32:53 AM PDT 24
Peak memory 196852 kb
Host smart-2062f2a1-174e-4486-893e-3c2009937239
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_en_
cdc_prim.199172
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2228279807
Short name T867
Test name
Test status
Simulation time 83256256 ps
CPU time 0.94 seconds
Started Jul 02 07:34:33 AM PDT 24
Finished Jul 02 07:34:35 AM PDT 24
Peak memory 196700 kb
Host smart-79006f15-63b0-4cf3-bcc3-c40d981f46af
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2228279807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.2228279807
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2201440515
Short name T897
Test name
Test status
Simulation time 54394288 ps
CPU time 1.03 seconds
Started Jul 02 07:36:46 AM PDT 24
Finished Jul 02 07:36:54 AM PDT 24
Peak memory 196236 kb
Host smart-8d08e696-4714-44e5-b6e5-f0d04a07e613
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201440515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2201440515
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2452406467
Short name T878
Test name
Test status
Simulation time 48602330 ps
CPU time 1.04 seconds
Started Jul 02 07:37:17 AM PDT 24
Finished Jul 02 07:37:24 AM PDT 24
Peak memory 198116 kb
Host smart-be2545c9-16b3-41a3-9c57-d154e0e52d94
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2452406467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.2452406467
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2674856611
Short name T853
Test name
Test status
Simulation time 360398477 ps
CPU time 1.31 seconds
Started Jul 02 07:36:51 AM PDT 24
Finished Jul 02 07:36:57 AM PDT 24
Peak memory 196360 kb
Host smart-57306a20-1f5f-4c48-b3c9-4d900a71737d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674856611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2674856611
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.4189570609
Short name T891
Test name
Test status
Simulation time 79240024 ps
CPU time 1.26 seconds
Started Jul 02 07:37:16 AM PDT 24
Finished Jul 02 07:37:23 AM PDT 24
Peak memory 195552 kb
Host smart-de4fa444-b49e-4a3d-aff5-d11137af805b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4189570609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.4189570609
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3079670987
Short name T904
Test name
Test status
Simulation time 143593410 ps
CPU time 1.08 seconds
Started Jul 02 07:36:28 AM PDT 24
Finished Jul 02 07:36:32 AM PDT 24
Peak memory 196652 kb
Host smart-b6014968-8953-4769-ae41-693c7bad6b3d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079670987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3079670987
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.4248774166
Short name T873
Test name
Test status
Simulation time 56086866 ps
CPU time 1.13 seconds
Started Jul 02 07:36:51 AM PDT 24
Finished Jul 02 07:36:57 AM PDT 24
Peak memory 195464 kb
Host smart-88f27457-d175-4695-8961-58a0efe60e30
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4248774166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.4248774166
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2369828015
Short name T925
Test name
Test status
Simulation time 52034864 ps
CPU time 1.02 seconds
Started Jul 02 07:37:17 AM PDT 24
Finished Jul 02 07:37:24 AM PDT 24
Peak memory 195588 kb
Host smart-b1ffa2e9-c933-480e-8688-f6b0f188e264
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369828015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2369828015
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.4147346517
Short name T939
Test name
Test status
Simulation time 101520268 ps
CPU time 1.38 seconds
Started Jul 02 07:37:17 AM PDT 24
Finished Jul 02 07:37:24 AM PDT 24
Peak memory 196824 kb
Host smart-8020ece7-88ee-40aa-a8a6-4e2d6b6694ba
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4147346517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.4147346517
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3477922489
Short name T854
Test name
Test status
Simulation time 121589272 ps
CPU time 0.8 seconds
Started Jul 02 07:35:07 AM PDT 24
Finished Jul 02 07:35:09 AM PDT 24
Peak memory 196016 kb
Host smart-66112bbc-bf55-403a-9545-56870b4c28de
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477922489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3477922489
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2411766538
Short name T936
Test name
Test status
Simulation time 80480887 ps
CPU time 1 seconds
Started Jul 02 07:36:12 AM PDT 24
Finished Jul 02 07:36:14 AM PDT 24
Peak memory 195276 kb
Host smart-9fd42891-911f-4950-9aaf-afde4a7219bb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2411766538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.2411766538
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2332360894
Short name T922
Test name
Test status
Simulation time 73821571 ps
CPU time 1.13 seconds
Started Jul 02 07:32:19 AM PDT 24
Finished Jul 02 07:32:21 AM PDT 24
Peak memory 197092 kb
Host smart-caea0d3e-6caa-4cfa-871a-9b027326d646
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332360894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2332360894
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.531511818
Short name T846
Test name
Test status
Simulation time 50264575 ps
CPU time 1.04 seconds
Started Jul 02 07:36:20 AM PDT 24
Finished Jul 02 07:36:23 AM PDT 24
Peak memory 195828 kb
Host smart-03dbaaa9-4d04-4b42-bbb8-d39b3bba8e56
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=531511818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.531511818
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3487088157
Short name T898
Test name
Test status
Simulation time 68320480 ps
CPU time 1.15 seconds
Started Jul 02 07:37:41 AM PDT 24
Finished Jul 02 07:37:54 AM PDT 24
Peak memory 196336 kb
Host smart-9e6f8fdb-9688-47b0-b33f-eeaafe6c7cb8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487088157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3487088157
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1389859454
Short name T895
Test name
Test status
Simulation time 32798351 ps
CPU time 0.91 seconds
Started Jul 02 07:35:34 AM PDT 24
Finished Jul 02 07:35:36 AM PDT 24
Peak memory 196784 kb
Host smart-d99b0565-5ef9-441f-b6ec-5ed2857b608f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1389859454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1389859454
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.100947645
Short name T911
Test name
Test status
Simulation time 116368652 ps
CPU time 1.07 seconds
Started Jul 02 07:37:13 AM PDT 24
Finished Jul 02 07:37:17 AM PDT 24
Peak memory 196500 kb
Host smart-192c1c50-0501-4496-aded-9dfe1861ac13
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100947645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.100947645
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.788503265
Short name T931
Test name
Test status
Simulation time 30453002 ps
CPU time 0.79 seconds
Started Jul 02 07:34:34 AM PDT 24
Finished Jul 02 07:34:36 AM PDT 24
Peak memory 195672 kb
Host smart-7df38215-ed1e-4eb5-9428-c587b35799a3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=788503265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.788503265
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3027076211
Short name T913
Test name
Test status
Simulation time 72789569 ps
CPU time 1.13 seconds
Started Jul 02 07:35:29 AM PDT 24
Finished Jul 02 07:35:31 AM PDT 24
Peak memory 198640 kb
Host smart-ce4e3071-a311-4f63-89e4-1d6b55f1ac9a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027076211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3027076211
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2719688570
Short name T900
Test name
Test status
Simulation time 228865960 ps
CPU time 1.09 seconds
Started Jul 02 07:37:05 AM PDT 24
Finished Jul 02 07:37:08 AM PDT 24
Peak memory 195716 kb
Host smart-68245cfd-8c91-4608-b17d-6b10f37cfe1c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2719688570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2719688570
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2669931316
Short name T865
Test name
Test status
Simulation time 68292300 ps
CPU time 1.21 seconds
Started Jul 02 07:35:35 AM PDT 24
Finished Jul 02 07:35:38 AM PDT 24
Peak memory 198412 kb
Host smart-71c7ab46-b228-4e24-9724-bf0e9a0bc2c6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669931316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2669931316
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2377824177
Short name T921
Test name
Test status
Simulation time 146887521 ps
CPU time 0.99 seconds
Started Jul 02 07:37:20 AM PDT 24
Finished Jul 02 07:37:28 AM PDT 24
Peak memory 196980 kb
Host smart-ee85f91f-2bfd-4b11-a71b-30be83555cc4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2377824177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.2377824177
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3000656991
Short name T926
Test name
Test status
Simulation time 187612128 ps
CPU time 1.08 seconds
Started Jul 02 07:31:54 AM PDT 24
Finished Jul 02 07:31:56 AM PDT 24
Peak memory 196764 kb
Host smart-6fc43e3c-a4fd-446b-a280-354ebae74460
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000656991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3000656991
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2315924995
Short name T890
Test name
Test status
Simulation time 34832035 ps
CPU time 1.04 seconds
Started Jul 02 07:36:21 AM PDT 24
Finished Jul 02 07:36:24 AM PDT 24
Peak memory 196480 kb
Host smart-267a90e9-331f-4902-aa4c-dbb921a04885
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2315924995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2315924995
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4291299826
Short name T901
Test name
Test status
Simulation time 70027344 ps
CPU time 1.27 seconds
Started Jul 02 07:36:27 AM PDT 24
Finished Jul 02 07:36:30 AM PDT 24
Peak memory 197500 kb
Host smart-fea52ff4-691a-4906-84e2-c5429d3f588a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291299826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4291299826
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3335689123
Short name T896
Test name
Test status
Simulation time 38060706 ps
CPU time 1.05 seconds
Started Jul 02 07:32:50 AM PDT 24
Finished Jul 02 07:32:51 AM PDT 24
Peak memory 196808 kb
Host smart-9e4af570-dac3-4700-b9c8-d1b50372217a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3335689123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.3335689123
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1202677614
Short name T909
Test name
Test status
Simulation time 198767947 ps
CPU time 1.45 seconds
Started Jul 02 07:35:20 AM PDT 24
Finished Jul 02 07:35:22 AM PDT 24
Peak memory 196816 kb
Host smart-7c50b3a3-f616-451d-a8af-00ce53d0f101
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202677614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1202677614
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.412805924
Short name T883
Test name
Test status
Simulation time 37666371 ps
CPU time 1 seconds
Started Jul 02 07:36:35 AM PDT 24
Finished Jul 02 07:36:43 AM PDT 24
Peak memory 196988 kb
Host smart-e85e8816-25b1-4aea-a7fe-1391b8b93246
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=412805924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.412805924
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3391221333
Short name T886
Test name
Test status
Simulation time 74071464 ps
CPU time 1.36 seconds
Started Jul 02 07:36:19 AM PDT 24
Finished Jul 02 07:36:22 AM PDT 24
Peak memory 197272 kb
Host smart-5fdf18b7-845f-4c8d-acfd-e781ac5c6569
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391221333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3391221333
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2556016006
Short name T893
Test name
Test status
Simulation time 61542957 ps
CPU time 1.08 seconds
Started Jul 02 07:36:19 AM PDT 24
Finished Jul 02 07:36:22 AM PDT 24
Peak memory 196136 kb
Host smart-ea1c0649-05cd-4325-85d1-5fc662a74085
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2556016006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2556016006
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3942706051
Short name T877
Test name
Test status
Simulation time 68649329 ps
CPU time 1.07 seconds
Started Jul 02 07:36:27 AM PDT 24
Finished Jul 02 07:36:29 AM PDT 24
Peak memory 196764 kb
Host smart-e70f689e-a0ab-49f7-a531-b51899b18b72
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942706051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3942706051
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2515242552
Short name T844
Test name
Test status
Simulation time 165163255 ps
CPU time 1.15 seconds
Started Jul 02 07:33:34 AM PDT 24
Finished Jul 02 07:33:35 AM PDT 24
Peak memory 196836 kb
Host smart-d07c4a10-0e62-48a1-b509-6c68a0fc36d5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2515242552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2515242552
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1533265284
Short name T929
Test name
Test status
Simulation time 122288379 ps
CPU time 0.92 seconds
Started Jul 02 07:36:27 AM PDT 24
Finished Jul 02 07:36:29 AM PDT 24
Peak memory 196812 kb
Host smart-7a0112d4-d720-4a4c-988d-ef0e315a565b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533265284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1533265284
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2335203895
Short name T902
Test name
Test status
Simulation time 17864580 ps
CPU time 0.74 seconds
Started Jul 02 07:37:26 AM PDT 24
Finished Jul 02 07:37:35 AM PDT 24
Peak memory 195424 kb
Host smart-099db8db-ddef-45ca-b495-86d917bb2f66
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2335203895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2335203895
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3679877190
Short name T888
Test name
Test status
Simulation time 82135811 ps
CPU time 1.07 seconds
Started Jul 02 07:36:34 AM PDT 24
Finished Jul 02 07:36:42 AM PDT 24
Peak memory 196412 kb
Host smart-319d24e3-c6fc-41dd-ba4b-0a73232f6425
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679877190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3679877190
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1609367467
Short name T866
Test name
Test status
Simulation time 96012701 ps
CPU time 0.76 seconds
Started Jul 02 07:36:34 AM PDT 24
Finished Jul 02 07:36:42 AM PDT 24
Peak memory 194788 kb
Host smart-f234fd2a-80b3-4f5f-aea0-78d6f15049ac
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1609367467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1609367467
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1120649406
Short name T884
Test name
Test status
Simulation time 479895082 ps
CPU time 1.18 seconds
Started Jul 02 07:36:33 AM PDT 24
Finished Jul 02 07:36:41 AM PDT 24
Peak memory 195556 kb
Host smart-b3e91917-de7a-4450-a995-93a214e34caf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120649406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1120649406
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1762302207
Short name T889
Test name
Test status
Simulation time 65949341 ps
CPU time 1.17 seconds
Started Jul 02 07:38:14 AM PDT 24
Finished Jul 02 07:38:34 AM PDT 24
Peak memory 195904 kb
Host smart-330daefa-8f28-4a78-b2ec-0721c1103f34
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1762302207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1762302207
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1954945571
Short name T892
Test name
Test status
Simulation time 104078400 ps
CPU time 1.12 seconds
Started Jul 02 07:33:50 AM PDT 24
Finished Jul 02 07:33:52 AM PDT 24
Peak memory 197028 kb
Host smart-a101d70e-d18a-4950-9879-3b461d8f6eea
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954945571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1954945571
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1952334881
Short name T870
Test name
Test status
Simulation time 167066540 ps
CPU time 0.93 seconds
Started Jul 02 07:37:03 AM PDT 24
Finished Jul 02 07:37:05 AM PDT 24
Peak memory 196272 kb
Host smart-c5605b60-bcab-4222-aa02-d10d1f8d9891
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1952334881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1952334881
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.720945870
Short name T862
Test name
Test status
Simulation time 160470634 ps
CPU time 1.14 seconds
Started Jul 02 07:37:17 AM PDT 24
Finished Jul 02 07:37:24 AM PDT 24
Peak memory 196144 kb
Host smart-d1159ba9-1931-4b2b-a13a-c810fd76b221
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720945870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.720945870
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.258054141
Short name T920
Test name
Test status
Simulation time 196296244 ps
CPU time 1 seconds
Started Jul 02 07:36:38 AM PDT 24
Finished Jul 02 07:36:47 AM PDT 24
Peak memory 196912 kb
Host smart-63533e6a-d0d6-4af5-a6f5-5c86e6f6d8f4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=258054141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.258054141
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.171526352
Short name T843
Test name
Test status
Simulation time 200741807 ps
CPU time 0.9 seconds
Started Jul 02 07:36:38 AM PDT 24
Finished Jul 02 07:36:47 AM PDT 24
Peak memory 195424 kb
Host smart-38f032b2-edc1-484e-8c52-16cf652b1b89
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171526352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.171526352
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1251495688
Short name T927
Test name
Test status
Simulation time 41512046 ps
CPU time 1.12 seconds
Started Jul 02 07:36:37 AM PDT 24
Finished Jul 02 07:36:47 AM PDT 24
Peak memory 195728 kb
Host smart-a55bec73-c39f-4e82-a281-a34d7bcad7d5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1251495688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1251495688
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2894416131
Short name T938
Test name
Test status
Simulation time 37789070 ps
CPU time 1.03 seconds
Started Jul 02 07:37:17 AM PDT 24
Finished Jul 02 07:37:24 AM PDT 24
Peak memory 196132 kb
Host smart-3a70049a-eacd-4242-ae1b-9594f090543c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894416131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2894416131
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2982595725
Short name T887
Test name
Test status
Simulation time 67503267 ps
CPU time 1.22 seconds
Started Jul 02 07:36:31 AM PDT 24
Finished Jul 02 07:36:38 AM PDT 24
Peak memory 196756 kb
Host smart-f64e1578-3081-4fab-9c25-3ec4ba703e75
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2982595725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2982595725
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3111749532
Short name T899
Test name
Test status
Simulation time 116863464 ps
CPU time 1.15 seconds
Started Jul 02 07:37:25 AM PDT 24
Finished Jul 02 07:37:35 AM PDT 24
Peak memory 196904 kb
Host smart-663aeba8-c161-4f34-92e0-dc675a736add
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111749532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3111749532
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1651345555
Short name T849
Test name
Test status
Simulation time 88478060 ps
CPU time 0.97 seconds
Started Jul 02 07:37:27 AM PDT 24
Finished Jul 02 07:37:36 AM PDT 24
Peak memory 195732 kb
Host smart-24a442f4-9710-4f3b-89cc-b31279b82fc9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1651345555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1651345555
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3573892270
Short name T914
Test name
Test status
Simulation time 33546524 ps
CPU time 0.97 seconds
Started Jul 02 07:36:31 AM PDT 24
Finished Jul 02 07:36:38 AM PDT 24
Peak memory 197876 kb
Host smart-75f2fc78-fc43-4694-9666-d8ee9f00eea7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573892270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3573892270
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1253953892
Short name T881
Test name
Test status
Simulation time 49597010 ps
CPU time 1.27 seconds
Started Jul 02 07:37:19 AM PDT 24
Finished Jul 02 07:37:26 AM PDT 24
Peak memory 197284 kb
Host smart-7686f1af-66fd-46da-8505-414d55576bd6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1253953892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1253953892
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1956114635
Short name T908
Test name
Test status
Simulation time 183759197 ps
CPU time 1.01 seconds
Started Jul 02 07:37:16 AM PDT 24
Finished Jul 02 07:37:22 AM PDT 24
Peak memory 198232 kb
Host smart-4e58899a-7c4f-468a-8171-4f42c5e1f4c6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956114635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1956114635
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2740889897
Short name T906
Test name
Test status
Simulation time 31778256 ps
CPU time 0.77 seconds
Started Jul 02 07:37:35 AM PDT 24
Finished Jul 02 07:37:47 AM PDT 24
Peak memory 195556 kb
Host smart-639a977c-63d3-4c42-bfc2-ed5a3c2854b4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2740889897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2740889897
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.6448447
Short name T930
Test name
Test status
Simulation time 74890374 ps
CPU time 1.19 seconds
Started Jul 02 07:37:19 AM PDT 24
Finished Jul 02 07:37:27 AM PDT 24
Peak memory 198388 kb
Host smart-0c7f7ebe-3809-42ff-ba5e-1162db713381
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6448447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.6448447
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.775176067
Short name T852
Test name
Test status
Simulation time 21378210 ps
CPU time 0.74 seconds
Started Jul 02 07:37:29 AM PDT 24
Finished Jul 02 07:37:39 AM PDT 24
Peak memory 195536 kb
Host smart-322213cc-2180-4a7b-9012-b85a0c7ef1eb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=775176067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.775176067
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1643478026
Short name T875
Test name
Test status
Simulation time 60398138 ps
CPU time 1.06 seconds
Started Jul 02 07:37:16 AM PDT 24
Finished Jul 02 07:37:22 AM PDT 24
Peak memory 198316 kb
Host smart-46001a44-191d-4c76-836b-75976fef62d3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643478026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1643478026
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3235764697
Short name T847
Test name
Test status
Simulation time 140951308 ps
CPU time 1.13 seconds
Started Jul 02 07:37:17 AM PDT 24
Finished Jul 02 07:37:23 AM PDT 24
Peak memory 196864 kb
Host smart-b2633e13-549a-4820-855a-c9612577a7e9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3235764697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3235764697
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2703281053
Short name T860
Test name
Test status
Simulation time 153532507 ps
CPU time 0.91 seconds
Started Jul 02 07:37:21 AM PDT 24
Finished Jul 02 07:37:30 AM PDT 24
Peak memory 196812 kb
Host smart-d2f05ebf-1c5f-4e84-9410-1e9f7b5ab55a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703281053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2703281053
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2912112958
Short name T869
Test name
Test status
Simulation time 26786012 ps
CPU time 0.86 seconds
Started Jul 02 07:37:19 AM PDT 24
Finished Jul 02 07:37:27 AM PDT 24
Peak memory 196892 kb
Host smart-2554e568-4e83-4b37-91cc-e710e03e1b02
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2912112958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2912112958
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2522492728
Short name T924
Test name
Test status
Simulation time 167725754 ps
CPU time 0.91 seconds
Started Jul 02 07:37:17 AM PDT 24
Finished Jul 02 07:37:24 AM PDT 24
Peak memory 196848 kb
Host smart-64fab906-75aa-4c70-a051-734b0d4f0edd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522492728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2522492728
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1788022573
Short name T871
Test name
Test status
Simulation time 71888002 ps
CPU time 1.32 seconds
Started Jul 02 07:33:47 AM PDT 24
Finished Jul 02 07:33:49 AM PDT 24
Peak memory 197924 kb
Host smart-fd7bcb6b-229e-4c4e-a7d3-8e0f7248cd23
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1788022573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1788022573
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3868064608
Short name T856
Test name
Test status
Simulation time 54893890 ps
CPU time 1.36 seconds
Started Jul 02 07:38:09 AM PDT 24
Finished Jul 02 07:38:27 AM PDT 24
Peak memory 196888 kb
Host smart-233ab274-43a2-4823-a39d-159e870d173f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868064608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3868064608
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.731173846
Short name T937
Test name
Test status
Simulation time 52601113 ps
CPU time 0.99 seconds
Started Jul 02 07:32:51 AM PDT 24
Finished Jul 02 07:32:53 AM PDT 24
Peak memory 198144 kb
Host smart-d968eb4a-7192-4eaf-b601-ecc3f0136269
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=731173846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.731173846
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2284496721
Short name T851
Test name
Test status
Simulation time 268729635 ps
CPU time 1.22 seconds
Started Jul 02 07:36:17 AM PDT 24
Finished Jul 02 07:36:19 AM PDT 24
Peak memory 196464 kb
Host smart-d381de23-5f4b-4b6e-9837-21db71677fd8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284496721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2284496721
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3785777795
Short name T885
Test name
Test status
Simulation time 441500739 ps
CPU time 1.01 seconds
Started Jul 02 07:36:40 AM PDT 24
Finished Jul 02 07:36:49 AM PDT 24
Peak memory 196916 kb
Host smart-3d171555-1d11-4b19-995f-5e1e047ce2ab
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3785777795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.3785777795
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.870456165
Short name T910
Test name
Test status
Simulation time 44355936 ps
CPU time 1.15 seconds
Started Jul 02 07:33:46 AM PDT 24
Finished Jul 02 07:33:48 AM PDT 24
Peak memory 196876 kb
Host smart-f9ee73ae-a56a-4ea7-959a-ff5f02022792
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870456165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.870456165
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.99841422
Short name T882
Test name
Test status
Simulation time 68417830 ps
CPU time 1.16 seconds
Started Jul 02 07:35:39 AM PDT 24
Finished Jul 02 07:35:41 AM PDT 24
Peak memory 198324 kb
Host smart-b2772b1c-8455-4ef6-ba3f-72ad8c3f6253
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=99841422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.99841422
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3765341793
Short name T912
Test name
Test status
Simulation time 31111348 ps
CPU time 0.92 seconds
Started Jul 02 07:36:17 AM PDT 24
Finished Jul 02 07:36:19 AM PDT 24
Peak memory 196428 kb
Host smart-419220ba-5cbd-448a-8b2b-5983ab2e60d6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765341793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3765341793
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3380578905
Short name T859
Test name
Test status
Simulation time 39974613 ps
CPU time 0.89 seconds
Started Jul 02 07:35:33 AM PDT 24
Finished Jul 02 07:35:34 AM PDT 24
Peak memory 196112 kb
Host smart-34eafee2-a1e6-46ee-851a-3da948a7cc6e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3380578905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3380578905
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3972667624
Short name T917
Test name
Test status
Simulation time 185498390 ps
CPU time 0.99 seconds
Started Jul 02 07:35:53 AM PDT 24
Finished Jul 02 07:35:55 AM PDT 24
Peak memory 196232 kb
Host smart-8bdb408d-03c0-4d1c-8839-5e507ba779e4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972667624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3972667624
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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