Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	5349325	1			T33	112		T1	53		T11	100
all_pins[1]	5349325	1			T33	112		T1	53		T11	100
all_pins[2]	5349325	1			T33	112		T1	53		T11	100
all_pins[3]	5349325	1			T33	112		T1	53		T11	100
all_pins[4]	5349325	1			T33	112		T1	53		T11	100
all_pins[5]	5349325	1			T33	112		T1	53		T11	100
all_pins[6]	5349325	1			T33	112		T1	53		T11	100
all_pins[7]	5349325	1			T33	112		T1	53		T11	100
all_pins[8]	5349325	1			T33	112		T1	53		T11	100
all_pins[9]	5349325	1			T33	112		T1	53		T11	100
all_pins[10]	5349325	1			T33	112		T1	53		T11	100
all_pins[11]	5349325	1			T33	112		T1	53		T11	100
all_pins[12]	5349325	1			T33	112		T1	53		T11	100
all_pins[13]	5349325	1			T33	112		T1	53		T11	100
all_pins[14]	5349325	1			T33	112		T1	53		T11	100
all_pins[15]	5349325	1			T33	112		T1	53		T11	100
all_pins[16]	5349325	1			T33	112		T1	53		T11	100
all_pins[17]	5349325	1			T33	112		T1	53		T11	100
all_pins[18]	5349325	1			T33	112		T1	53		T11	100
all_pins[19]	5349325	1			T33	112		T1	53		T11	100
all_pins[20]	5349325	1			T33	112		T1	53		T11	100
all_pins[21]	5349325	1			T33	112		T1	53		T11	100
all_pins[22]	5349325	1			T33	112		T1	53		T11	100
all_pins[23]	5349325	1			T33	112		T1	53		T11	100
all_pins[24]	5349325	1			T33	112		T1	53		T11	100
all_pins[25]	5349325	1			T33	112		T1	53		T11	100
all_pins[26]	5349325	1			T33	112		T1	53		T11	100
all_pins[27]	5349325	1			T33	112		T1	53		T11	100
all_pins[28]	5349325	1			T33	112		T1	53		T11	100
all_pins[29]	5349325	1			T33	112		T1	53		T11	100
all_pins[30]	5349325	1			T33	112		T1	53		T11	100
all_pins[31]	5349325	1			T33	112		T1	53		T11	100

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	106332074	1			T33	2374		T1	1358		T11	1679
values[0x1]	64846326	1			T33	1210		T1	338		T11	1521
transitions[0x0=>0x1]	38880833	1			T33	753		T1	225		T11	773
transitions[0x1=>0x0]	38880671	1			T33	753		T1	225		T11	772

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3322019	1			T33	64		T1	44		T11	52
all_pins[0]	values[0x1]	2027306	1			T33	48		T1	9		T11	48
all_pins[0]	transitions[0x0=>0x1]	1254293	1			T33	36		T1	2		T11	24
all_pins[0]	transitions[0x1=>0x0]	1255865	1			T33	9		T1	4		T11	30
all_pins[1]	values[0x0]	3328713	1			T33	74		T1	31		T11	58
all_pins[1]	values[0x1]	2020612	1			T33	38		T1	22		T11	42
all_pins[1]	transitions[0x0=>0x1]	1207731	1			T33	20		T1	19		T11	19
all_pins[1]	transitions[0x1=>0x0]	1214425	1			T33	30		T1	6		T11	25
all_pins[2]	values[0x0]	3317993	1			T33	83		T1	38		T11	53
all_pins[2]	values[0x1]	2031332	1			T33	29		T1	15		T11	47
all_pins[2]	transitions[0x0=>0x1]	1217443	1			T33	19		T1	5		T11	27
all_pins[2]	transitions[0x1=>0x0]	1206723	1			T33	28		T1	12		T11	22
all_pins[3]	values[0x0]	3324251	1			T33	81		T1	44		T11	51
all_pins[3]	values[0x1]	2025074	1			T33	31		T1	9		T11	49
all_pins[3]	transitions[0x0=>0x1]	1209709	1			T33	23		T1	8		T11	27
all_pins[3]	transitions[0x1=>0x0]	1215967	1			T33	21		T1	14		T11	25
all_pins[4]	values[0x0]	3321441	1			T33	49		T1	43		T11	43
all_pins[4]	values[0x1]	2027884	1			T33	63		T1	10		T11	57
all_pins[4]	transitions[0x0=>0x1]	1213526	1			T33	47		T1	8		T11	29
all_pins[4]	transitions[0x1=>0x0]	1210716	1			T33	15		T1	7		T11	21
all_pins[5]	values[0x0]	3319149	1			T33	82		T1	40		T11	46
all_pins[5]	values[0x1]	2030176	1			T33	30		T1	13		T11	54
all_pins[5]	transitions[0x0=>0x1]	1214964	1			T33	19		T1	8		T11	25
all_pins[5]	transitions[0x1=>0x0]	1212672	1			T33	52		T1	5		T11	28
all_pins[6]	values[0x0]	3319625	1			T33	63		T1	39		T11	48
all_pins[6]	values[0x1]	2029700	1			T33	49		T1	14		T11	52
all_pins[6]	transitions[0x0=>0x1]	1215731	1			T33	36		T1	10		T11	21
all_pins[6]	transitions[0x1=>0x0]	1216207	1			T33	17		T1	9		T11	23
all_pins[7]	values[0x0]	3322110	1			T33	99		T1	43		T11	54
all_pins[7]	values[0x1]	2027215	1			T33	13		T1	10		T11	46
all_pins[7]	transitions[0x0=>0x1]	1211731	1			T33	13		T1	5		T11	21
all_pins[7]	transitions[0x1=>0x0]	1214216	1			T33	49		T1	9		T11	27
all_pins[8]	values[0x0]	3322388	1			T33	69		T1	45		T11	59
all_pins[8]	values[0x1]	2026937	1			T33	43		T1	8		T11	41
all_pins[8]	transitions[0x0=>0x1]	1215172	1			T33	36		T1	5		T11	22
all_pins[8]	transitions[0x1=>0x0]	1215450	1			T33	6		T1	7		T11	27
all_pins[9]	values[0x0]	3320088	1			T33	43		T1	39		T11	60
all_pins[9]	values[0x1]	2029237	1			T33	69		T1	14		T11	40
all_pins[9]	transitions[0x0=>0x1]	1214416	1			T33	39		T1	10		T11	22
all_pins[9]	transitions[0x1=>0x0]	1212116	1			T33	13		T1	4		T11	23
all_pins[10]	values[0x0]	3324083	1			T33	73		T1	44		T11	51
all_pins[10]	values[0x1]	2025242	1			T33	39		T1	9		T11	49
all_pins[10]	transitions[0x0=>0x1]	1212726	1			T33	11		T1	4		T11	26
all_pins[10]	transitions[0x1=>0x0]	1216721	1			T33	41		T1	9		T11	17
all_pins[11]	values[0x0]	3319176	1			T33	76		T1	48		T11	55
all_pins[11]	values[0x1]	2030149	1			T33	36		T1	5		T11	45
all_pins[11]	transitions[0x0=>0x1]	1215259	1			T33	25		T1	1		T11	18
all_pins[11]	transitions[0x1=>0x0]	1210352	1			T33	28		T1	5		T11	22
all_pins[12]	values[0x0]	3329379	1			T33	112		T1	39		T11	48
all_pins[12]	values[0x1]	2019946	1			T1	14		T11	52		T14	11670
all_pins[12]	transitions[0x0=>0x1]	1209536	1			T1	10		T11	29		T14	6850
all_pins[12]	transitions[0x1=>0x0]	1219739	1			T33	36		T1	1		T11	22
all_pins[13]	values[0x0]	3319704	1			T33	78		T1	45		T11	59
all_pins[13]	values[0x1]	2029621	1			T33	34		T1	8		T11	41
all_pins[13]	transitions[0x0=>0x1]	1217873	1			T33	34		T1	4		T11	20
all_pins[13]	transitions[0x1=>0x0]	1208198	1			T1	10		T11	31		T14	6625
all_pins[14]	values[0x0]	3317343	1			T33	80		T1	48		T11	50
all_pins[14]	values[0x1]	2031982	1			T33	32		T1	5		T11	50
all_pins[14]	transitions[0x0=>0x1]	1214395	1			T33	20		T1	5		T11	32
all_pins[14]	transitions[0x1=>0x0]	1212034	1			T33	22		T1	8		T11	23
all_pins[15]	values[0x0]	3319505	1			T33	53		T1	48		T11	53
all_pins[15]	values[0x1]	2029820	1			T33	59		T1	5		T11	47
all_pins[15]	transitions[0x0=>0x1]	1214800	1			T33	35		T1	4		T11	20
all_pins[15]	transitions[0x1=>0x0]	1216962	1			T33	8		T1	4		T11	23
all_pins[16]	values[0x0]	3331317	1			T33	75		T1	45		T11	53
all_pins[16]	values[0x1]	2018008	1			T33	37		T1	8		T11	47
all_pins[16]	transitions[0x0=>0x1]	1207013	1			T33	10		T1	8		T11	20
all_pins[16]	transitions[0x1=>0x0]	1218825	1			T33	32		T1	5		T11	20
all_pins[17]	values[0x0]	3321228	1			T33	86		T1	42		T11	56
all_pins[17]	values[0x1]	2028097	1			T33	26		T1	11		T11	44
all_pins[17]	transitions[0x0=>0x1]	1219570	1			T33	14		T1	10		T11	25
all_pins[17]	transitions[0x1=>0x0]	1209481	1			T33	25		T1	7		T11	28
all_pins[18]	values[0x0]	3318350	1			T33	55		T1	37		T11	48
all_pins[18]	values[0x1]	2030975	1			T33	57		T1	16		T11	52
all_pins[18]	transitions[0x0=>0x1]	1217743	1			T33	37		T1	12		T11	29
all_pins[18]	transitions[0x1=>0x0]	1214865	1			T33	6		T1	7		T11	21
all_pins[19]	values[0x0]	3321719	1			T33	70		T1	42		T11	39
all_pins[19]	values[0x1]	2027606	1			T33	42		T1	11		T11	61
all_pins[19]	transitions[0x0=>0x1]	1213088	1			T33	14		T1	4		T11	31
all_pins[19]	transitions[0x1=>0x0]	1216457	1			T33	29		T1	9		T11	22
all_pins[20]	values[0x0]	3324520	1			T33	77		T1	41		T11	49
all_pins[20]	values[0x1]	2024805	1			T33	35		T1	12		T11	51
all_pins[20]	transitions[0x0=>0x1]	1214746	1			T33	25		T1	5		T11	20
all_pins[20]	transitions[0x1=>0x0]	1217547	1			T33	32		T1	4		T11	30
all_pins[21]	values[0x0]	3327087	1			T33	70		T1	39		T11	59
all_pins[21]	values[0x1]	2022238	1			T33	42		T1	14		T11	41
all_pins[21]	transitions[0x0=>0x1]	1211096	1			T33	25		T1	10		T11	22
all_pins[21]	transitions[0x1=>0x0]	1213663	1			T33	18		T1	8		T11	32
all_pins[22]	values[0x0]	3322232	1			T33	88		T1	49		T11	49
all_pins[22]	values[0x1]	2027093	1			T33	24		T1	4		T11	51
all_pins[22]	transitions[0x0=>0x1]	1216489	1			T33	6		T1	4		T11	28
all_pins[22]	transitions[0x1=>0x0]	1211634	1			T33	24		T1	14		T11	18
all_pins[23]	values[0x0]	3328901	1			T33	85		T1	43		T11	49
all_pins[23]	values[0x1]	2020424	1			T33	27		T1	10		T11	51
all_pins[23]	transitions[0x0=>0x1]	1211401	1			T33	24		T1	10		T11	26
all_pins[23]	transitions[0x1=>0x0]	1218070	1			T33	21		T1	4		T11	26
all_pins[24]	values[0x0]	3327568	1			T33	63		T1	41		T11	58
all_pins[24]	values[0x1]	2021757	1			T33	49		T1	12		T11	42
all_pins[24]	transitions[0x0=>0x1]	1212977	1			T33	33		T1	5		T11	20
all_pins[24]	transitions[0x1=>0x0]	1211644	1			T33	11		T1	3		T11	29
all_pins[25]	values[0x0]	3320178	1			T33	63		T1	32		T11	60
all_pins[25]	values[0x1]	2029147	1			T33	49		T1	21		T11	40
all_pins[25]	transitions[0x0=>0x1]	1217479	1			T33	21		T1	14		T11	23
all_pins[25]	transitions[0x1=>0x0]	1210089	1			T33	21		T1	5		T11	25
all_pins[26]	values[0x0]	3327644	1			T33	72		T1	49		T11	62
all_pins[26]	values[0x1]	2021681	1			T33	40		T1	4		T11	38
all_pins[26]	transitions[0x0=>0x1]	1205735	1			T33	21		T1	1		T11	27
all_pins[26]	transitions[0x1=>0x0]	1213201	1			T33	30		T1	18		T11	29
all_pins[27]	values[0x0]	3323670	1			T33	87		T1	49		T11	44
all_pins[27]	values[0x1]	2025655	1			T33	25		T1	4		T11	56
all_pins[27]	transitions[0x0=>0x1]	1216363	1			T33	6		T1	4		T11	32
all_pins[27]	transitions[0x1=>0x0]	1212389	1			T33	21		T1	4		T11	14
all_pins[28]	values[0x0]	3328242	1			T33	64		T1	44		T11	54
all_pins[28]	values[0x1]	2021083	1			T33	48		T1	9		T11	46
all_pins[28]	transitions[0x0=>0x1]	1210887	1			T33	36		T1	9		T11	17
all_pins[28]	transitions[0x1=>0x0]	1215459	1			T33	13		T1	4		T11	27
all_pins[29]	values[0x0]	3320179	1			T33	84		T1	39		T11	55
all_pins[29]	values[0x1]	2029146	1			T33	28		T1	14		T11	45
all_pins[29]	transitions[0x0=>0x1]	1216223	1			T33	10		T1	9		T11	21
all_pins[29]	transitions[0x1=>0x0]	1208160	1			T33	30		T1	4		T11	22
all_pins[30]	values[0x0]	3321987	1			T33	65		T1	46		T11	59
all_pins[30]	values[0x1]	2027338	1			T33	47		T1	7		T11	41
all_pins[30]	transitions[0x0=>0x1]	1213731	1			T33	41		T1	4		T11	19
all_pins[30]	transitions[0x1=>0x0]	1215539	1			T33	22		T1	11		T11	23
all_pins[31]	values[0x0]	3320285	1			T33	91		T1	42		T11	45
all_pins[31]	values[0x1]	2029040	1			T33	21		T1	11		T11	55
all_pins[31]	transitions[0x0=>0x1]	1216987	1			T33	17		T1	8		T11	31
all_pins[31]	transitions[0x1=>0x0]	1215285	1			T33	43		T1	4		T11	17