Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17407915	1			T33	172		T1	79		T11	1733
all_values[1]	17407915	1			T33	172		T1	79		T11	1733
all_values[2]	17407915	1			T33	172		T1	79		T11	1733
all_values[3]	17407915	1			T33	172		T1	79		T11	1733
all_values[4]	17407915	1			T33	172		T1	79		T11	1733
all_values[5]	17407915	1			T33	172		T1	79		T11	1733
all_values[6]	17407915	1			T33	172		T1	79		T11	1733
all_values[7]	17407915	1			T33	172		T1	79		T11	1733
all_values[8]	17407915	1			T33	172		T1	79		T11	1733
all_values[9]	17407915	1			T33	172		T1	79		T11	1733
all_values[10]	17407915	1			T33	172		T1	79		T11	1733
all_values[11]	17407915	1			T33	172		T1	79		T11	1733
all_values[12]	17407915	1			T33	172		T1	79		T11	1733
all_values[13]	17407915	1			T33	172		T1	79		T11	1733
all_values[14]	17407915	1			T33	172		T1	79		T11	1733
all_values[15]	17407915	1			T33	172		T1	79		T11	1733
all_values[16]	17407915	1			T33	172		T1	79		T11	1733
all_values[17]	17407915	1			T33	172		T1	79		T11	1733
all_values[18]	17407915	1			T33	172		T1	79		T11	1733
all_values[19]	17407915	1			T33	172		T1	79		T11	1733
all_values[20]	17407915	1			T33	172		T1	79		T11	1733
all_values[21]	17407915	1			T33	172		T1	79		T11	1733
all_values[22]	17407915	1			T33	172		T1	79		T11	1733
all_values[23]	17407915	1			T33	172		T1	79		T11	1733
all_values[24]	17407915	1			T33	172		T1	79		T11	1733
all_values[25]	17407915	1			T33	172		T1	79		T11	1733
all_values[26]	17407915	1			T33	172		T1	79		T11	1733
all_values[27]	17407915	1			T33	172		T1	79		T11	1733
all_values[28]	17407915	1			T33	172		T1	79		T11	1733
all_values[29]	17407915	1			T33	172		T1	79		T11	1733
all_values[30]	17407915	1			T33	172		T1	79		T11	1733
all_values[31]	17407915	1			T33	172		T1	79		T11	1733

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

314080269

1

T33

2985

T1

1717

T11

55456

auto[1]

242973011

1

T33

2519

T1

811

T14

124512

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

117867985

1

T33

1273

T1

1482

T11

55456

auto[1]

439185295

1

T33

4231

T1

1046

T14

223464

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

550898788

1

T33

5504

T1

2401

T11

55456

auto[1]

6154492

1

T1

127

T14

23874

T34

256932

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2947626	1			T33	30		T1	38		T11	1733
all_values[0]	auto[0]	auto[0]	auto[1]	6755319	1			T33	46		T1	20		T14	35058
all_values[0]	auto[0]	auto[1]	auto[0]	727563	1			T33	11		T1	9		T14	4215
all_values[0]	auto[0]	auto[1]	auto[1]	6785168	1			T33	85		T1	8		T14	34293
all_values[0]	auto[1]	auto[0]	auto[1]	96049	1			T1	2		T14	352		T34	3967
all_values[0]	auto[1]	auto[1]	auto[1]	96190	1			T1	2		T14	409		T34	4078
all_values[1]	auto[0]	auto[0]	auto[0]	2955277	1			T33	26		T1	32		T11	1733
all_values[1]	auto[0]	auto[0]	auto[1]	6777598	1			T33	46		T1	2		T14	33790
all_values[1]	auto[0]	auto[1]	auto[0]	736287	1			T33	23		T1	15		T14	5028
all_values[1]	auto[0]	auto[1]	auto[1]	6746528	1			T33	77		T1	25		T14	34154
all_values[1]	auto[1]	auto[0]	auto[1]	96924	1			T1	2		T14	345		T34	3954
all_values[1]	auto[1]	auto[1]	auto[1]	95301	1			T1	3		T14	350		T34	4007
all_values[2]	auto[0]	auto[0]	auto[0]	2943986	1			T33	29		T1	31		T11	1733
all_values[2]	auto[0]	auto[0]	auto[1]	6784206	1			T33	77		T1	9		T14	33584
all_values[2]	auto[0]	auto[1]	auto[0]	726489	1			T33	13		T1	18		T14	4042
all_values[2]	auto[0]	auto[1]	auto[1]	6760523	1			T33	53		T1	18		T14	35616
all_values[2]	auto[1]	auto[0]	auto[1]	96306	1			T14	361		T34	3946		T72	4
all_values[2]	auto[1]	auto[1]	auto[1]	96405	1			T1	3		T14	366		T34	4079
all_values[3]	auto[0]	auto[0]	auto[0]	2951931	1			T33	23		T1	27		T11	1733
all_values[3]	auto[0]	auto[0]	auto[1]	6783175	1			T33	80		T1	17		T14	34955
all_values[3]	auto[0]	auto[1]	auto[0]	728792	1			T33	15		T1	19		T14	4422
all_values[3]	auto[0]	auto[1]	auto[1]	6751655	1			T33	54		T1	10		T14	33883
all_values[3]	auto[1]	auto[0]	auto[1]	96759	1			T1	5		T14	354		T34	3962
all_values[3]	auto[1]	auto[1]	auto[1]	95603	1			T1	1		T14	399		T34	4020
all_values[4]	auto[0]	auto[0]	auto[0]	2950185	1			T33	9		T1	35		T11	1733
all_values[4]	auto[0]	auto[0]	auto[1]	6753132	1			T33	43		T1	20		T14	35546
all_values[4]	auto[0]	auto[1]	auto[0]	729612	1			T33	11		T1	12		T14	3936
all_values[4]	auto[0]	auto[1]	auto[1]	6782241	1			T33	109		T1	9		T14	33721
all_values[4]	auto[1]	auto[0]	auto[1]	96479	1			T1	2		T14	394		T34	4027
all_values[4]	auto[1]	auto[1]	auto[1]	96266	1			T1	1		T14	365		T34	4009
all_values[5]	auto[0]	auto[0]	auto[0]	2937568	1			T33	35		T1	28		T11	1733
all_values[5]	auto[0]	auto[0]	auto[1]	6763503	1			T33	52		T1	20		T14	35594
all_values[5]	auto[0]	auto[1]	auto[0]	729907	1			T33	21		T1	8		T14	4201
all_values[5]	auto[0]	auto[1]	auto[1]	6784808	1			T33	64		T1	18		T14	33428
all_values[5]	auto[1]	auto[0]	auto[1]	96132	1			T1	5		T14	377		T34	4006
all_values[5]	auto[1]	auto[1]	auto[1]	95997	1			T14	362		T34	4107		T72	2
all_values[6]	auto[0]	auto[0]	auto[0]	2938067	1			T33	18		T1	26		T11	1733
all_values[6]	auto[0]	auto[0]	auto[1]	6740993	1			T33	47		T1	15		T14	32809
all_values[6]	auto[0]	auto[1]	auto[0]	736645	1			T33	21		T1	18		T14	4024
all_values[6]	auto[0]	auto[1]	auto[1]	6799407	1			T33	86		T1	16		T14	36476
all_values[6]	auto[1]	auto[0]	auto[1]	96581	1			T1	3		T14	387		T34	4069
all_values[6]	auto[1]	auto[1]	auto[1]	96222	1			T1	1		T14	345		T34	4043
all_values[7]	auto[0]	auto[0]	auto[0]	2954790	1			T33	17		T1	32		T11	1733
all_values[7]	auto[0]	auto[0]	auto[1]	6744668	1			T33	127		T1	16		T14	35747
all_values[7]	auto[0]	auto[1]	auto[0]	732049	1			T33	11		T1	12		T14	4298
all_values[7]	auto[0]	auto[1]	auto[1]	6784168	1			T33	17		T1	14		T14	32804
all_values[7]	auto[1]	auto[0]	auto[1]	96580	1			T1	3		T14	408		T34	3961
all_values[7]	auto[1]	auto[1]	auto[1]	95660	1			T1	2		T14	331		T34	4007
all_values[8]	auto[0]	auto[0]	auto[0]	2944759	1			T33	22		T1	40		T11	1733
all_values[8]	auto[0]	auto[0]	auto[1]	6774993	1			T33	68		T1	18		T14	35566
all_values[8]	auto[0]	auto[1]	auto[0]	723985	1			T33	25		T1	9		T14	4227
all_values[8]	auto[0]	auto[1]	auto[1]	6771241	1			T33	57		T1	7		T14	33578
all_values[8]	auto[1]	auto[0]	auto[1]	96184	1			T1	2		T14	383		T34	4012
all_values[8]	auto[1]	auto[1]	auto[1]	96753	1			T1	3		T14	382		T34	4032
all_values[9]	auto[0]	auto[0]	auto[0]	2956980	1			T33	11		T1	35		T11	1733
all_values[9]	auto[0]	auto[0]	auto[1]	6765053	1			T33	32		T1	17		T14	34661
all_values[9]	auto[0]	auto[1]	auto[0]	734094	1			T33	12		T1	4		T14	3825
all_values[9]	auto[0]	auto[1]	auto[1]	6758753	1			T33	117		T1	20		T14	34931
all_values[9]	auto[1]	auto[0]	auto[1]	96297	1			T1	3		T14	370		T34	3944
all_values[9]	auto[1]	auto[1]	auto[1]	96738	1			T14	341		T34	4161		T72	1
all_values[10]	auto[0]	auto[0]	auto[0]	2952096	1			T33	37		T1	42		T11	1733
all_values[10]	auto[0]	auto[0]	auto[1]	6780479	1			T33	60		T1	16		T14	33523
all_values[10]	auto[0]	auto[1]	auto[0]	743562	1			T33	13		T1	4		T14	4318
all_values[10]	auto[0]	auto[1]	auto[1]	6739756	1			T33	62		T1	14		T14	35426
all_values[10]	auto[1]	auto[0]	auto[1]	96152	1			T1	1		T14	376		T34	3897
all_values[10]	auto[1]	auto[1]	auto[1]	95870	1			T1	2		T14	354		T34	4117
all_values[11]	auto[0]	auto[0]	auto[0]	2947974	1			T33	17		T1	42		T11	1733
all_values[11]	auto[0]	auto[0]	auto[1]	6764178	1			T33	66		T1	10		T14	34712
all_values[11]	auto[0]	auto[1]	auto[0]	727091	1			T33	22		T1	16		T14	4183
all_values[11]	auto[0]	auto[1]	auto[1]	6776578	1			T33	67		T1	8		T14	34364
all_values[11]	auto[1]	auto[0]	auto[1]	96502	1			T1	2		T14	370		T34	4008
all_values[11]	auto[1]	auto[1]	auto[1]	95592	1			T1	1		T14	353		T34	4001
all_values[12]	auto[0]	auto[0]	auto[0]	2961652	1			T33	54		T1	39		T11	1733
all_values[12]	auto[0]	auto[0]	auto[1]	6766762	1			T33	112		T1	12		T14	35599
all_values[12]	auto[0]	auto[1]	auto[0]	735772	1			T33	6		T1	2		T14	4164
all_values[12]	auto[0]	auto[1]	auto[1]	6751843	1			T1	20		T14	33068		T15	1445
all_values[12]	auto[1]	auto[0]	auto[1]	95974	1			T1	2		T14	351		T34	3918
all_values[12]	auto[1]	auto[1]	auto[1]	95912	1			T1	4		T14	367		T34	4008
all_values[13]	auto[0]	auto[0]	auto[0]	2948790	1			T33	45		T1	29		T11	1733
all_values[13]	auto[0]	auto[0]	auto[1]	6769475	1			T33	48		T1	23		T14	34671
all_values[13]	auto[0]	auto[1]	auto[0]	732120	1			T33	19		T1	12		T14	3990
all_values[13]	auto[0]	auto[1]	auto[1]	6765502	1			T33	60		T1	11		T14	35021
all_values[13]	auto[1]	auto[0]	auto[1]	95857	1			T1	3		T14	356		T34	4007
all_values[13]	auto[1]	auto[1]	auto[1]	96171	1			T1	1		T14	412		T34	3979
all_values[14]	auto[0]	auto[0]	auto[0]	2954440	1			T33	43		T1	32		T11	1733
all_values[14]	auto[0]	auto[0]	auto[1]	6725447	1			T33	61		T1	23		T14	33930
all_values[14]	auto[0]	auto[1]	auto[0]	734604	1			T33	9		T1	16		T14	4339
all_values[14]	auto[0]	auto[1]	auto[1]	6801464	1			T33	59		T1	5		T14	35404
all_values[14]	auto[1]	auto[0]	auto[1]	96053	1			T1	2		T14	353		T34	3992
all_values[14]	auto[1]	auto[1]	auto[1]	95907	1			T1	1		T14	397		T34	4081
all_values[15]	auto[0]	auto[0]	auto[0]	2951808	1			T33	6		T1	46		T11	1733
all_values[15]	auto[0]	auto[0]	auto[1]	6772042	1			T33	67		T1	16		T14	34011
all_values[15]	auto[0]	auto[1]	auto[0]	729408	1			T33	10		T1	7		T14	4005
all_values[15]	auto[0]	auto[1]	auto[1]	6762660	1			T33	89		T1	7		T14	35056
all_values[15]	auto[1]	auto[0]	auto[1]	96654	1			T1	3		T14	341		T34	4196
all_values[15]	auto[1]	auto[1]	auto[1]	95343	1			T14	396		T34	3840		T72	1
all_values[16]	auto[0]	auto[0]	auto[0]	2957122	1			T33	18		T1	38		T11	1733
all_values[16]	auto[0]	auto[0]	auto[1]	6771469	1			T33	69		T1	13		T14	35517
all_values[16]	auto[0]	auto[1]	auto[0]	734587	1			T33	21		T1	13		T14	4172
all_values[16]	auto[0]	auto[1]	auto[1]	6752638	1			T33	64		T1	10		T14	33688
all_values[16]	auto[1]	auto[0]	auto[1]	96338	1			T1	3		T14	372		T34	4084
all_values[16]	auto[1]	auto[1]	auto[1]	95761	1			T1	2		T14	388		T34	4012
all_values[17]	auto[0]	auto[0]	auto[0]	2934707	1			T33	35		T1	28		T11	1733
all_values[17]	auto[0]	auto[0]	auto[1]	6782628	1			T33	91		T1	17		T14	31474
all_values[17]	auto[0]	auto[1]	auto[0]	738786	1			T33	9		T1	18		T14	4610
all_values[17]	auto[0]	auto[1]	auto[1]	6759461	1			T33	37		T1	12		T14	37643
all_values[17]	auto[1]	auto[0]	auto[1]	96398	1			T1	3		T14	360		T34	3899
all_values[17]	auto[1]	auto[1]	auto[1]	95935	1			T1	1		T14	386		T34	4203
all_values[18]	auto[0]	auto[0]	auto[0]	2939374	1			T33	23		T1	29		T11	1733
all_values[18]	auto[0]	auto[0]	auto[1]	6757733	1			T33	47		T1	11		T14	34802
all_values[18]	auto[0]	auto[1]	auto[0]	731876	1			T33	9		T1	12		T14	3914
all_values[18]	auto[0]	auto[1]	auto[1]	6786654	1			T33	93		T1	23		T14	34942
all_values[18]	auto[1]	auto[0]	auto[1]	96098	1			T1	2		T14	369		T34	3942
all_values[18]	auto[1]	auto[1]	auto[1]	96180	1			T1	2		T14	415		T34	4052
all_values[19]	auto[0]	auto[0]	auto[0]	2940710	1			T33	21		T1	49		T11	1733
all_values[19]	auto[0]	auto[0]	auto[1]	6762806	1			T33	68		T1	2		T14	33717
all_values[19]	auto[0]	auto[1]	auto[0]	736055	1			T33	2		T1	10		T14	4370
all_values[19]	auto[0]	auto[1]	auto[1]	6776025	1			T33	81		T1	16		T14	35154
all_values[19]	auto[1]	auto[0]	auto[1]	97022	1			T1	2		T14	363		T34	4066
all_values[19]	auto[1]	auto[1]	auto[1]	95297	1			T14	447		T34	3874		T72	1
all_values[20]	auto[0]	auto[0]	auto[0]	2955946	1			T33	30		T1	31		T11	1733
all_values[20]	auto[0]	auto[0]	auto[1]	6771487	1			T33	37		T1	11		T14	36122
all_values[20]	auto[0]	auto[1]	auto[0]	737568	1			T33	36		T1	19		T14	3959
all_values[20]	auto[0]	auto[1]	auto[1]	6750500	1			T33	69		T1	15		T14	33289
all_values[20]	auto[1]	auto[0]	auto[1]	96468	1			T1	2		T14	350		T34	4012
all_values[20]	auto[1]	auto[1]	auto[1]	95946	1			T1	1		T14	382		T34	3998
all_values[21]	auto[0]	auto[0]	auto[0]	2952816	1			T33	28		T1	30		T11	1733
all_values[21]	auto[0]	auto[0]	auto[1]	6796811	1			T33	68		T1	25		T14	37094
all_values[21]	auto[0]	auto[1]	auto[0]	723051	1			T33	4		T1	4		T14	4641
all_values[21]	auto[0]	auto[1]	auto[1]	6743170	1			T33	72		T1	16		T14	31644
all_values[21]	auto[1]	auto[0]	auto[1]	96417	1			T1	4		T14	409		T34	4054
all_values[21]	auto[1]	auto[1]	auto[1]	95650	1			T14	329		T34	4056		T72	3
all_values[22]	auto[0]	auto[0]	auto[0]	2952641	1			T33	31		T1	38		T11	1733
all_values[22]	auto[0]	auto[0]	auto[1]	6748200	1			T33	84		T1	27		T14	33971
all_values[22]	auto[0]	auto[1]	auto[0]	728163	1			T33	8		T1	5		T14	4135
all_values[22]	auto[0]	auto[1]	auto[1]	6786452	1			T33	49		T1	5		T14	34619
all_values[22]	auto[1]	auto[0]	auto[1]	96546	1			T1	2		T14	346		T34	3984
all_values[22]	auto[1]	auto[1]	auto[1]	95913	1			T1	2		T14	395		T34	4061
all_values[23]	auto[0]	auto[0]	auto[0]	2955947	1			T33	27		T1	35		T11	1733
all_values[23]	auto[0]	auto[0]	auto[1]	6782828	1			T33	93		T1	17		T14	34283
all_values[23]	auto[0]	auto[1]	auto[0]	721551	1			T33	7		T1	12		T14	3935
all_values[23]	auto[0]	auto[1]	auto[1]	6754459	1			T33	45		T1	12		T14	35036
all_values[23]	auto[1]	auto[0]	auto[1]	96951	1			T1	2		T14	385		T34	4058
all_values[23]	auto[1]	auto[1]	auto[1]	96179	1			T1	1		T14	375		T34	3970
all_values[24]	auto[0]	auto[0]	auto[0]	2956562	1			T33	14		T1	36		T11	1733
all_values[24]	auto[0]	auto[0]	auto[1]	6766420	1			T33	40		T1	18		T14	35148
all_values[24]	auto[0]	auto[1]	auto[0]	739402	1			T33	30		T1	6		T14	4417
all_values[24]	auto[0]	auto[1]	auto[1]	6753374	1			T33	88		T1	15		T14	33026
all_values[24]	auto[1]	auto[0]	auto[1]	96260	1			T1	4		T14	387		T34	3923
all_values[24]	auto[1]	auto[1]	auto[1]	95897	1			T14	342		T34	4023		T72	2
all_values[25]	auto[0]	auto[0]	auto[0]	2944739	1			T33	22		T1	32		T11	1733
all_values[25]	auto[0]	auto[0]	auto[1]	6772891	1			T33	67		T1	7		T14	34134
all_values[25]	auto[0]	auto[1]	auto[0]	733604	1			T33	6		T1	13		T14	3857
all_values[25]	auto[0]	auto[1]	auto[1]	6764986	1			T33	77		T1	24		T14	35768
all_values[25]	auto[1]	auto[0]	auto[1]	96641	1			T1	1		T14	411		T34	4015
all_values[25]	auto[1]	auto[1]	auto[1]	95054	1			T1	2		T14	370		T34	4057
all_values[26]	auto[0]	auto[0]	auto[0]	2956153	1			T33	30		T1	33		T11	1733
all_values[26]	auto[0]	auto[0]	auto[1]	6768232	1			T33	55		T1	24		T14	34360
all_values[26]	auto[0]	auto[1]	auto[0]	747510	1			T33	20		T1	13		T14	3931
all_values[26]	auto[0]	auto[1]	auto[1]	6743789	1			T33	67		T1	4		T14	35183
all_values[26]	auto[1]	auto[0]	auto[1]	96229	1			T1	5		T14	375		T34	4089
all_values[26]	auto[1]	auto[1]	auto[1]	96002	1			T14	359		T34	3877		T72	2
all_values[27]	auto[0]	auto[0]	auto[0]	2955133	1			T33	31		T1	35		T11	1733
all_values[27]	auto[0]	auto[0]	auto[1]	6792853	1			T33	98		T1	28		T14	35730
all_values[27]	auto[0]	auto[1]	auto[0]	728967	1			T33	4		T1	5		T14	3797
all_values[27]	auto[0]	auto[1]	auto[1]	6738519	1			T33	39		T1	7		T14	33841
all_values[27]	auto[1]	auto[0]	auto[1]	97036	1			T1	4		T14	405		T34	4105
all_values[27]	auto[1]	auto[1]	auto[1]	95407	1			T14	384		T34	3961		T72	1
all_values[28]	auto[0]	auto[0]	auto[0]	2955410	1			T33	25		T1	38		T11	1733
all_values[28]	auto[0]	auto[0]	auto[1]	6802064	1			T33	45		T1	4		T14	36525
all_values[28]	auto[0]	auto[1]	auto[0]	732254	1			T33	21		T1	20		T14	4268
all_values[28]	auto[0]	auto[1]	auto[1]	6725722	1			T33	81		T1	12		T14	32624
all_values[28]	auto[1]	auto[0]	auto[1]	97161	1			T1	4		T14	388		T34	4044
all_values[28]	auto[1]	auto[1]	auto[1]	95304	1			T1	1		T14	373		T34	4023
all_values[29]	auto[0]	auto[0]	auto[0]	2953507	1			T33	29		T1	41		T11	1733
all_values[29]	auto[0]	auto[0]	auto[1]	6759837	1			T33	71		T1	12		T14	36627
all_values[29]	auto[0]	auto[1]	auto[0]	734004	1			T33	24		T1	9		T14	3972
all_values[29]	auto[0]	auto[1]	auto[1]	6768176	1			T33	48		T1	14		T14	32558
all_values[29]	auto[1]	auto[0]	auto[1]	96456	1			T1	1		T14	364		T34	3933
all_values[29]	auto[1]	auto[1]	auto[1]	95935	1			T1	2		T14	376		T34	4053
all_values[30]	auto[0]	auto[0]	auto[0]	2956268	1			T33	7		T1	33		T11	1733
all_values[30]	auto[0]	auto[0]	auto[1]	6771594	1			T33	86		T1	22		T14	33702
all_values[30]	auto[0]	auto[1]	auto[0]	741262	1			T33	8		T1	11		T14	4693
all_values[30]	auto[0]	auto[1]	auto[1]	6746594	1			T33	71		T1	9		T14	34685
all_values[30]	auto[1]	auto[0]	auto[1]	96351	1			T1	3		T14	381		T34	4067
all_values[30]	auto[1]	auto[1]	auto[1]	95846	1			T1	1		T14	358		T34	4008
all_values[31]	auto[0]	auto[0]	auto[0]	2947476	1			T33	29		T1	49		T11	1733
all_values[31]	auto[0]	auto[0]	auto[1]	6752479	1			T33	112		T1	12		T14	34581
all_values[31]	auto[0]	auto[1]	auto[0]	738925	1			T1	2		T14	4040		T15	113
all_values[31]	auto[0]	auto[1]	auto[1]	6776634	1			T33	31		T1	11		T14	34303
all_values[31]	auto[1]	auto[0]	auto[1]	96619	1			T1	2		T14	365		T34	4040
all_values[31]	auto[1]	auto[1]	auto[1]	95782	1			T1	3		T14	358		T34	3954

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal