Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[1]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[2]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[3]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[4]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[5]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[6]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[7]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[8]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[9]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[10]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[11]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[12]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[13]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[14]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[15]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[16]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[17]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[18]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[19]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[20]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[21]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[22]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[23]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[24]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[25]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[26]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[27]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[28]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[29]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[30]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[31]	17099256	1			T33	111		T1	105		T11	1733

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

330844383

1

T33

1735

T1

1478

T11

27525

auto[1]

216331809

1

T33

1817

T1

1882

T11

27931

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

437731167

1

T33

3552

T1

3032

T11

55456

auto[1]

109445025

1

T1

328

T12

5675

T13

12209

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

405122169

1

T33

3552

T1

2391

T11

55456

auto[1]

142054023

1

T1

969

T12

5907

T13

12279

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	6370067	1			T33	64		T1	30		T11	833
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4565556	1			T33	47		T1	29		T11	900
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1723375	1			T12	108		T13	174		T14	7557
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2245479	1			T1	11		T12	84		T13	193
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	492390	1			T1	18		T14	12690		T17	10
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1702389	1			T1	17		T12	92		T13	218
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	6367413	1			T33	67		T1	25		T11	876
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4566717	1			T33	44		T1	47		T11	857
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1725055	1			T1	7		T12	90		T13	180
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2242914	1			T1	18		T12	93		T13	172
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	491930	1			T1	4		T14	12568		T17	7
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1705227	1			T1	4		T12	98		T13	212
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	6375079	1			T33	38		T1	27		T11	881
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4561714	1			T33	73		T1	40		T11	852
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1718533	1			T1	3		T12	90		T13	194
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2243213	1			T1	9		T12	101		T13	202
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	490775	1			T1	9		T14	12081		T17	9
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1709942	1			T1	17		T12	94		T13	214
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	6377041	1			T33	52		T1	24		T11	919
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4562528	1			T33	59		T1	31		T11	814
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1725837	1			T12	93		T13	177		T14	7510
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	2239066	1			T1	14		T12	76		T13	224
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	488643	1			T1	21		T14	12584		T17	4
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1706141	1			T1	15		T12	108		T13	208
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	6369526	1			T33	48		T1	46		T11	903
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4568991	1			T33	63		T1	30		T11	830
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1725487	1			T1	2		T12	64		T13	199
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2242499	1			T1	14		T12	104		T13	166
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	490738	1			T1	13		T14	12074		T17	10
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1702015	1			T12	100		T13	194		T14	7594
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	6366944	1			T33	61		T1	51		T11	875
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4571612	1			T33	50		T1	32		T11	858
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1721914	1			T1	2		T12	82		T13	211
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2243148	1			T1	17		T12	108		T13	182
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	490494	1			T1	2		T14	12032		T17	15
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1705144	1			T1	1		T12	95		T13	186
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	6368480	1			T33	53		T1	23		T11	842
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4568283	1			T33	58		T1	42		T11	891
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1720844	1			T1	5		T12	74		T13	199
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2246647	1			T1	13		T12	125		T13	186
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	490984	1			T1	13		T14	12717		T17	7
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1704018	1			T1	9		T12	86		T13	142
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	6369770	1			T33	49		T1	29		T11	925
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4560874	1			T33	62		T1	32		T11	808
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1716786	1			T1	8		T12	98		T13	176
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2251217	1			T1	4		T12	86		T13	200
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	492288	1			T1	17		T14	11964		T17	21
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1708321	1			T1	15		T12	82		T13	196
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	6363321	1			T33	65		T1	35		T11	870
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4578959	1			T33	46		T1	35		T11	863
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1723604	1			T12	100		T13	206		T14	7548
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2243978	1			T1	14		T12	118		T13	206
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	489944	1			T1	17		T14	12317		T17	10
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1699450	1			T1	4		T12	77		T13	138
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	6364206	1			T33	47		T1	25		T11	755
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4571619	1			T33	64		T1	63		T11	978
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1724103	1			T12	91		T13	206		T14	7437
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2241930	1			T1	10		T12	94		T13	178
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	492348	1			T1	6		T14	12376		T17	13
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1705050	1			T1	1		T12	78		T13	186
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	6375739	1			T33	54		T1	22		T11	1015
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4564026	1			T33	57		T1	57		T11	718
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1723095	1			T1	2		T12	82		T13	182
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2237324	1			T1	9		T12	113		T13	200
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	491903	1			T1	12		T14	12339		T17	10
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1707169	1			T1	3		T12	74		T13	203
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	6376928	1			T33	59		T1	32		T11	744
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4566943	1			T33	52		T1	22		T11	989
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1722889	1			T1	2		T12	68		T13	191
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2243144	1			T1	24		T12	98		T13	170
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	488103	1			T1	17		T14	12274		T17	5
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1701249	1			T1	8		T12	85		T13	186
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	6372648	1			T33	54		T1	16		T11	885
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4567099	1			T33	57		T1	62		T11	848
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1720551	1			T12	70		T13	176		T14	7594
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2241772	1			T1	9		T12	90		T13	223
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	492038	1			T1	11		T14	12347		T17	8
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1705148	1			T1	7		T12	74		T13	164
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	6373972	1			T33	50		T1	27		T11	854
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4562370	1			T33	61		T1	38		T11	879
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1722731	1			T1	2		T12	80		T13	176
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	2240542	1			T1	24		T12	91		T13	175
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	490701	1			T1	12		T14	12283		T17	7
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1708940	1			T1	2		T12	88		T13	192
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	6379838	1			T33	54		T1	14		T11	813
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4557034	1			T33	57		T1	48		T11	920
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1723074	1			T1	2		T12	85		T13	182
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	2248957	1			T1	20		T12	100		T13	177
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	489852	1			T1	18		T14	12033		T17	7
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1700501	1			T1	3		T12	88		T13	234
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	6373674	1			T33	57		T1	46		T11	957
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4566324	1			T33	54		T1	29		T11	776
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1716149	1			T1	8		T12	87		T13	182
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2247347	1			T1	11		T12	94		T13	170
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	491410	1			T1	3		T14	12074		T17	1
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1704352	1			T1	8		T12	118		T13	194
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	6369321	1			T33	61		T1	17		T11	844
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4578376	1			T33	50		T1	44		T11	889
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1713798	1			T1	1		T12	100		T13	191
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	2247381	1			T1	11		T12	82		T13	182
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	489372	1			T1	24		T14	12463		T17	11
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1701008	1			T1	8		T12	89		T13	202
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	6370442	1			T33	57		T1	38		T11	918
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4567467	1			T33	54		T1	28		T11	815
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1715177	1			T1	5		T12	118		T13	179
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2254088	1			T1	17		T12	76		T13	218
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	492049	1			T1	8		T14	12350		T17	10
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1700033	1			T1	9		T12	99		T13	222
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	6387736	1			T33	49		T1	29		T11	841
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4559709	1			T33	62		T1	41		T11	892
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1711595	1			T1	1		T12	68		T13	154
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2248825	1			T1	4		T12	112		T13	218
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	492724	1			T1	8		T14	12470		T17	9
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1698667	1			T1	22		T12	80		T13	210
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	6387058	1			T33	61		T1	34		T11	924
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4561699	1			T33	50		T1	34		T11	809
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1711820	1			T12	94		T13	198		T14	7348
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	2244617	1			T1	27		T12	86		T13	146
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	492030	1			T1	9		T14	12274		T17	8
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1702032	1			T1	1		T12	86		T13	210
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	6380269	1			T33	53		T1	33		T11	848
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4564467	1			T33	58		T1	44		T11	885
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1713138	1			T1	11		T12	108		T13	172
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2247287	1			T1	7		T12	76		T13	200
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	494312	1			T1	7		T14	12038		T17	9
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1699783	1			T1	3		T12	84		T13	212
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	6384259	1			T33	55		T1	45		T11	798
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4565167	1			T33	56		T1	29		T11	935
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1714915	1			T1	9		T12	79		T13	200
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2246236	1			T1	6		T12	98		T13	191
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	491597	1			T1	12		T14	12743		T17	16
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1697082	1			T1	4		T12	90		T13	196
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	6374304	1			T33	61		T1	38		T11	898
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4566559	1			T33	50		T1	36		T11	835
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1719319	1			T1	4		T12	96		T13	191
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2245433	1			T1	6		T12	91		T13	190
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	492408	1			T1	7		T14	12158		T17	6
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1701233	1			T1	14		T12	68		T13	186
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	6375148	1			T33	44		T1	27		T11	869
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4569417	1			T33	67		T1	37		T11	864
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1716907	1			T1	8		T12	104		T13	174
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	2246329	1			T1	19		T12	72		T13	198
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	492720	1			T1	10		T14	12484		T17	4
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1698735	1			T1	4		T12	96		T13	210
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	6374306	1			T33	59		T1	9		T11	822
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4571394	1			T33	52		T1	67		T11	911
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1718985	1			T1	6		T12	70		T13	219
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2246658	1			T1	2		T12	102		T13	170
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	490765	1			T1	17		T14	12494		T17	12
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1697148	1			T1	4		T12	118		T13	174
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	6376400	1			T33	44		T1	24		T11	870
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4575359	1			T33	67		T1	65		T11	863
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1718993	1			T1	6		T12	101		T13	216
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2242881	1			T1	4		T12	108		T13	170
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	490976	1			T1	4		T14	12083		T17	8
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1694647	1			T1	2		T12	72		T13	229
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	6380484	1			T33	52		T1	42		T11	870
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4561683	1			T33	59		T1	40		T11	863
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1715258	1			T1	3		T12	115		T13	168
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2247525	1			T1	8		T12	74		T13	179
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	491309	1			T1	5		T14	12416		T17	9
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1702997	1			T1	7		T12	54		T13	188
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	6374643	1			T33	51		T1	21		T11	800
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4565378	1			T33	60		T1	42		T11	933
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1718551	1			T1	1		T12	78		T13	186
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2249759	1			T1	7		T12	100		T13	178
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	490915	1			T1	18		T14	12278		T17	13
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1700010	1			T1	16		T12	99		T13	162
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	6372865	1			T33	45		T1	52		T11	890
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4579644	1			T33	66		T1	37		T11	843
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1710213	1			T12	78		T13	213		T14	7751
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2249940	1			T1	11		T12	110		T13	192
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	491549	1			T1	5		T14	12024		T17	2
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1695045	1			T12	78		T13	160		T14	7811
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	6378020	1			T33	65		T1	22		T11	817
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4565548	1			T33	46		T1	51		T11	916
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1712840	1			T12	85		T13	152		T14	7289
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	2251668	1			T1	25		T12	108		T13	215
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	490336	1			T1	7		T14	12943		T17	2
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1700844	1			T12	92		T13	204		T14	7882
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	6387973	1			T33	48		T1	33		T11	788
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4562619	1			T33	63		T1	39		T11	945
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1707500	1			T12	95		T13	191		T14	7384
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2254014	1			T1	15		T12	90		T13	206
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	493926	1			T1	13		T14	12844		T17	13
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1693224	1			T1	5		T12	94		T13	194
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	6369177	1			T33	58		T1	41		T11	781
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4574116	1			T33	53		T1	36		T11	952
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1712831	1			T1	9		T12	78		T13	192
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2249647	1			T1	4		T12	101		T13	200
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	491871	1			T1	7		T14	12227		T17	10
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1701614	1			T1	8		T12	110		T13	176

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal