Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[1]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[2]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[3]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[4]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[5]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[6]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[7]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[8]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[9]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[10]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[11]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[12]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[13]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[14]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[15]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[16]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[17]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[18]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[19]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[20]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[21]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[22]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[23]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[24]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[25]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[26]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[27]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[28]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[29]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[30]	17099256	1			T33	111		T1	105		T11	1733
bins_for_gpio_bits[31]	17099256	1			T33	111		T1	105		T11	1733

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

330844383

1

T33

1735

T1

1478

T11

27525

auto[1]

216331809

1

T33

1817

T1

1882

T11

27931

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

330836664

1

T33

1735

T1

1482

T11

27525

auto[1]

216339528

1

T33

1817

T1

1878

T11

27931

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	10033099	1			T33	64		T1	41		T11	833
bins_for_gpio_bits[0]	auto[0]	auto[1]	305602	1			T12	27		T13	47		T14	1409
bins_for_gpio_bits[0]	auto[1]	auto[0]	305822	1			T12	27		T13	47		T14	1402
bins_for_gpio_bits[0]	auto[1]	auto[1]	6454733	1			T33	47		T1	64		T11	900
bins_for_gpio_bits[1]	auto[0]	auto[0]	10029567	1			T33	67		T1	49		T11	876
bins_for_gpio_bits[1]	auto[0]	auto[1]	305600	1			T1	1		T12	21		T13	49
bins_for_gpio_bits[1]	auto[1]	auto[0]	305815	1			T1	1		T12	21		T13	49
bins_for_gpio_bits[1]	auto[1]	auto[1]	6458274	1			T33	44		T1	54		T11	857
bins_for_gpio_bits[2]	auto[0]	auto[0]	10031256	1			T33	38		T1	39		T11	881
bins_for_gpio_bits[2]	auto[0]	auto[1]	305302	1			T12	23		T13	55		T14	1371
bins_for_gpio_bits[2]	auto[1]	auto[0]	305569	1			T12	23		T13	55		T14	1365
bins_for_gpio_bits[2]	auto[1]	auto[1]	6457129	1			T33	73		T1	66		T11	852
bins_for_gpio_bits[3]	auto[0]	auto[0]	10036866	1			T33	52		T1	38		T11	919
bins_for_gpio_bits[3]	auto[0]	auto[1]	304840	1			T12	26		T13	48		T14	1369
bins_for_gpio_bits[3]	auto[1]	auto[0]	305078	1			T12	26		T13	48		T14	1359
bins_for_gpio_bits[3]	auto[1]	auto[1]	6452472	1			T33	59		T1	67		T11	814
bins_for_gpio_bits[4]	auto[0]	auto[0]	10032571	1			T33	48		T1	62		T11	903
bins_for_gpio_bits[4]	auto[0]	auto[1]	304676	1			T12	23		T13	47		T14	1408
bins_for_gpio_bits[4]	auto[1]	auto[0]	304941	1			T12	23		T13	47		T14	1404
bins_for_gpio_bits[4]	auto[1]	auto[1]	6457068	1			T33	63		T1	43		T11	830
bins_for_gpio_bits[5]	auto[0]	auto[0]	10026540	1			T33	61		T1	70		T11	875
bins_for_gpio_bits[5]	auto[0]	auto[1]	305195	1			T12	21		T13	51		T14	1386
bins_for_gpio_bits[5]	auto[1]	auto[0]	305466	1			T12	22		T13	51		T14	1384
bins_for_gpio_bits[5]	auto[1]	auto[1]	6462055	1			T33	50		T1	35		T11	858
bins_for_gpio_bits[6]	auto[0]	auto[0]	10030675	1			T33	53		T1	40		T11	842
bins_for_gpio_bits[6]	auto[0]	auto[1]	305071	1			T1	1		T12	27		T13	43
bins_for_gpio_bits[6]	auto[1]	auto[0]	305296	1			T1	1		T12	27		T13	43
bins_for_gpio_bits[6]	auto[1]	auto[1]	6458214	1			T33	58		T1	63		T11	891
bins_for_gpio_bits[7]	auto[0]	auto[0]	10031543	1			T33	49		T1	41		T11	925
bins_for_gpio_bits[7]	auto[0]	auto[1]	305977	1			T1	1		T12	19		T13	51
bins_for_gpio_bits[7]	auto[1]	auto[0]	306230	1			T12	19		T13	51		T14	1401
bins_for_gpio_bits[7]	auto[1]	auto[1]	6455506	1			T33	62		T1	63		T11	808
bins_for_gpio_bits[8]	auto[0]	auto[0]	10025906	1			T33	65		T1	49		T11	870
bins_for_gpio_bits[8]	auto[0]	auto[1]	304759	1			T12	26		T13	40		T14	1395
bins_for_gpio_bits[8]	auto[1]	auto[0]	304997	1			T12	27		T13	40		T14	1391
bins_for_gpio_bits[8]	auto[1]	auto[1]	6463594	1			T33	46		T1	56		T11	863
bins_for_gpio_bits[9]	auto[0]	auto[0]	10024508	1			T33	47		T1	35		T11	755
bins_for_gpio_bits[9]	auto[0]	auto[1]	305479	1			T12	20		T13	51		T14	1395
bins_for_gpio_bits[9]	auto[1]	auto[0]	305731	1			T12	20		T13	51		T14	1392
bins_for_gpio_bits[9]	auto[1]	auto[1]	6463538	1			T33	64		T1	70		T11	978
bins_for_gpio_bits[10]	auto[0]	auto[0]	10030897	1			T33	54		T1	33		T11	1015
bins_for_gpio_bits[10]	auto[0]	auto[1]	305021	1			T12	23		T13	47		T14	1415
bins_for_gpio_bits[10]	auto[1]	auto[0]	305261	1			T12	23		T13	48		T14	1408
bins_for_gpio_bits[10]	auto[1]	auto[1]	6458077	1			T33	57		T1	72		T11	718
bins_for_gpio_bits[11]	auto[0]	auto[0]	10037408	1			T33	59		T1	58		T11	744
bins_for_gpio_bits[11]	auto[0]	auto[1]	305322	1			T12	19		T13	45		T14	1454
bins_for_gpio_bits[11]	auto[1]	auto[0]	305553	1			T12	20		T13	45		T14	1442
bins_for_gpio_bits[11]	auto[1]	auto[1]	6450973	1			T33	52		T1	47		T11	989
bins_for_gpio_bits[12]	auto[0]	auto[0]	10029546	1			T33	54		T1	25		T11	885
bins_for_gpio_bits[12]	auto[0]	auto[1]	305170	1			T12	19		T13	46		T14	1408
bins_for_gpio_bits[12]	auto[1]	auto[0]	305425	1			T12	19		T13	46		T14	1407
bins_for_gpio_bits[12]	auto[1]	auto[1]	6459115	1			T33	57		T1	80		T11	848
bins_for_gpio_bits[13]	auto[0]	auto[0]	10031278	1			T33	50		T1	53		T11	854
bins_for_gpio_bits[13]	auto[0]	auto[1]	305727	1			T12	25		T13	42		T14	1385
bins_for_gpio_bits[13]	auto[1]	auto[0]	305967	1			T12	25		T13	42		T14	1377
bins_for_gpio_bits[13]	auto[1]	auto[1]	6456284	1			T33	61		T1	52		T11	879
bins_for_gpio_bits[14]	auto[0]	auto[0]	10046746	1			T33	54		T1	36		T11	813
bins_for_gpio_bits[14]	auto[0]	auto[1]	304873	1			T12	25		T13	52		T14	1441
bins_for_gpio_bits[14]	auto[1]	auto[0]	305123	1			T12	25		T13	52		T14	1433
bins_for_gpio_bits[14]	auto[1]	auto[1]	6442514	1			T33	57		T1	69		T11	920
bins_for_gpio_bits[15]	auto[0]	auto[0]	10031823	1			T33	57		T1	65		T11	957
bins_for_gpio_bits[15]	auto[0]	auto[1]	305117	1			T1	1		T12	24		T13	49
bins_for_gpio_bits[15]	auto[1]	auto[0]	305347	1			T12	24		T13	49		T14	1414
bins_for_gpio_bits[15]	auto[1]	auto[1]	6456969	1			T33	54		T1	39		T11	776
bins_for_gpio_bits[16]	auto[0]	auto[0]	10024770	1			T33	61		T1	29		T11	844
bins_for_gpio_bits[16]	auto[0]	auto[1]	305480	1			T12	23		T13	51		T14	1372
bins_for_gpio_bits[16]	auto[1]	auto[0]	305730	1			T12	24		T13	51		T14	1367
bins_for_gpio_bits[16]	auto[1]	auto[1]	6463276	1			T33	50		T1	76		T11	889
bins_for_gpio_bits[17]	auto[0]	auto[0]	10034047	1			T33	57		T1	59		T11	918
bins_for_gpio_bits[17]	auto[0]	auto[1]	305466	1			T1	1		T12	26		T13	59
bins_for_gpio_bits[17]	auto[1]	auto[0]	305660	1			T1	1		T12	27		T13	59
bins_for_gpio_bits[17]	auto[1]	auto[1]	6454083	1			T33	54		T1	44		T11	815
bins_for_gpio_bits[18]	auto[0]	auto[0]	10043021	1			T33	49		T1	34		T11	841
bins_for_gpio_bits[18]	auto[0]	auto[1]	304901	1			T12	21		T13	49		T14	1367
bins_for_gpio_bits[18]	auto[1]	auto[0]	305135	1			T12	21		T13	49		T14	1361
bins_for_gpio_bits[18]	auto[1]	auto[1]	6446199	1			T33	62		T1	71		T11	892
bins_for_gpio_bits[19]	auto[0]	auto[0]	10038320	1			T33	61		T1	61		T11	924
bins_for_gpio_bits[19]	auto[0]	auto[1]	304975	1			T12	20		T13	47		T14	1359
bins_for_gpio_bits[19]	auto[1]	auto[0]	305175	1			T12	20		T13	47		T14	1356
bins_for_gpio_bits[19]	auto[1]	auto[1]	6450786	1			T33	50		T1	44		T11	809
bins_for_gpio_bits[20]	auto[0]	auto[0]	10035258	1			T33	53		T1	51		T11	848
bins_for_gpio_bits[20]	auto[0]	auto[1]	305192	1			T12	19		T13	42		T14	1410
bins_for_gpio_bits[20]	auto[1]	auto[0]	305436	1			T12	19		T13	42		T14	1404
bins_for_gpio_bits[20]	auto[1]	auto[1]	6453370	1			T33	58		T1	54		T11	885
bins_for_gpio_bits[21]	auto[0]	auto[0]	10040277	1			T33	55		T1	60		T11	798
bins_for_gpio_bits[21]	auto[0]	auto[1]	304899	1			T12	25		T13	54		T14	1385
bins_for_gpio_bits[21]	auto[1]	auto[0]	305133	1			T12	25		T13	54		T14	1380
bins_for_gpio_bits[21]	auto[1]	auto[1]	6448947	1			T33	56		T1	45		T11	935
bins_for_gpio_bits[22]	auto[0]	auto[0]	10032833	1			T33	61		T1	47		T11	898
bins_for_gpio_bits[22]	auto[0]	auto[1]	306001	1			T1	1		T12	20		T13	55
bins_for_gpio_bits[22]	auto[1]	auto[0]	306223	1			T1	1		T12	20		T13	55
bins_for_gpio_bits[22]	auto[1]	auto[1]	6454199	1			T33	50		T1	56		T11	835
bins_for_gpio_bits[23]	auto[0]	auto[0]	10032684	1			T33	44		T1	54		T11	869
bins_for_gpio_bits[23]	auto[0]	auto[1]	305418	1			T1	1		T12	20		T13	51
bins_for_gpio_bits[23]	auto[1]	auto[0]	305700	1			T12	20		T13	51		T14	1398
bins_for_gpio_bits[23]	auto[1]	auto[1]	6455454	1			T33	67		T1	50		T11	864
bins_for_gpio_bits[24]	auto[0]	auto[0]	10034180	1			T33	59		T1	17		T11	822
bins_for_gpio_bits[24]	auto[0]	auto[1]	305505	1			T12	24		T13	52		T14	1398
bins_for_gpio_bits[24]	auto[1]	auto[0]	305769	1			T12	24		T13	52		T14	1392
bins_for_gpio_bits[24]	auto[1]	auto[1]	6453802	1			T33	52		T1	88		T11	911
bins_for_gpio_bits[25]	auto[0]	auto[0]	10032921	1			T33	44		T1	34		T11	870
bins_for_gpio_bits[25]	auto[0]	auto[1]	305140	1			T12	22		T13	49		T14	1424
bins_for_gpio_bits[25]	auto[1]	auto[0]	305353	1			T12	22		T13	50		T14	1420
bins_for_gpio_bits[25]	auto[1]	auto[1]	6455842	1			T33	67		T1	71		T11	863
bins_for_gpio_bits[26]	auto[0]	auto[0]	10037521	1			T33	52		T1	53		T11	870
bins_for_gpio_bits[26]	auto[0]	auto[1]	305450	1			T12	20		T13	45		T14	1384
bins_for_gpio_bits[26]	auto[1]	auto[0]	305746	1			T12	20		T13	45		T14	1380
bins_for_gpio_bits[26]	auto[1]	auto[1]	6450539	1			T33	59		T1	52		T11	863
bins_for_gpio_bits[27]	auto[0]	auto[0]	10036937	1			T33	51		T1	29		T11	800
bins_for_gpio_bits[27]	auto[0]	auto[1]	305766	1			T12	23		T13	47		T14	1424
bins_for_gpio_bits[27]	auto[1]	auto[0]	306016	1			T12	24		T13	47		T14	1417
bins_for_gpio_bits[27]	auto[1]	auto[1]	6450537	1			T33	60		T1	76		T11	933
bins_for_gpio_bits[28]	auto[0]	auto[0]	10027765	1			T33	45		T1	63		T11	890
bins_for_gpio_bits[28]	auto[0]	auto[1]	305010	1			T12	21		T13	44		T14	1467
bins_for_gpio_bits[28]	auto[1]	auto[0]	305253	1			T12	21		T13	44		T14	1458
bins_for_gpio_bits[28]	auto[1]	auto[1]	6461228	1			T33	66		T1	42		T11	843
bins_for_gpio_bits[29]	auto[0]	auto[0]	10036012	1			T33	65		T1	47		T11	817
bins_for_gpio_bits[29]	auto[0]	auto[1]	306272	1			T12	21		T13	44		T14	1378
bins_for_gpio_bits[29]	auto[1]	auto[0]	306516	1			T12	21		T13	44		T14	1372
bins_for_gpio_bits[29]	auto[1]	auto[1]	6450456	1			T33	46		T1	58		T11	916
bins_for_gpio_bits[30]	auto[0]	auto[0]	10044821	1			T33	48		T1	48		T11	788
bins_for_gpio_bits[30]	auto[0]	auto[1]	304416	1			T12	20		T13	49		T14	1368
bins_for_gpio_bits[30]	auto[1]	auto[0]	304666	1			T12	20		T13	49		T14	1363
bins_for_gpio_bits[30]	auto[1]	auto[1]	6445353	1			T33	63		T1	57		T11	945
bins_for_gpio_bits[31]	auto[0]	auto[0]	10026157	1			T33	58		T1	54		T11	781
bins_for_gpio_bits[31]	auto[0]	auto[1]	305289	1			T1	1		T12	24		T13	48
bins_for_gpio_bits[31]	auto[1]	auto[0]	305498	1			T12	24		T13	48		T14	1421
bins_for_gpio_bits[31]	auto[1]	auto[1]	6462312	1			T33	53		T1	50		T11	952