Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9798994 |
1 |
|
|
T33 |
76 |
|
T1 |
60 |
|
T11 |
1733 |
| auto[1] |
7608921 |
1 |
|
|
T33 |
96 |
|
T1 |
19 |
|
T14 |
38917 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16428232 |
1 |
|
|
T33 |
165 |
|
T1 |
79 |
|
T11 |
1733 |
| auto[1] |
979683 |
1 |
|
|
T33 |
7 |
|
T14 |
5290 |
|
T15 |
302 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9786404 |
1 |
|
|
T33 |
95 |
|
T1 |
67 |
|
T11 |
1733 |
| auto[1] |
7621511 |
1 |
|
|
T33 |
77 |
|
T1 |
12 |
|
T14 |
38864 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3321144 |
1 |
|
|
T33 |
21 |
|
T1 |
7 |
|
T14 |
16509 |
| auto[1] |
auto[0] |
auto[1] |
489669 |
1 |
|
|
T33 |
4 |
|
T14 |
2657 |
|
T15 |
122 |
| auto[1] |
auto[1] |
auto[0] |
3320684 |
1 |
|
|
T33 |
49 |
|
T1 |
5 |
|
T14 |
17065 |
| auto[1] |
auto[1] |
auto[1] |
490014 |
1 |
|
|
T33 |
3 |
|
T14 |
2633 |
|
T15 |
180 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9829799 |
1 |
|
|
T33 |
72 |
|
T1 |
36 |
|
T11 |
1733 |
| auto[1] |
7578116 |
1 |
|
|
T33 |
100 |
|
T1 |
43 |
|
T14 |
39532 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16430127 |
1 |
|
|
T33 |
164 |
|
T1 |
78 |
|
T11 |
1733 |
| auto[1] |
977788 |
1 |
|
|
T33 |
8 |
|
T1 |
1 |
|
T14 |
5126 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9823388 |
1 |
|
|
T33 |
64 |
|
T1 |
52 |
|
T11 |
1733 |
| auto[1] |
7584527 |
1 |
|
|
T33 |
108 |
|
T1 |
27 |
|
T14 |
37459 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3306484 |
1 |
|
|
T33 |
39 |
|
T1 |
7 |
|
T14 |
15981 |
| auto[1] |
auto[0] |
auto[1] |
489017 |
1 |
|
|
T33 |
3 |
|
T14 |
2583 |
|
T15 |
119 |
| auto[1] |
auto[1] |
auto[0] |
3300255 |
1 |
|
|
T33 |
61 |
|
T1 |
19 |
|
T14 |
16352 |
| auto[1] |
auto[1] |
auto[1] |
488771 |
1 |
|
|
T33 |
5 |
|
T1 |
1 |
|
T14 |
2543 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9828727 |
1 |
|
|
T33 |
97 |
|
T1 |
59 |
|
T11 |
1733 |
| auto[1] |
7579188 |
1 |
|
|
T33 |
75 |
|
T1 |
20 |
|
T14 |
40098 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16435961 |
1 |
|
|
T33 |
161 |
|
T1 |
79 |
|
T11 |
1733 |
| auto[1] |
971954 |
1 |
|
|
T33 |
11 |
|
T14 |
5344 |
|
T15 |
252 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9853985 |
1 |
|
|
T33 |
32 |
|
T1 |
62 |
|
T11 |
1733 |
| auto[1] |
7553930 |
1 |
|
|
T33 |
140 |
|
T1 |
17 |
|
T14 |
38375 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3315626 |
1 |
|
|
T33 |
65 |
|
T1 |
8 |
|
T14 |
15752 |
| auto[1] |
auto[0] |
auto[1] |
489201 |
1 |
|
|
T33 |
6 |
|
T14 |
2528 |
|
T15 |
144 |
| auto[1] |
auto[1] |
auto[0] |
3266350 |
1 |
|
|
T33 |
64 |
|
T1 |
9 |
|
T14 |
17279 |
| auto[1] |
auto[1] |
auto[1] |
482753 |
1 |
|
|
T33 |
5 |
|
T14 |
2816 |
|
T15 |
108 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9808654 |
1 |
|
|
T33 |
83 |
|
T1 |
54 |
|
T11 |
1733 |
| auto[1] |
7599261 |
1 |
|
|
T33 |
89 |
|
T1 |
25 |
|
T14 |
38900 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16431250 |
1 |
|
|
T33 |
163 |
|
T1 |
79 |
|
T11 |
1733 |
| auto[1] |
976665 |
1 |
|
|
T33 |
9 |
|
T14 |
5279 |
|
T15 |
294 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9829317 |
1 |
|
|
T33 |
79 |
|
T1 |
50 |
|
T11 |
1733 |
| auto[1] |
7578598 |
1 |
|
|
T33 |
93 |
|
T1 |
29 |
|
T14 |
38070 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3301107 |
1 |
|
|
T33 |
52 |
|
T1 |
17 |
|
T14 |
16864 |
| auto[1] |
auto[0] |
auto[1] |
487918 |
1 |
|
|
T33 |
5 |
|
T14 |
2694 |
|
T15 |
133 |
| auto[1] |
auto[1] |
auto[0] |
3300826 |
1 |
|
|
T33 |
32 |
|
T1 |
12 |
|
T14 |
15927 |
| auto[1] |
auto[1] |
auto[1] |
488747 |
1 |
|
|
T33 |
4 |
|
T14 |
2585 |
|
T15 |
161 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9824388 |
1 |
|
|
T33 |
166 |
|
T1 |
53 |
|
T11 |
1733 |
| auto[1] |
7583527 |
1 |
|
|
T33 |
6 |
|
T1 |
26 |
|
T14 |
37599 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16435172 |
1 |
|
|
T33 |
166 |
|
T1 |
79 |
|
T11 |
1733 |
| auto[1] |
972743 |
1 |
|
|
T33 |
6 |
|
T14 |
5385 |
|
T15 |
289 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9851448 |
1 |
|
|
T33 |
130 |
|
T1 |
67 |
|
T11 |
1733 |
| auto[1] |
7556467 |
1 |
|
|
T33 |
42 |
|
T1 |
12 |
|
T14 |
38962 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3300921 |
1 |
|
|
T33 |
36 |
|
T1 |
11 |
|
T14 |
17600 |
| auto[1] |
auto[0] |
auto[1] |
489556 |
1 |
|
|
T33 |
6 |
|
T14 |
2900 |
|
T15 |
118 |
| auto[1] |
auto[1] |
auto[0] |
3282803 |
1 |
|
|
T1 |
1 |
|
T14 |
15977 |
|
T15 |
705 |
| auto[1] |
auto[1] |
auto[1] |
483187 |
1 |
|
|
T14 |
2485 |
|
T15 |
171 |
|
T16 |
30 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9814122 |
1 |
|
|
T33 |
93 |
|
T1 |
55 |
|
T11 |
1733 |
| auto[1] |
7593793 |
1 |
|
|
T33 |
79 |
|
T1 |
24 |
|
T14 |
39423 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16429410 |
1 |
|
|
T33 |
169 |
|
T1 |
79 |
|
T11 |
1733 |
| auto[1] |
978505 |
1 |
|
|
T33 |
3 |
|
T14 |
5386 |
|
T15 |
273 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9814060 |
1 |
|
|
T33 |
118 |
|
T1 |
47 |
|
T11 |
1733 |
| auto[1] |
7593855 |
1 |
|
|
T33 |
54 |
|
T1 |
32 |
|
T14 |
38858 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3304738 |
1 |
|
|
T33 |
28 |
|
T1 |
23 |
|
T14 |
15961 |
| auto[1] |
auto[0] |
auto[1] |
489152 |
1 |
|
|
T33 |
1 |
|
T14 |
2586 |
|
T15 |
152 |
| auto[1] |
auto[1] |
auto[0] |
3310612 |
1 |
|
|
T33 |
23 |
|
T1 |
9 |
|
T14 |
17511 |
| auto[1] |
auto[1] |
auto[1] |
489353 |
1 |
|
|
T33 |
2 |
|
T14 |
2800 |
|
T15 |
121 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9775940 |
1 |
|
|
T33 |
104 |
|
T1 |
57 |
|
T11 |
1733 |
| auto[1] |
7631975 |
1 |
|
|
T33 |
68 |
|
T1 |
22 |
|
T14 |
40140 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16426202 |
1 |
|
|
T33 |
161 |
|
T1 |
78 |
|
T11 |
1733 |
| auto[1] |
981713 |
1 |
|
|
T33 |
11 |
|
T1 |
1 |
|
T14 |
5318 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9790103 |
1 |
|
|
T33 |
59 |
|
T1 |
57 |
|
T11 |
1733 |
| auto[1] |
7617812 |
1 |
|
|
T33 |
113 |
|
T1 |
22 |
|
T14 |
38749 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3292203 |
1 |
|
|
T33 |
64 |
|
T1 |
17 |
|
T14 |
16322 |
| auto[1] |
auto[0] |
auto[1] |
486454 |
1 |
|
|
T33 |
7 |
|
T1 |
1 |
|
T14 |
2706 |
| auto[1] |
auto[1] |
auto[0] |
3343896 |
1 |
|
|
T33 |
38 |
|
T1 |
4 |
|
T14 |
17109 |
| auto[1] |
auto[1] |
auto[1] |
495259 |
1 |
|
|
T33 |
4 |
|
T14 |
2612 |
|
T15 |
118 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9820504 |
1 |
|
|
T33 |
73 |
|
T1 |
65 |
|
T11 |
1733 |
| auto[1] |
7587411 |
1 |
|
|
T33 |
99 |
|
T1 |
14 |
|
T14 |
39457 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16424555 |
1 |
|
|
T33 |
161 |
|
T1 |
78 |
|
T11 |
1733 |
| auto[1] |
983360 |
1 |
|
|
T33 |
11 |
|
T1 |
1 |
|
T14 |
5225 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9781000 |
1 |
|
|
T33 |
88 |
|
T1 |
61 |
|
T11 |
1733 |
| auto[1] |
7626915 |
1 |
|
|
T33 |
84 |
|
T1 |
18 |
|
T14 |
37857 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3344235 |
1 |
|
|
T33 |
29 |
|
T1 |
12 |
|
T14 |
16705 |
| auto[1] |
auto[0] |
auto[1] |
495414 |
1 |
|
|
T33 |
8 |
|
T1 |
1 |
|
T14 |
2706 |
| auto[1] |
auto[1] |
auto[0] |
3299320 |
1 |
|
|
T33 |
44 |
|
T1 |
5 |
|
T14 |
15927 |
| auto[1] |
auto[1] |
auto[1] |
487946 |
1 |
|
|
T33 |
3 |
|
T14 |
2519 |
|
T15 |
164 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9824929 |
1 |
|
|
T33 |
87 |
|
T1 |
54 |
|
T11 |
1733 |
| auto[1] |
7582986 |
1 |
|
|
T33 |
85 |
|
T1 |
25 |
|
T14 |
38248 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16429766 |
1 |
|
|
T33 |
170 |
|
T1 |
78 |
|
T11 |
1733 |
| auto[1] |
978149 |
1 |
|
|
T33 |
2 |
|
T1 |
1 |
|
T14 |
5709 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9811395 |
1 |
|
|
T33 |
114 |
|
T1 |
54 |
|
T11 |
1733 |
| auto[1] |
7596520 |
1 |
|
|
T33 |
58 |
|
T1 |
25 |
|
T14 |
41322 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3306114 |
1 |
|
|
T33 |
30 |
|
T1 |
15 |
|
T14 |
18666 |
| auto[1] |
auto[0] |
auto[1] |
488887 |
1 |
|
|
T33 |
1 |
|
T1 |
1 |
|
T14 |
2998 |
| auto[1] |
auto[1] |
auto[0] |
3312257 |
1 |
|
|
T33 |
26 |
|
T1 |
9 |
|
T14 |
16947 |
| auto[1] |
auto[1] |
auto[1] |
489262 |
1 |
|
|
T33 |
1 |
|
T14 |
2711 |
|
T15 |
103 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9813733 |
1 |
|
|
T33 |
126 |
|
T1 |
48 |
|
T11 |
1733 |
| auto[1] |
7594182 |
1 |
|
|
T33 |
46 |
|
T1 |
31 |
|
T14 |
42639 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16434711 |
1 |
|
|
T33 |
160 |
|
T1 |
79 |
|
T11 |
1733 |
| auto[1] |
973204 |
1 |
|
|
T33 |
12 |
|
T14 |
5380 |
|
T15 |
301 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9851592 |
1 |
|
|
T33 |
67 |
|
T1 |
33 |
|
T11 |
1733 |
| auto[1] |
7556323 |
1 |
|
|
T33 |
105 |
|
T1 |
46 |
|
T14 |
38383 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3290625 |
1 |
|
|
T33 |
52 |
|
T1 |
28 |
|
T14 |
14787 |
| auto[1] |
auto[0] |
auto[1] |
486292 |
1 |
|
|
T33 |
7 |
|
T14 |
2279 |
|
T15 |
157 |
| auto[1] |
auto[1] |
auto[0] |
3292494 |
1 |
|
|
T33 |
41 |
|
T1 |
18 |
|
T14 |
18216 |
| auto[1] |
auto[1] |
auto[1] |
486912 |
1 |
|
|
T33 |
5 |
|
T14 |
3101 |
|
T15 |
144 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9793205 |
1 |
|
|
T33 |
70 |
|
T1 |
42 |
|
T11 |
1733 |
| auto[1] |
7614710 |
1 |
|
|
T33 |
102 |
|
T1 |
37 |
|
T14 |
39271 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16430762 |
1 |
|
|
T33 |
166 |
|
T1 |
79 |
|
T11 |
1733 |
| auto[1] |
977153 |
1 |
|
|
T33 |
6 |
|
T14 |
5243 |
|
T15 |
267 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9818844 |
1 |
|
|
T33 |
73 |
|
T1 |
63 |
|
T11 |
1733 |
| auto[1] |
7589071 |
1 |
|
|
T33 |
99 |
|
T1 |
16 |
|
T14 |
38313 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3294193 |
1 |
|
|
T33 |
40 |
|
T1 |
11 |
|
T14 |
15953 |
| auto[1] |
auto[0] |
auto[1] |
486736 |
1 |
|
|
T33 |
3 |
|
T14 |
2615 |
|
T15 |
127 |
| auto[1] |
auto[1] |
auto[0] |
3317725 |
1 |
|
|
T33 |
53 |
|
T1 |
5 |
|
T14 |
17117 |
| auto[1] |
auto[1] |
auto[1] |
490417 |
1 |
|
|
T33 |
3 |
|
T14 |
2628 |
|
T15 |
140 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9800538 |
1 |
|
|
T33 |
89 |
|
T1 |
53 |
|
T11 |
1733 |
| auto[1] |
7607377 |
1 |
|
|
T33 |
83 |
|
T1 |
26 |
|
T14 |
39971 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16423994 |
1 |
|
|
T33 |
163 |
|
T1 |
79 |
|
T11 |
1733 |
| auto[1] |
983921 |
1 |
|
|
T33 |
9 |
|
T14 |
5362 |
|
T15 |
284 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9786504 |
1 |
|
|
T33 |
66 |
|
T1 |
49 |
|
T11 |
1733 |
| auto[1] |
7621411 |
1 |
|
|
T33 |
106 |
|
T1 |
30 |
|
T14 |
38611 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3308860 |
1 |
|
|
T33 |
57 |
|
T1 |
12 |
|
T14 |
15711 |
| auto[1] |
auto[0] |
auto[1] |
490674 |
1 |
|
|
T33 |
4 |
|
T14 |
2462 |
|
T15 |
173 |
| auto[1] |
auto[1] |
auto[0] |
3328630 |
1 |
|
|
T33 |
40 |
|
T1 |
18 |
|
T14 |
17538 |
| auto[1] |
auto[1] |
auto[1] |
493247 |
1 |
|
|
T33 |
5 |
|
T14 |
2900 |
|
T15 |
111 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9824498 |
1 |
|
|
T33 |
106 |
|
T1 |
40 |
|
T11 |
1733 |
| auto[1] |
7583417 |
1 |
|
|
T33 |
66 |
|
T1 |
39 |
|
T14 |
40024 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16429412 |
1 |
|
|
T33 |
167 |
|
T1 |
79 |
|
T11 |
1733 |
| auto[1] |
978503 |
1 |
|
|
T33 |
5 |
|
T14 |
5643 |
|
T15 |
277 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9816914 |
1 |
|
|
T33 |
89 |
|
T1 |
43 |
|
T11 |
1733 |
| auto[1] |
7591001 |
1 |
|
|
T33 |
83 |
|
T1 |
36 |
|
T14 |
40911 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3301208 |
1 |
|
|
T33 |
51 |
|
T1 |
19 |
|
T14 |
16391 |
| auto[1] |
auto[0] |
auto[1] |
488227 |
1 |
|
|
T33 |
4 |
|
T14 |
2620 |
|
T15 |
181 |
| auto[1] |
auto[1] |
auto[0] |
3311290 |
1 |
|
|
T33 |
27 |
|
T1 |
17 |
|
T14 |
18877 |
| auto[1] |
auto[1] |
auto[1] |
490276 |
1 |
|
|
T33 |
1 |
|
T14 |
3023 |
|
T15 |
96 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9823901 |
1 |
|
|
T33 |
67 |
|
T1 |
44 |
|
T11 |
1733 |
| auto[1] |
7584014 |
1 |
|
|
T33 |
105 |
|
T1 |
35 |
|
T14 |
37630 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16428553 |
1 |
|
|
T33 |
166 |
|
T1 |
79 |
|
T11 |
1733 |
| auto[1] |
979362 |
1 |
|
|
T33 |
6 |
|
T14 |
5723 |
|
T15 |
331 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9806881 |
1 |
|
|
T33 |
58 |
|
T1 |
66 |
|
T11 |
1733 |
| auto[1] |
7601034 |
1 |
|
|
T33 |
114 |
|
T1 |
13 |
|
T14 |
41394 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3320343 |
1 |
|
|
T33 |
49 |
|
T1 |
9 |
|
T14 |
19406 |
| auto[1] |
auto[0] |
auto[1] |
492101 |
1 |
|
|
T33 |
2 |
|
T14 |
3168 |
|
T15 |
166 |
| auto[1] |
auto[1] |
auto[0] |
3301329 |
1 |
|
|
T33 |
59 |
|
T1 |
4 |
|
T14 |
16265 |
| auto[1] |
auto[1] |
auto[1] |
487261 |
1 |
|
|
T33 |
4 |
|
T14 |
2555 |
|
T15 |
165 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9846044 |
1 |
|
|
T33 |
96 |
|
T1 |
59 |
|
T11 |
1733 |
| auto[1] |
7561871 |
1 |
|
|
T33 |
76 |
|
T1 |
20 |
|
T14 |
36614 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16428252 |
1 |
|
|
T33 |
167 |
|
T1 |
78 |
|
T11 |
1733 |
| auto[1] |
979663 |
1 |
|
|
T33 |
5 |
|
T1 |
1 |
|
T14 |
5683 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9800851 |
1 |
|
|
T33 |
95 |
|
T1 |
54 |
|
T11 |
1733 |
| auto[1] |
7607064 |
1 |
|
|
T33 |
77 |
|
T1 |
25 |
|
T14 |
40259 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3323969 |
1 |
|
|
T33 |
24 |
|
T1 |
18 |
|
T14 |
18613 |
| auto[1] |
auto[0] |
auto[1] |
492862 |
1 |
|
|
T33 |
1 |
|
T1 |
1 |
|
T14 |
3141 |
| auto[1] |
auto[1] |
auto[0] |
3303432 |
1 |
|
|
T33 |
48 |
|
T1 |
6 |
|
T14 |
15963 |
| auto[1] |
auto[1] |
auto[1] |
486801 |
1 |
|
|
T33 |
4 |
|
T14 |
2542 |
|
T15 |
124 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9797387 |
1 |
|
|
T33 |
115 |
|
T1 |
67 |
|
T11 |
1733 |
| auto[1] |
7610528 |
1 |
|
|
T33 |
57 |
|
T1 |
12 |
|
T14 |
39149 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16425455 |
1 |
|
|
T33 |
158 |
|
T1 |
78 |
|
T11 |
1733 |
| auto[1] |
982460 |
1 |
|
|
T33 |
14 |
|
T1 |
1 |
|
T14 |
5226 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9804665 |
1 |
|
|
T33 |
40 |
|
T1 |
66 |
|
T11 |
1733 |
| auto[1] |
7603250 |
1 |
|
|
T33 |
132 |
|
T1 |
13 |
|
T14 |
38241 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3292060 |
1 |
|
|
T33 |
84 |
|
T1 |
8 |
|
T14 |
16019 |
| auto[1] |
auto[0] |
auto[1] |
487992 |
1 |
|
|
T33 |
11 |
|
T1 |
1 |
|
T14 |
2552 |
| auto[1] |
auto[1] |
auto[0] |
3328730 |
1 |
|
|
T33 |
34 |
|
T1 |
4 |
|
T14 |
16996 |
| auto[1] |
auto[1] |
auto[1] |
494468 |
1 |
|
|
T33 |
3 |
|
T14 |
2674 |
|
T15 |
177 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9835726 |
1 |
|
|
T33 |
120 |
|
T1 |
54 |
|
T11 |
1733 |
| auto[1] |
7572189 |
1 |
|
|
T33 |
52 |
|
T1 |
25 |
|
T14 |
39346 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16427026 |
1 |
|
|
T33 |
170 |
|
T1 |
78 |
|
T11 |
1733 |
| auto[1] |
980889 |
1 |
|
|
T33 |
2 |
|
T1 |
1 |
|
T14 |
5178 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9805191 |
1 |
|
|
T33 |
145 |
|
T1 |
63 |
|
T11 |
1733 |
| auto[1] |
7602724 |
1 |
|
|
T33 |
27 |
|
T1 |
16 |
|
T14 |
38130 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3313090 |
1 |
|
|
T33 |
21 |
|
T1 |
8 |
|
T14 |
16599 |
| auto[1] |
auto[0] |
auto[1] |
490648 |
1 |
|
|
T33 |
1 |
|
T14 |
2649 |
|
T15 |
95 |
| auto[1] |
auto[1] |
auto[0] |
3308745 |
1 |
|
|
T33 |
4 |
|
T1 |
7 |
|
T14 |
16353 |
| auto[1] |
auto[1] |
auto[1] |
490241 |
1 |
|
|
T33 |
1 |
|
T1 |
1 |
|
T14 |
2529 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9819242 |
1 |
|
|
T33 |
54 |
|
T1 |
58 |
|
T11 |
1733 |
| auto[1] |
7588673 |
1 |
|
|
T33 |
118 |
|
T1 |
21 |
|
T14 |
37785 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16432959 |
1 |
|
|
T33 |
160 |
|
T1 |
78 |
|
T11 |
1733 |
| auto[1] |
974956 |
1 |
|
|
T33 |
12 |
|
T1 |
1 |
|
T14 |
5163 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9831004 |
1 |
|
|
T33 |
37 |
|
T1 |
56 |
|
T11 |
1733 |
| auto[1] |
7576911 |
1 |
|
|
T33 |
135 |
|
T1 |
23 |
|
T14 |
37752 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3308793 |
1 |
|
|
T33 |
37 |
|
T1 |
15 |
|
T14 |
15965 |
| auto[1] |
auto[0] |
auto[1] |
489919 |
1 |
|
|
T33 |
5 |
|
T14 |
2406 |
|
T15 |
155 |
| auto[1] |
auto[1] |
auto[0] |
3293162 |
1 |
|
|
T33 |
86 |
|
T1 |
7 |
|
T14 |
16624 |
| auto[1] |
auto[1] |
auto[1] |
485037 |
1 |
|
|
T33 |
7 |
|
T1 |
1 |
|
T14 |
2757 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9814271 |
1 |
|
|
T33 |
89 |
|
T1 |
40 |
|
T11 |
1733 |
| auto[1] |
7593644 |
1 |
|
|
T33 |
83 |
|
T1 |
39 |
|
T14 |
39995 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16430242 |
1 |
|
|
T33 |
160 |
|
T1 |
79 |
|
T11 |
1733 |
| auto[1] |
977673 |
1 |
|
|
T33 |
12 |
|
T14 |
5605 |
|
T15 |
279 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9816972 |
1 |
|
|
T33 |
44 |
|
T1 |
57 |
|
T11 |
1733 |
| auto[1] |
7590943 |
1 |
|
|
T33 |
128 |
|
T1 |
22 |
|
T14 |
40450 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3310030 |
1 |
|
|
T33 |
52 |
|
T1 |
17 |
|
T14 |
16615 |
| auto[1] |
auto[0] |
auto[1] |
488452 |
1 |
|
|
T33 |
5 |
|
T14 |
2722 |
|
T15 |
120 |
| auto[1] |
auto[1] |
auto[0] |
3303240 |
1 |
|
|
T33 |
64 |
|
T1 |
5 |
|
T14 |
18230 |
| auto[1] |
auto[1] |
auto[1] |
489221 |
1 |
|
|
T33 |
7 |
|
T14 |
2883 |
|
T15 |
159 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9820614 |
1 |
|
|
T33 |
85 |
|
T1 |
62 |
|
T11 |
1733 |
| auto[1] |
7587301 |
1 |
|
|
T33 |
87 |
|
T1 |
17 |
|
T14 |
39473 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16433523 |
1 |
|
|
T33 |
163 |
|
T1 |
79 |
|
T11 |
1733 |
| auto[1] |
974392 |
1 |
|
|
T33 |
9 |
|
T14 |
5267 |
|
T15 |
318 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9850943 |
1 |
|
|
T33 |
56 |
|
T1 |
65 |
|
T11 |
1733 |
| auto[1] |
7556972 |
1 |
|
|
T33 |
116 |
|
T1 |
14 |
|
T14 |
39062 |