Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9797203 |
1 |
|
|
T33 |
87 |
|
T1 |
53 |
|
T11 |
1733 |
| auto[1] |
7610712 |
1 |
|
|
T33 |
85 |
|
T1 |
26 |
|
T14 |
37991 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16430587 |
1 |
|
|
T33 |
167 |
|
T1 |
78 |
|
T11 |
1733 |
| auto[1] |
977328 |
1 |
|
|
T33 |
5 |
|
T1 |
1 |
|
T14 |
5246 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9816853 |
1 |
|
|
T33 |
110 |
|
T1 |
43 |
|
T11 |
1733 |
| auto[1] |
7591062 |
1 |
|
|
T33 |
62 |
|
T1 |
36 |
|
T14 |
38745 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3299128 |
1 |
|
|
T33 |
29 |
|
T1 |
25 |
|
T14 |
17315 |
| auto[1] |
auto[0] |
auto[1] |
486715 |
1 |
|
|
T33 |
4 |
|
T14 |
2758 |
|
T15 |
124 |
| auto[1] |
auto[1] |
auto[0] |
3314606 |
1 |
|
|
T33 |
28 |
|
T1 |
10 |
|
T14 |
16184 |
| auto[1] |
auto[1] |
auto[1] |
490613 |
1 |
|
|
T33 |
1 |
|
T1 |
1 |
|
T14 |
2488 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |