Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9775641 |
1 |
|
|
T33 |
65 |
|
T1 |
44 |
|
T11 |
1733 |
| auto[1] |
7632274 |
1 |
|
|
T33 |
107 |
|
T1 |
35 |
|
T14 |
40845 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16429909 |
1 |
|
|
T33 |
164 |
|
T1 |
78 |
|
T11 |
1733 |
| auto[1] |
978006 |
1 |
|
|
T33 |
8 |
|
T1 |
1 |
|
T14 |
5393 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9821882 |
1 |
|
|
T33 |
80 |
|
T1 |
49 |
|
T11 |
1733 |
| auto[1] |
7586033 |
1 |
|
|
T33 |
92 |
|
T1 |
30 |
|
T14 |
38472 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3291144 |
1 |
|
|
T33 |
26 |
|
T1 |
18 |
|
T14 |
16187 |
| auto[1] |
auto[0] |
auto[1] |
486378 |
1 |
|
|
T33 |
3 |
|
T1 |
1 |
|
T14 |
2593 |
| auto[1] |
auto[1] |
auto[0] |
3316883 |
1 |
|
|
T33 |
58 |
|
T1 |
11 |
|
T14 |
16892 |
| auto[1] |
auto[1] |
auto[1] |
491628 |
1 |
|
|
T33 |
5 |
|
T14 |
2800 |
|
T15 |
196 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |