Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9796038 |
1 |
|
|
T33 |
144 |
|
T1 |
51 |
|
T11 |
1733 |
| auto[1] |
7611877 |
1 |
|
|
T33 |
28 |
|
T1 |
28 |
|
T14 |
37433 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16435254 |
1 |
|
|
T33 |
160 |
|
T1 |
79 |
|
T11 |
1733 |
| auto[1] |
972661 |
1 |
|
|
T33 |
12 |
|
T14 |
5265 |
|
T15 |
292 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9854127 |
1 |
|
|
T33 |
58 |
|
T1 |
54 |
|
T11 |
1733 |
| auto[1] |
7553788 |
1 |
|
|
T33 |
114 |
|
T1 |
25 |
|
T14 |
38629 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3276861 |
1 |
|
|
T33 |
90 |
|
T1 |
15 |
|
T14 |
17373 |
| auto[1] |
auto[0] |
auto[1] |
484093 |
1 |
|
|
T33 |
9 |
|
T14 |
2791 |
|
T15 |
142 |
| auto[1] |
auto[1] |
auto[0] |
3304266 |
1 |
|
|
T33 |
12 |
|
T1 |
10 |
|
T14 |
15991 |
| auto[1] |
auto[1] |
auto[1] |
488568 |
1 |
|
|
T33 |
3 |
|
T14 |
2474 |
|
T15 |
150 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |