Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9815936 |
1 |
|
|
T33 |
90 |
|
T1 |
60 |
|
T11 |
1733 |
| auto[1] |
7591979 |
1 |
|
|
T33 |
82 |
|
T1 |
19 |
|
T14 |
38187 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16427725 |
1 |
|
|
T33 |
168 |
|
T1 |
79 |
|
T11 |
1733 |
| auto[1] |
980190 |
1 |
|
|
T33 |
4 |
|
T14 |
5677 |
|
T15 |
326 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9799325 |
1 |
|
|
T33 |
110 |
|
T1 |
49 |
|
T11 |
1733 |
| auto[1] |
7608590 |
1 |
|
|
T33 |
62 |
|
T1 |
30 |
|
T14 |
40655 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3296075 |
1 |
|
|
T33 |
39 |
|
T1 |
30 |
|
T14 |
17842 |
| auto[1] |
auto[0] |
auto[1] |
486119 |
1 |
|
|
T33 |
1 |
|
T14 |
2930 |
|
T15 |
151 |
| auto[1] |
auto[1] |
auto[0] |
3332325 |
1 |
|
|
T33 |
19 |
|
T14 |
17136 |
|
T15 |
713 |
| auto[1] |
auto[1] |
auto[1] |
494071 |
1 |
|
|
T33 |
3 |
|
T14 |
2747 |
|
T15 |
175 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |