Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9818330 |
1 |
|
|
T33 |
43 |
|
T1 |
55 |
|
T11 |
1733 |
| auto[1] |
7589585 |
1 |
|
|
T33 |
129 |
|
T1 |
24 |
|
T14 |
39097 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16428516 |
1 |
|
|
T33 |
170 |
|
T1 |
78 |
|
T11 |
1733 |
| auto[1] |
979399 |
1 |
|
|
T33 |
2 |
|
T1 |
1 |
|
T14 |
5440 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9820195 |
1 |
|
|
T33 |
131 |
|
T1 |
45 |
|
T11 |
1733 |
| auto[1] |
7587720 |
1 |
|
|
T33 |
41 |
|
T1 |
34 |
|
T14 |
39022 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3319443 |
1 |
|
|
T33 |
7 |
|
T1 |
19 |
|
T14 |
16651 |
| auto[1] |
auto[0] |
auto[1] |
492097 |
1 |
|
|
T1 |
1 |
|
T14 |
2667 |
|
T15 |
166 |
| auto[1] |
auto[1] |
auto[0] |
3288878 |
1 |
|
|
T33 |
32 |
|
T1 |
14 |
|
T14 |
16931 |
| auto[1] |
auto[1] |
auto[1] |
487302 |
1 |
|
|
T33 |
2 |
|
T14 |
2773 |
|
T15 |
102 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |