Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9798994 |
1 |
|
|
T33 |
76 |
|
T1 |
60 |
|
T11 |
1733 |
| auto[1] |
7608921 |
1 |
|
|
T33 |
96 |
|
T1 |
19 |
|
T14 |
38917 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14318967 |
1 |
|
|
T33 |
112 |
|
T1 |
64 |
|
T11 |
1733 |
| auto[1] |
3088948 |
1 |
|
|
T33 |
60 |
|
T1 |
15 |
|
T14 |
23662 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9835218 |
1 |
|
|
T33 |
86 |
|
T1 |
52 |
|
T11 |
1733 |
| auto[1] |
7572697 |
1 |
|
|
T33 |
86 |
|
T1 |
27 |
|
T14 |
40144 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2233956 |
1 |
|
|
T33 |
18 |
|
T1 |
10 |
|
T14 |
8463 |
| auto[1] |
auto[0] |
auto[1] |
1544345 |
1 |
|
|
T33 |
20 |
|
T1 |
8 |
|
T14 |
12089 |
| auto[1] |
auto[1] |
auto[0] |
2249793 |
1 |
|
|
T33 |
8 |
|
T1 |
2 |
|
T14 |
8019 |
| auto[1] |
auto[1] |
auto[1] |
1544603 |
1 |
|
|
T33 |
40 |
|
T1 |
7 |
|
T14 |
11573 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |