Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9829799 |
1 |
|
|
T33 |
72 |
|
T1 |
36 |
|
T11 |
1733 |
| auto[1] |
7578116 |
1 |
|
|
T33 |
100 |
|
T1 |
43 |
|
T14 |
39532 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14328569 |
1 |
|
|
T33 |
139 |
|
T1 |
62 |
|
T11 |
1733 |
| auto[1] |
3079346 |
1 |
|
|
T33 |
33 |
|
T1 |
17 |
|
T14 |
21834 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9845592 |
1 |
|
|
T33 |
76 |
|
T1 |
59 |
|
T11 |
1733 |
| auto[1] |
7562323 |
1 |
|
|
T33 |
96 |
|
T1 |
20 |
|
T14 |
37747 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2238050 |
1 |
|
|
T33 |
31 |
|
T14 |
8053 |
|
T15 |
425 |
| auto[1] |
auto[0] |
auto[1] |
1539495 |
1 |
|
|
T33 |
15 |
|
T1 |
2 |
|
T14 |
10801 |
| auto[1] |
auto[1] |
auto[0] |
2244927 |
1 |
|
|
T33 |
32 |
|
T1 |
3 |
|
T14 |
7860 |
| auto[1] |
auto[1] |
auto[1] |
1539851 |
1 |
|
|
T33 |
18 |
|
T1 |
15 |
|
T14 |
11033 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |